P 6 F a m ily • D u a l In d e p e n d e n t B u s ( D IB ) ; • L 1 c a c h e ( i- c a c h e a n d d -c a c h e ):

Ed. AJProença,Arquitectura de Computadores, MICEI, UMinho, 2006/07

ICCA’07 8th Internal Conference on Computer Architecture

F A Q - 0 2

Quais as principais evoluções que se sentiram na arquitectura do IA32 desde oprimeiroPentiumatéao Pentium4 (o parceiro do Xeonque equipa a maioria dos nós docluster), ao nível da redução do impacto das memórias lentas? "From Pentium to Pentium 4: memory hierarchy evolution This communication describes and compares the evolution of technical features developed for IA32 processors -Pentium to Pentium 4 –to reduce the bottleneck memory. In previous years, the CPUs are increasing your clock rate and this feature was not followed by the memory technologies. But, the evolutions on hierarchy memory will permit to dream about more performance in future; the changes on caches memories are responsible for the main evolutions, such as, cache separated by data and instructions, dual independent bus, advanced transfer cache, new cacheabilityand execution trace cache." Rui BorgesJanuary 2007

F ro m P e n ti u m t o P e n ti u m 4 : m e m o ry h ie ra rc h y e v o lu ti o n

Rui Miguel Borges ICCA’07 Department of Informatics, University of Minho January 2007

C P U /M e m o ry G a p

January 2007

P 5 F a m ily • L 1 c a c h e s e p a ra te d b y d a ta a n d in s tr u c ti o n s ( p re -d e c o d e d i n s tr u c ti o n s ) • L 1 c a c h e w it h H a rv a rd a rc h it e c tu re : d a ta c a c h e ( L 1 d -c a c h e ) p lu s i n s tr u c ti o n c a c h e (L 1 i -c a c h e ) – 1 6 K B y te , 4 -w a y s e t a s s o c ia ti v e , 3 2 -b y te c a c h e l in e s iz e ; – 8 K B y te , 2 -w a y s e t a s s o c ia ti v e f o r e a rl ie r p ro c e s s o rs ; – w ri te -b a c k d a ta • L 2 u n if ie d c a c h e i s o ff -c h ip ; • T y p ic a lly 2 5 6 o r 5 1 2 K B y te , 4 -w a y s e t a s s o c ia ti v e , 3 2 b y te c a c h e l in e s iz e

January 2007

P 6 F a m ily • D u a l In d e p e n d e n t B u s ( D IB ) ; • L 1 c a c h e ( i- c a c h e a n d d -c a c h e ):

–16 KByte, 4 way set associative, 32 byte cache line size; –8 KBytes, 2-way set associative for earlier P6 processors;

• L 2 u n if ie d c a c h e :

–128 KByte, 256 KByte, 512 KByte, 1 MByteor 2 MByte, 4 way set associative, 32 byte cache line size; –On processor package -before Pentium III Katmai –On-chip after Pentium III Coppermine -Advanced Transfer Cache

• N e w C a c h e a b ili ty in s tr u c ti o n s ( P e n ti u m II I) ;

January 2007

P e n ti u m 4 • E x e c u ti o n T ra c e C a c h e ; • T ra c e c a c h e :

–12K micro-op, 8-way set associative;

• L 1 d -c a c h e :

–8 KByte, 4-way set associative, 64 byte cache line size;

• L 2 u n if ie d c a c h e :

–256 or 512 KByte, 8-way set associative, sectored, 64 byte cache line size; –Increase data transfer rate;

• L 3 u n if ie d c a c h e – P e n ti u m E x tr e me E d it io n • 5 1 2 K B y te o r 1 MB y te , 8 -w a y s e t a s s o c ia ti v e , s e c to re d , 6 4 b y te c a c h e l in e s iz e ;

January 2007

S e A R C H c lu s te r • T ra c e c a c h e – 1 2 K m ic ro -o p , 8 -w a y s e t a s s o c ia ti v e ; • L 1 d -c a c h e – 8 K B y te , 4 -w a y s e t a s s o c ia ti v e , 6 4 b y te c a c h e lin e s iz e ; • L 2 u n if ie d c a c h e – 2 /4 M b • L 3 – n o t e x is t • F S B 8 0 0 /1 3 3 3 M h z

January 2007

Q u e s ti o n s