Low Power Reversible Parallel Binary Adder/Subtractor

There are three major design goals in reversible logic. 1) The quantum cost, which is the number of 1*1 and 2*2 reversible calculations necessary to generate the

In the present paper we design the 4 input majority gate based on Low Power VLSI Design which provides low power consumption implemented on FPGA.After design the final architecture

The adder has been simulated using verilog HDL codes and mapped this design to the TSMC (180nm) implementation technology using the Synopsys Design Complier and calculated the

In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the

In this paper we design a reversible Half Subtractor circuit by Feynman gate using QCA Technology.. The half subtractor performs

The proposed Full adder can be implemented using combination of all optical reversible NOR logic gate and using all optical reversible NAND gate (NAND logic based

In this paper design the 4-bit Vedic multiplier using different adder and implementation 8-bit radix-2 FFT algorithm.. The paper is organized as follows: Section II

This can be done if the quantum cost and garbage output value of the digital circuits should be reduced which can only be possible by using reversible logic gates.. Peres