A NOVEL HIGH PRECISION LOW
POWER CURRENT MODE CMOS
WINNER-TAKE-ALL CIRCUIT
K.L.Baishnab, Amlan Nag, F.A.Talukdar, Members IEEE
ECE Dept, National institute of Technology Silchar, Assam India
Abstract: The design and simulation of winner-take –all Current Mode (WTA) circuit is proposed. Inputs
and outputs of the Circuits are current and voltage respectively, which makes the circuit appropriated for low voltage neural hardware computation. The circuit was designed and simulated using Cadence gpdk090. The proposed novel current mode CMOS WTA operates at 0.7v with resolution of 0.001nA and a dynamic range from input current 10nA---1µA, which are much better than existing realizations. It is also observed that dynamic range can be raised further with increasing of power supply. Simulation results along with appropriate mathematical relations are reported.
Key Words: Analog circuit, Current mode, WTA, Neural Networks hardware realization.
I. Introduction:
The Winner-take-all circuit, which chooses a winner from a group of input signals, is a basic and important building block for neural network hardware realization. WTA may be classified as current mode as well as voltage mode. In this work we proposed a novel current mode CMOS WTA. There are several structures of CM WTA circuits proposed in the literature [1]-[16]. Lazzaro et.al [1] 1998 was the pioneer in developing a current mode MOS implementation of the WTA and has been used by others both in weak and strong inversion region as discussed in the literature. The first current mode WTA circuit producing output current proportional to the value winning current was first introduced by Andreou et al. [2] in 1991 and Boahen et. Al [3]. However in 1993 positive feedback had been used by Poulique et. Al [4]. Several modifications to Lazzaro’s have been suggested in the past [6]- [7]. The circuit has been modified by Starzyk and Fang et. Al 1993 [6] by improving precision and speed. However In 1995, the circuit was further modified with feedback and inhibitition by Wilson and DeWeerth [7] and latter 1999, by Kalim and Wilson [8]. The performances of WTA circuits can be measured in terms of speed, accuracy and power consumption. A. Fish et. al [10], 2005 has done novel work making the circuit to work both on strong inversion as well as weak inversion with an impressive dynamic range, however the circuit causes lot of delay to learn the system. It is reported that a delay of around 300ns, under 3.3v supply voltage, apart from these the circuit possesses, a higher order of complexity. So this circuit is not suitable for certain applications where time of processing and power are the critical issues. So we proposed a novel current mode CMOS WTA in weak inversion region (sub threshold region) with supply voltage 0.7v which drastically improves power, and resolution (0.001nA) as well as speed (10ns) performance as compare to the Fang et. Al [6], where supply voltage 5 V and resolution 0.5µV and A. Fish et. al [11] where supply voltage 3.3 V and resolution 1 µA.
II. Current mode WTA Architectures
In order to described the proposed circuit we would like to review the Lazzaro’s1998 [1] circuit as well as Fang [5] 1993.
2.1 Lazzaro WTA circuit- The circuit shown in the figure 2.1 is the LIzzaro’s WTA circuit. It consists of N interfacing cells. Each cell contains two n-MOS transistors, these are MK1 and MK2 where as k=1, 2…N( number of
cells participating in the competition) . Each cell receives a unidirectional input current Ik (k=1...N) where N:
number of contending cells and transistors MK1 (k=1, N) of each of the cell shares the same gate to source voltage.
The circuit operates by choosing the maximum input current Im for a particular cell. The cell carrying highest current
Im would have highest Vm ( gate to source voltage of M2k ) this is due to the early effect at transistor M1 which is in
weak inversion. In weak inversion, the drain-source current for an nMOS device is as follows.
which leads to less resolution and speed of the circuit.
Fig-2.1 Lazzaro’s WTA circuit
2.2 Fang’s Modified circuit: In order to enhance the resolution and speed of the Lazzaro circuit, et. al. Fang [6]
has modified the circuit by the adding a current source to each of the cells. In the circuit in figure 2.2 transistor M3K
and M4K (k=1-N) formed current source in each of the cells. The motive behind the inclusion of the current source is
to introduce excitory feedback to every cell. The purpose of the current mirror in each cell is to copy the current through M2k to M1k. So with the inclusion of current source, current through the cell (M2M ) carrying maximum
current at the input grows more faster as compare to the M2k of other cells and eventually a time will come when
M2M copies entire biasing current ( IB) provided by the transistor MB and circuit stop competition as M1k and M2k
of the other cells entire into ohmic and cut-off region respectively. With inclusion of current source and suitably choosing the transistor parameters, Fang [6] improved the resolution. However in et. al. Fang [6] winning is all depending upon the rate of the growth of the winning cell as compare to the other contending cells, no extra inhibitory circuit to inhibit the loser cell more faster. We proposed a novel cell where we introduced an inhibitory feedback along with the exitory feedback in order to inhibits other cell more faster.
Fig-2.2 Lazzaro’s WTA circuit with current source
2.1 Proposed Circuit
In order to improve the resolution and speed of the Lazzaro’s circuit further, we have proposed a novel circuit by adding one more transistor M4k (k=1—N) in each of the cells as shown in the figure 2.3 . The motive behind the
inclusion is to inhibit the other cells faster by increasing the common voltage Vc to a higher value. The total impact
of the both excitory and inhibitory circuit make the entire system more faster, and it is observed that The transistor M4m joins with M2mto drive–out all the transistors M2k (k≠m) into cut-off and eventually all the M1k (k≠m) into
ohmic region and naturally competition stops with a significant improvement of the resolution.
Fig-2.3 the proposed circuit with excitory and inhibitory circuit.
II. Circuit description:
The circuit is as same of Fang circuit, the only difference in the inclusion of transistor M4 as shown in the figure 2.3 as well as optimized the transistor parameters to have impressive resolution as well as speed. Due to action of current source formed by M3 and M4, it will pump more current to the biasing transistor MB, which will experience early effect. Point to be notated that transistor MB needs to be set very clear fully so that transistor experience early effect in sub threshold. In the design the W/L of M1 is set, to its minimum value so that VD should not get any
assistance from M1to increase further and also it will experience a good amount of early effect. ∆ 1 / ∆ / 1 . (2)
Where the first parenthesized term in the equation (2) stands for gain factor, that describes how sensitive cell is with respect to the input difference and “ Ve ” stands early voltage, Ibais stands for bias voltage when Iin1=Iin2. So larger
minimum value of 0A in the same time of 5 ns. So for input difference of 0.001nA the response time of the circuit is only 5 ns. Again in the fig-3.4—fig-3.6, show very impressive result, with the increase of current from 90nA-100µA, the response time reduces by 120ns, thus the learning time of the circuit decreases. On the other hands biasing are done in such a way that all M2 must be under sub threshold. So this novel circuit can be extensively used utilized for low power as well as high speed system.
TABLE-1
Simulation results of varied supply voltage Range of input
current
Supply Voltage 10nA----1µA 0.7v 10nA---- 5µA 0.9v
10nA--- 100µA 1.8v
Fig-3.1 transient response of two cells
Fig-3.2 transient response of two cells for supply voltage 0.7v
Fig-3.3 transient response of two cells for supply voltage 1.8v
Fig-3.4transient response of two cells for supply voltage 0.7v
Fig-3.5transient response of two cells for supply voltage 0.7v
Fig-3.6transient response of two cells for supply voltage 0.7v
Fig-3.7transient response of two cells for supply voltage 0.7vObservation:
TABLE-II
Major characteristics of existing WTA circuit
Parameter The proposed WTA
WTA[6] Fang
WTA[16] Taylor
WTA [11] Fish
Input Current Current Current Current
output Voltage Voltage Current Voltage
Input range
10nA----1µA Not reported 5µA-100µA 3-50nA
Suppply voltage 0.7V 5V 5 V 3.3V
Technology 90nm 2m 2.4m 0.35m
Again sources of power dissipation in CMOS devices are summarized by the following expression: P = 1/2 .C.VDD2.f. E(sw) + QSC.VDD.f .N + Ileak.VDD …(1)
where “P” denotes the total power dissipation, VDD is the supply voltage, and “f” is the frequency of operation. The
factor QSC represents the quantity of charge carried by the short-circuit current per transition. The third term in the
Eqn( 1) represents static power dissipation due to leakage current Ileak. Device source and drain diffusions from
So it is observed that power dissipation of a CMOS is directly proportional to the square of supply voltage. As power supply of the proposed circuit is reduced to 0.7 v, a huge improvement in term of harvesting of power can be achieved through the proposed circuit.
Conclusion:
We have presented a high speed and high resolution CM WTA circuit, described its operation and compared it to the WTA circuits previously published in the literature. A novel WTA circuit, each for different range of input currents, have been simulated in a standard cadence Spectra gpdk 90nm Technology. The circuit employs both inhibitory and excitory feedbacks based on input currents and simulation results shown a significant improvement in terms of speed and resolution and is suitable for wide range of input currents. However sub threshold matching issues and circuit operation with a large number of inputs is subject of further research. Dynamic range can be improved further is subject of further research. Exact Power dissipation needs be calculated.
Acknowledgement:
The authors wish to thank all the persons involved in the SMDP-II at NIT Silchar, India for their all way supports to carry-out the research work.
References:
[1] Lazzaro.J, Ryckebusch. S, Mahowald, M.A and MEAD. C.A “California Institute of Technology Pasadena CA 91125 Winner-take –all network of O(N) complexity “Advances in neural information processing systems, 1989
[2] Andreas G Andreou Mem,ber of IEEE A.Boahen, Aleksandra Pavasovic, Robert E. Jenkins, Kim Strohbehn “Current mode Subthreshold MOS circuits for Analog VLSI Neural Systems” IEEE Trasnsaction on Neural Networks Vol-2 No-2 March 1991.
[3] K.A.Boah, A.G.Andreou, P.O.Pouliquen and R.E.Jenkins, “Current-Mode based analog circuits for synthetic neural systems U.S Patent 5206541 Apr 27, 1993.
[4] Mead .C, “Analog VLSI and neural Systems” Addison Wesley Publishing Company 1989.
[5] P.O.Poulique, A.G.Andreou, K. Strohbehn and R> E.Jenkins “ An associative memory integration system for character recognisation in proceding 38th Midwest Symposium Circuit SystemsDetroit MI Aug 1993.
[6] J.A. Starzyk and X.Fang “CMOS current mode winner-take-all with both excitory and inhibitory feedback” IEEE Electronics letter 13th
May 1993 Vol-29 No-10.
[7] S.P.DeWaeerth and T.G.Morris “ CMOS current mode winner-take all circuit with distributed hysteresis “ Eletcronics Letter vol.31. No 13 pp1051-1053, 1995.
[8] D.M.Wilson and S.P.DeWeerth “Winning is not everything “in Proceeding ISCAS,1995 pp105-108.
[9] R.Kalim and D.M.Wilson , “ Semi-parallel rank order filtering in analog VLSI” in Proceeding IEEE ISCAS, 1999, vol-2 pp-232-235 [10] Nicolas Donckers, Carlos Dualibe and Michel Verleysen “A Current –Mode CMOS Loser-Take-all with minimum function for Neural
Computations. ISCAS -2000 IEEE international Symposium on Circuits and systems May-28-31 Geneva Switzerland.
[11] Alexander Fish, Vadim Milrud and Orly Yadid-Pechit “High speed and high precision current Winner-Take –All circuit” IEEE Transaction on ircuit and systems –II Vol-52, N0 3, March 2005.
[12] Moises E. Robinson, Hideki Yoneda and Edgar Sanchez-Sinenci0, Fellow IEEE “A modular CMOS design of a Hamming Network. IEEE transactions on neural Networks Vol.3. No.3 May-1992
[13] Prefetti. R “ Winner-take-all circuit for neural computing application” IEE Proc Pt.G.Vol 137 no 5, Oct 1990 pp 353-359
[14] Fang X “Small area, low power mixed-mode circuits for hybrid neural network application “PhD Dissertation, Ohio University 1994. [15] A.Fish Vadim Milrud, Orly Yadid “ High Speed and High Precision Current mode Winner-Take –All Circuit” IEEE Transaction on Circuits
and Systems-II Vol-52 No: 3 2005.
