VLSI IMPLEMENTATION OF AN
ANALOG MULTIPLIER FOR MODEM
SRIVIDYA .P
Asst Prof, Dept of ECE, SJBIT, Kengeri, Bangalore, India.
KR REKHA
E&C Dept, M. G. R. University, Chennai, India
Dr. K.R NATARAJ
Professor, Dept of ECE, SJBIT, Kengeri, Bangalore, India
Abstract
A modem (modulator-demodulator) is a device that modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goal is to produce a signal that can be transmitted easily and decoded to reproduce the original digital data. Here there is a need to mix the signals of different frequencies or signals of different types, which emphasizes the use of mixers or multipliers for different RF applications. In this paper, A CMOS analog multiplier, with less number of transistors which can operate at high frequencies with low power and high linearity is proposed. The multiplier works on the basis of parallel connected MOS operation circuit.
Keywords: Modem; Multiplier; Tanner tool; Physical design; schematic design.
Introduction to Analog Multipliers
Analog multiplier, Figure 1 is an important basic building block in communication systems like analog signal processing systems; for example frequency mixers, variable gain amplifiers, adaptive filters, phase-locked loop, amplitude modulators, frequency doublers, rectifiers and demodulators etc. It is necessary to design an analog multiplier circuit which is suitable for low power, low voltage and high speed applications with better linearity.
Figure 1: Basic Multiplier Symbol
Depending on the input/output, analog multipliers can be classified as, Voltage Mode Multipliers[1] and Current Mode Multipliers[2].
And also depending on the circuit configuration it can be classified as
• Single balanced (2-quadrant), and • Double balanced (4-quadrant) multipliers.
Quadrant based classification of multipliers is as follows:
• One-quadrant multipliers: Inputs are of the same phase
In this paper, a low voltage, low power, high linearity and high speed multiplier circuit which operates in the voltage mode using parallel connected MOS devices at the input side and diode connected MOS devices as a load at the output side is proposed for a modem
I. Four-Quadrant Multipliers using Series Connected Transistors
A voltage mode four quadrant analog multiplier based on a basic NMOS differential amplifier[1] that can produce the output signal in voltage form can be constructed using four one-quadrant multipliers or by using two two-quadrant multipliers as shown in Figure. 2.
Figure 2: Four-Quadrant Multiplier
Current equations:
1
*
2a d d
I
I
I
(2.1)
3
*
4b d d
I
I
I
(2.2)
total a b
I
I
I
(2.3)
1 2
(
)(
)
a gs th gs th
I
K V
V
V
V
(2.4)
(
0
)(
)
a x th y th
I
K V
V
V
V
V
(2.5)
(
)(
)
a x y
I
K V
a V
b
(2.6)
3 4
(
)(
)
b gs th gs th
I
K V
V
V
V
(2.7)
(
0
)(
)
b x th y th
I
K V
V
V
V
V
(2.8)
(
)(
)
b x y
I
K V
a V
b
(2.9)
1
[(
)(
) (
)(
)]
total x y x y
I
K V
a V
b
V
a V
b
(2.10)
1
(
)(
0 0)
total y x th x th
I
K V
b V
V
V
V
V
V
(2.11)
1
2
(
)
total x y
I
KV V
b
(2.12)
5
*
6e d d
I
I
I
(2.13)
7
*
8f d d
2
total e f
I
I
I
(2.15)
5 6
(
)(
)
e gs th gs th
I
K V
V
V
V
(2.16)
(
0
)(
)
e x th y th
I
K V
V
V
V
V
(2.17)
(
)(
)
e x y
I
K V
a
V
b
(2.18)
7 8
(
)(
)
f gs th gs th
I
K V
V
V
V
(2.19)
(
0
)(
)
f x th y th
I
K V
V
V
V
V
(2.20)
(
)(
)
f x y
I
K V
a
V
b
(2.21)
2
[(
)(
) (
)(
)]
total x y x y
I
K
V
a
V
b
V
a
V
b
(2.22)
2
(
)(
0 0)
total y x th x th
I
K V
b
V
V
V
V
V
V
(2.23)
2
2
(
)
total x y
I
KV
V
b
(2.24)
1
2total total total
I
I
I
(2.25)
2
(
) 2
(
)
total x y x y
I
KV V
b
KV
V
b
(2.26)
2
(
)
total x y y
I
KV V
b V
b
(2.27)
4
total x y
I
KV V
(2.28)The above “Eq (2.28)” shows the output of four-quadrant multiplier which is independent of threshold voltage and depends on aspect ratio (W/L) of the transistors. In the following section let us analyze the basic voltage mode multiplier using the four-quadrant multiplier with series connected transistors.
II. Basic Voltage Mode Multiplier
Figure 3 shows the basic voltage mode multiplier structure which is constructed using four quadrant multiplier[5-9] with series connected transistors
Figure 3: Basic Voltage Mode Multiplier Structure
Since it has to operate in all the quadrants, output of Vx*Vy and –Vx*-Vy are cross connected to get the total
current Itotal1 andsimilarly the output of –Vx *Vy and Vx*-Vy are cross connected to get the total current Itoatl2.
III. Modified four quadrant Multiplier
at the load side PMOS are used because of its negative threshold voltage.
Figure 4: Modified four quadrant Multiplier Structure
22 4
[(2
) (2
)]
d d x y x
i
i
K
v v
v
(4.12)
(
1
3) (
2
4)
total d d d d
I
i
i
i
i
(4.13)
2
2[ 2
2
]
[2
2
]
total x y x x y x
I
K
v v
v
K v v
v
(4.14)
2
2( 2
2
2
2
)
total x y x x y x
I
K
v v
v
v v
v
(4.15)
4 2
total x y
I
K v v
(4.16)IV. Physical Design
The Physical design of proposed multiplier is done using Tanner EDA’s (Electronic deign Automation) L-Edit (Layout L-Edit). Figure 5.1 and Figure 5.2 shows the layout for basic voltage mode multiplier and proposed multiplier structure with clean DRC (Design Rule Check) and LVS (Layout versus Schematic) respectively.
Figure5.1: Layout of Basic Voltage Mode Multiplier
V. Simulation Results
Here the simulation results of both schematic and layout designs for basic multiplier are included. Different Analysis is performed to check the performance of the multiplier. Pre-Layout simulation results correspond to the schematic results and Post-Layout results correspond to the layout results.
Figure 6.1: Transient Analysis of Basic Multiplier
100k 1M 10M 100M 1G 10G 100G
Frequency (Hz)
-200 -150 -100 -50 0 50 100 150 200
V
o
lta
g
e P
h
as
e
(
d
eg
)
vp(Vout,Vx2) vp(Vout,Vx1) Cell00
100k 1M 10M 100M 1G 10G 100G
Frequency (Hz)
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10
V
o
lta
g
e M
a
gni
tu
d
e
(
d
B
)
vdb(V out,Vx2) vdb(V out,Vx1) Cell00
Figure 6.2: AC Analysis of Basic Multiplier
Figure 6.4: Transient Analysis of Modified four Quadrants Multiplier
100k 1M 10M 100M 1G 10G 100G
Frequency (Hz)
-200 -150 -100 -50 0 50 100 150 200
V
o
lta
g
e P
h
a
se
(
d
eg)
vp(Vout,Vx2) vp(Vout,Vx1) Cell00
100k 1M 10M 100M 1G 10G 100G
Frequency (Hz)
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10
V
o
lta
ge M
a
gn
it
ud
e
(d
B
)
vdb(V out,Vx2) vdb(V out,Vx1) Cell00
Figure 6.5: AC Analysis of Modified four Quadrant Multiplier
VI. Modulation
Modulation is nothing but multiplexing the different signals with different frequencies or different amplitudes. The basic function of modulator is to perform multiplication of amplitude or frequency of the inputs. Figure 7.1 shows the modulated waveform at the output of modulator.
VII. Demodulator
Multiplier can be used as a demodulator by including additional diode connected MOSFETs[8] and capacitors at the output. Figure 8.1 shows the output of demodulator circuit.
Figure 8.1: Demodulator
VIII. Conclusion
In this paper “Low Voltage, Low Power, High Speed and High Linearity-CMOS Analog Multiplier for Modem is proposed”. The multiplier circuit is implemented in 180nm technology with minimum transistor sizes (W/L=180nm/180nm). It can be operated even at low Supply voltage VDD=0.5V. Band width of operation is about 4THz, which is suitable for high frequency/high speed applications
Therefore the Modified four quadrant structures with less number of transistors occupies less area and hence consumes less power.
Table I shows the comparison between the simulation results of Basic Voltage Mode Multiplier and Modified four quadrant multiplier structure
Table I: Comparison between Basic Multiplier and Proposed Multiplier
PARAMETER BASIC MULTIPLIER PROPOSED MULTIPLIER
W/L (min) 180nm/180nm 180nm/180nm
Vdd 1 V 1V
Offset error across output
-4mV 0V
Linearity error High, Output intersects at many points
Less compared to basic multiplier
Power in Watts 1.28MW 700uW
Vx and –Vx 500mV ,1GHz 500mV ,1GHz Vy and –Vy 500mV ,10GHz 500mV ,10GHz
No of transistors 16 6
References
[1] Boonchai Boonchu and Wanlop Surakampontorn, “A four-quadrant Analog Multiplier using basic differential pair”, IEEE 2004 ,pp 290-293.
[2] A Naderi, H Majarrad, H Ghasemzadeh, “Four Quadrant CMOS Analog Multiplier Based on new Current Suarer circuit with high speed”, IEEE,2009,pp 282-286.
[3] Chunhong Chen and Zheng Li,” A Low poweer CMOS Analog Multiplier”, IEEE 2009,vol53,pp100-104. [4] W. Machowski, J Jasielski, S Kuta, “ Low Voltage Analog Multipliers based on Cmos inverters”, 15th
[5] Zhangcai Huang, Yasuaki Inoue, Hong Yu and Quan Zhang, “ A Wide Dyanamic Range Four Quadrant CMOS Analog Mulitplier using Active Feedback”, APCCAS 2006,pp 708-711.
[6] Navin Saxena and James J Clark, “ A Four Quadrant Analog Multiplier for Analog Neural Networks”, IEEE 1994, vol 29,pp 746-749. [7] Shuo- Yuan Hsiao and Chung-Yu Wu, “ A 1.2 V CMOS Four Quadrant Analog Mulitplier”.IEEE 1997,pp 241-244.
[8] Boonchai Boonchu Wanlop Surakampontorn, “ CMOS Voltage Mode Analog Multiplier”, IEEE 2007,pp 1989-1992.
