Design of High speed Low Power Reversible Vedic multiplier and Reversible Divider

In this paper, a Wilkinson power divider using high- low impedance resonator cells for harmonic suppression and size reduction is proposed.. The key features of the proposed

Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high

Reversible logic c ircuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of

In this paper we design a reversible Half Subtractor circuit by Feynman gate using QCA Technology.. The half subtractor performs

In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the

In this paper, we are discussing basic reversible gates, algorithm of 2x2 vedic multiplier and 4x4 vedic multiplier and how it is optimized by reducing number of

A new technique of implementing a multiplier circuit using Decomposition Logic is proposed here which improves speed with very little increase in power dissipation when compared

The multiplier, being the most significant block in many such digital systems, their speed and efficiency are primarily dependent upon the speed, area, throughput