Universidade de Aveiro Departamento deElectrónica, Telecomunicações e Informática 2019
Marcelo
Marques
Implementação em FPGA de um Detector
Universidade de Aveiro Departamento deElectrónica, Telecomunicações e Informática 2019
Marcelo
Marques
Implementação em FPGA de um Detector
ASK/FSK para Balizas de Sinalização Ferroviária
(FPGA-based Implementation of an ASK/FSK Detector for Railway Sig-nalling Balises)
Dissertação apresentada à Universidade de Aveiro para cumprimento dos requesitos necessários à obtenção do grau de Mestre em Engenharia Elec-trónica e Telecomunicações, realizada sob a orientação científica do Professor Doutor Arnaldo Silva Rodrigues de Oliveira, Professor auxiliar do Departa-mento de Electrónica, Telecomunicações e Informática da Universidade de Aveiro e sob a orientação empresarial do Mestre Nefi Carvalho, BTM Man-ager da empresa CAF Signalling.
o júri / the jury
presidente / president Professor Doutor Adão Paulo Soares da Silva Professor Auxiliar, Universidade de Aveiro
vogais / examiners committee Professor Doutor Arnaldo Silva Rodrigues de Oliveira Professor Auxiliar, Universidade de Aveiro (orientador)
Professor Doutor Sérgio Ivan Fernandes Lopes
Professor Adjunto, Escola Superior de Tecnologia e Gestão Instituto Politécnico de Viana do Castelo
agradecimentos / acknowledgements
Desejaria agradecer ao orientador Professor Doutor Arnaldo Rodrigues de Oliveira por todo o incentivo, motivação e disponibilidade. Da mesma forma agradeço ao Engenheiro Mestre Nefi Carvalho pelo incentivo, motivação, disponibilidade e pela possibilidade de visitar e conhecer a CAF Signalling. Para a minha família e amigos um grande obrigado por todo o incentivo que me prestaram, principalmente nos momentos em que a motivação estava mais longe.
Palavras-chave ASK, FSK, Detector de Modulação, FPGA, ERTMS, Sinalização Ferroviária
Resumo Esta dissertação insere-se na área de telecomunicações, mais concretamente nos sistemas de telecomunicações na sinalização ferroviária. O trabalho foi proposto pela empresa CAF Signalling e tem como objectivo a implemen-tação de uma função de segurança que assegura a interoperabilidade entre sistemas de Proteção Automática de Comboios (ATP), ERTMS e KER, dis-tinguindo entre Eurobalisas e balisas KER. Ao longo do trabalho o detector foi modelado em Simulink e convertido em código VHDL.A fase final da dissertação consiste na implementação em FPGA de um detetor de tipo de balisa capaz de operar em condições não ideais. O funcionamento do de-tector foi avaliado com sinais de teste e sinais reais em condições ideais, de ruído AWGN e ruído pulsante.
Keywords ASK, FSK, Modulation Detector, FPGA, ERTMS, Railway Signalling
Abstract This dissertation is inserted in the telecommunications field, specifically rail-way signalling telecommunications systems. This project was proposed by CAF Signalling and aims at implementing the safety function to assure the in-teroperability of both Automatic Train Protection Systems (ATP) systems, ERTMS and KER. Namely, distinguish Eurobalises and KER type balises. Throughout the work the detector is modelled in Simulink and converted to VHDL code. The final step of this dissertation is the implementation on the FPGA of a robust balise type detector capable of detecting the balise type under ideal and non-ideal conditions. The performance of the detector was evaluated with real and test balise signals under ideal conditions, AWGN noise and pulsing noise.
Contents
Contents i List of Figures v List of Tables ix Acronyms xi 1 Introduction 1 1.1 Scope . . . 1 1.2 Motivation . . . 3 1.3 Objectives . . . 41.4 Structure of the Dissertation . . . 4
2 Fundamental Concepts 7 2.1 Railway Signalling Systems . . . 7
2.1.1 Balise . . . 7
2.1.2 EBICAB . . . 8
2.1.3 European Train Control System (ETCS) . . . 9
2.2 Interoperability . . . 11
2.3 Digital Modulation Methods . . . 11
2.3.1 ASK Modulation . . . 11
2.3.1.1 ASK Balise Signal Properties . . . 12
2.3.1.2 ASK Balise Signal Deviations . . . 12
2.3.2 FSK Modulation . . . 12
2.3.2.1 Continuous Phase Frequency-Shift Keying (CPFSK) Modulation 13 2.3.2.2 Eurobalise Signal Properties . . . 13
2.3.2.3 Eurobalise Signal Deviations . . . 13
2.3.2.4 Comparing FSK and ASK Signals . . . 13
2.4 Noise . . . 13
2.4.1 Additive White Gaussian Noise (AWGN) . . . 14
2.4.2 Disturbance Noise . . . 14
2.5 Safety . . . 15
2.5.1 Safety Integrity Level (SIL) . . . 15
3 Architecture Modelling and Simulation 17
3.1 Balise Reference and Test Signals . . . 17
3.1.1 Test Signal Generator . . . 19
3.1.1.1 Telegram Step . . . 19
3.1.1.2 Signal Electrical Characteristics . . . 19
3.1.1.3 Balise Passage Step . . . 20
3.1.1.4 Output Step . . . 20
3.1.2 Noise Generation . . . 20
3.1.2.1 Adding AWGN . . . 20
3.1.2.2 Adding Disturbance Noise . . . 21
3.1.3 Validation of Test Signals with Laboratory Equipment . . . 21
3.1.4 Results . . . 21
3.1.5 Real-World Signals . . . 23
3.2 Algorithm Components . . . 24
3.2.1 Fast Fourier Transform (FFT) . . . 24
3.2.2 Frequency Zoom . . . 24 3.2.3 Frequency Thresholding . . . 24 3.2.4 Bandwidth Calculation . . . 25 3.2.5 Signal classification . . . 25 3.2.6 Majority decision . . . 25 3.3 Simulink Model . . . 26 3.3.1 Filtering . . . 26 3.3.2 FFT Block . . . 26
3.3.3 Frequency Index Counter . . . 28
3.3.4 Complex to Absolute Block . . . 28
3.3.5 Frequency Zoom Block . . . 28
3.3.6 Frequency Thresholding Blocks . . . 29
3.3.7 Bandwidth Calculation Block . . . 29
3.3.8 Signal Type Block . . . 29
3.3.9 Majority Decision Block . . . 30
3.3.10 Disturbance Detector Block . . . 30
3.4 Behaviour Simulation with Test Signals . . . 31
3.4.1 Ideal Conditions . . . 31
3.4.2 Added AWGN . . . 34
3.4.3 Added Disturbance Noise . . . 36
3.5 Behaviour Simulation with Real World Signals . . . 38
3.5.1 Simulation results - added AWGN . . . 41
3.5.2 Simulation results - Disturbance Noise . . . 41
3.6 Response Time . . . 46
3.7 Conclusion . . . 47
4 Implementation and Testing 49 4.1 VHDL Code Generation . . . 49
4.1.1 Fixed-Point Data Convertion . . . 49
4.1.2 HDL Coder . . . 50
4.2 Functional Simulation . . . 52
4.4 FPGA Tests . . . 54
4.4.1 Nexys 4 . . . 54
4.4.2 Agilent 16822A . . . 55
4.4.3 FPGA Tests - Ideal Conditions . . . 55
4.4.4 FPGA tests - added AWGN . . . 60
4.4.5 FPGA Tests - Disturbance Noise . . . 62
4.5 Conclusion . . . 65
5 Conclusion 67 5.1 Future Work . . . 67
List of Figures
1.1 A Fixed Railway Signal. https://www.networkrail.co.uk/ [accessed October
10, 2019]. . . 1
1.2 A train about to pass over a railway balise. https://new.siemens.com/global/ en/products/mobility/rail-solutions/rail-automation/automatic-train-control/ european-train-control-system.html [accessed October 15, 2019]. . . 2
1.3 A map of the signalling systems used in different countries in Europe. https:// ec.europa.eu/transport/modes/rail/ertms/general-information/history_ ertms_it [accessed December 28, 2019]. . . 3
1.4 Block diagram of the communication between ERTMS and the STM. Adapted from [1]. . . 4
2.1 Block diagram of the communication between train and balise. http://www. railsystem.net/balise/ [accessed October 10, 2019]. . . 8
2.2 Train passing over an EBICAB balise. http://www.railsystem.net/balise/ [accessed October 10, 2019]. . . 8
2.3 ETCS trackside components. http://www.youngrailpro.com/yrp-attend-ertms-etcs-conference-2018/ [accessed October 11, 2019]. . . 9
2.4 ETCS operation levels 1 (a), 2 (b) and 3 (c). http://www.railsystem.net/ balise/ [accessed October 10, 2019]. . . 10
2.5 Representation of the different signalling components on a train. Adapted from [17]. . . 11
2.6 EBICAB ASK symbol. . . 12
2.7 Damped oscillation typical of disturbance noise. Retrieved from [16]. . . 14
3.1 High level diagram of the architecture of the detector. . . 18
3.2 Signal generator block diagram. . . 19
3.3 Test signal generator app. . . 19
3.4 Balise radiation pattern depending on air-gap distance. . . 20
3.5 AWGN generator block diagram. . . 21
3.6 Disturbance noise generator block diagram. . . 21
3.7 Diagram of the setup used for validation. . . 21
3.8 Frequency Spectrum of a) ASK Test Signal, b) ASK Real Signal, c) FSK Test Signal, b) FSK Real Signal. . . 22
3.9 Real-world a) ASK and b) FSK signal . . . 23
3.11 Frequency thresholding of example : a) ASK Spectrum, b) FSK Spectrum. . . . 25
3.12 Band-pass and band-stop filters. . . 26
3.13 FFT block optimised for HDL code. . . 26
3.14 Simulink model used to implement the detector. . . 27
3.15 Complex to absolute conversion block. . . 28
3.16 Frequency zoom block. . . 29
3.17 Frequency Thresholding blocks. . . 29
3.18 Bandwidth calculation blocks. . . 30
3.19 Signal type block. . . 30
3.20 Majority decision block. . . 31
3.21 Disturbance noise detection block. . . 31
3.22 Simulation result for an ASK test signal without noise. . . 32
3.23 Simulation result for a FSK test signal without noise. . . 32
3.24 Simulation result for a FSK test signal followed by an ASK test signal without noise. . . 33
3.25 Simulation result for an ASK test signal followed by a FSK test signal without noise. . . 33
3.26 Simulation result for an ASK test signal followed by a FSK test signal with AWGN noise (Eb/N0 = 2). . . 34
3.27 Detector performance for a) ASK and b) FSK test signals with different train speeds. . . 35
3.28 Disturbance noise test for test FSK(a) and ASK(b) signals (Peak disturbance to signal = 3). . . 36
3.29 False positive classifications with test ASK signals(a) and false negatives with test FSK signals(b) (Peak disturbance to signal = 3). . . 37
3.30 Simulation result for a real ASK signal without noise. . . 38
3.31 Simulation result for a real FSK signal without noise. . . 39
3.32 Simulation result for a real FSK signal followed by a real ASK signal without noise. . . 39
3.33 Simulation result for a real ASK signal followed by a real FSK signal without noise. . . 40
3.34 Simulation result for a real ASK signal followed by a real FSK signal with AWGN noise (Eb/N0 = 2). . . 41
3.35 Simulation of real signals under different Eb/N0. . . 42
3.36 Disturbance noise test for real world signals Fs = 4.5 Mhz, Df = 30 and repe-tition rate = 1.5 kHz. . . 42
3.37 Disturbance noise test for real world signals Fs = 3.9 Mhz, Df = 30 and repe-tition rate = 1.5 kHz. . . 43
3.38 Disturbance noise test for real-world FSK(a) and ASK(b) signals. . . 44
3.39 False positive classifications with real-world ASK signals(a) and false negatives with FSK signals(b). . . 45
3.40 Response time test of an ASK test signal. . . 46
3.41 Response time test of an FSK test signal. . . 47
3.42 Response time test of a real-world ASK signal. . . 48
3.43 Response time test of a real-world FSK test signal. . . 48
4.2 Fixed-Point Tool. . . 51
4.3 HDL Workflow Advisor. . . 51
4.4 Functional Simulation of real ASK signal. . . 52
4.5 Timing summary of the design. . . 53
4.6 Utilization summary of the design. . . 53
4.7 Setup used to test the running algorithm in the FPGA. . . 54
4.8 PCB used to convert the ECL to LVCMOS33. . . 55
4.9 FPGA test for an ASK test signal without noise. . . 56
4.10 FPGA test for a FSK test signal without noise. . . 56
4.11 FPGA test for a FSK test signal followed by an ASK test signal without noise. 57 4.12 FPGA test for an ASK test signal followed by a FSK test signal without noise. 57 4.13 FPGA test for a real ASK signal without noise. . . 58
4.14 FPGA test for a real FSK signal without noise. . . 58
4.15 FPGA test for a real FSK signal followed by a real ASK signal without noise. . 59
4.16 FPGA test for a real ASK signal followed by a real FSK signal without noise. . 59
4.17 FPGA test for an ASK test signal followed by a FSK test signal with AWGN noise (Eb/N0 = 2) . . . 60
4.18 Detector FPGA test for FSK test signals with different train speeds . . . 61
4.19 Detector FPGA test for ASK test signals with different train speeds . . . 61
4.20 FPGA Disturbance noise test for real world signals Fs = 3.9 Mhz, Df = 5 and repetition rate = 1.5 kHz (Peak disturbance to signal = 3) . . . 62
4.21 Disturbance noise test for test FSK(a), test ASK(b), real-world FSK(c) and real-world ASK(d) signals (Peak disturbance to signal = 3). . . 63
4.22 False positive classifications with test FSK(a), test ASK(b), real-world FSK(c) and real-world ASK(d) signals (Peak disturbance to signal = 3). . . 64
List of Tables
2.1 Comparing the electrical data of FSK and ASK signals. . . 13 2.2 Safety Integrity Levels. . . 15
Acronyms
ASK Amplitude-shift Keying Modulation. i, v–vii, ix, 3, 4, 7, 8, 11–13, 17, 20–25, 30–41, 45, 46, 48, 55–61, 67
ATP Automatic Train Protection. 1, 8
AWGN Additive White Gaussian Noise. ii, iii, 4, 13, 14, 20, 31, 34, 41, 47, 60 BTM On-Board Transmission Module. 7, 15
CSV Comma-separated Values. 55
ERRI European Rail Research Institute. 2
ERTMS European Rail Traffic Management System. 1, 2, 67 ETCS European Train Control System. 7
FFT Fast Fourier Transform. 24
FPGA Field Programmable Gate Array. 3, 49, 50, 54, 55, 60, 62, 65 FPT Fixed-Point Tool. 49
FSK Frequency-shift Keying Modulation. i, v, vi, 3, 4, 7, 9, 12, 13, 17, 21–25, 29–39, 41, 55, 60, 67
KER KVB, Ebicab and RSDD. 1, 3, 8, 11 PFD Probability of Failure on Demand. 15, 67 R&S Rohde Schwarz. 21
RF Radio Frequency. 17, 23, 38, 54, 68 SIF Safety Instrumentation Function. 15 SIL Safety Integrity Level. i, 15, 67 SIS Safety Instrumentation System. 15 STM Specific Transmission Module. 11
TSG Test Signal Generator. 17
UIC International Union of Railways. 2 VSG Vector Signal Generator. 21
Chapter 1
Introduction
1.1
Scope
Since the dawn of railway transportation, signalling is a crucial component whose develop-ment has followed the evolution of this mode of transportation. The need for signalling stems from the fact that trains are heavy and usually operate at speeds that make it very difficult to stop within the driver’s field of view, requiring careful control of the speed and position of each train in the network.
Initially, trains didn’t use signalling, the driver decided train speed based on his senses. This quickly led to multiple accidents and the need for a signalling system, so a system where trains would depart within a fixed time interval of each other was put in place, this proved inefficient in several ways, it didn’t account for the fact that the travel time would vary between trains and when a train broke down in the middle of a track the ones behind had no warning. Later railway operators started dividing the track into several portions or blocks, so only one train occupied each block to avoid collisions and using fixed light signals, like the one in Figure 1.1, to visually inform the train driver if he can transit to the next block. Nowadays, due to higher train speeds a train driver can no longer react in time to visual signals and newer, unified and safer train control and signalling systems are required.
Figure 1.1: A Fixed Railway Signal. https://www.networkrail.co.uk/ [accessed October 10, 2019].
These systems rely on the use of telecommunications to exchange information between trains and the track equipment, mainly through the use of Balises, passive transponders in-stalled on the track, as shown in Figure 1.2. This results in improved traffic capacity, safety and punctuality.
Figure 1.2: A train about to pass over a railway balise. https://new.siemens.com/global/ en/products/mobility/rail-solutions/rail-automation/automatic-train-control/ european-train-control-system.html [accessed October 15, 2019].
As Figure 1.3 shows, the adoption of these signalling systems happened independently in each country without regard to the railway infrastructure of neighbouring countries. In Europe there are many factors that make moving trains between countries a complicated task :
• More than 20 different signalling systems; • Five different railway electrification systems;
• Different measuring units (Imperial and Metric Units);
• Different railway gauges in countries like Ireland, Spain, Portugal and Russia.
In an effort to unify railway standards across Europe in the mid-1980s, the International Union of Railways (UIC) and the European Rail Research Institute (ERRI) began the de-velopment of a rail traffic management solution that could be adopted by every country in Europe, the European Rail Traffic Management System (ERTMS) which set the following targets :
• Create a unified train protection system to allow both quick replacement and interoper-ability with legacy systems;
• Unify and enhance communication of track status to the train;
• Allow components from different manufacturers to work on the same track under ERTMS. Nowadays ERTMS has also become the "de facto" railway signalling for railway projects outside of Europe, in countries like China, India, Saudi Arabia, etc.
Figure 1.3: A map of the signalling systems used in different countries in Europe. https://ec.europa.eu/transport/modes/rail/ertms/general-information/ history_ertms_it [accessed December 28, 2019].
1.2
Motivation
As mentioned above one of the main targets of ERTMS is interoperability between ERTMS and legacy signalling systems, the objective is that a train equipped with ERTMS, running on a track equipped with a legacy system, can detect the system on track and use the Specific Transmission Module (STM), a component of the ERTMS train capable of receiving and processing communications from a specific legacy system, to process the information received. The objective of this project is the creation of a detector that can identify the current system on-track and therefore the type of balise communicating with the train. Since ERTMS and KER (legacy) balises transmit FSK and ASK signals, respectively, this project aims to develop a robust balise type detector to be implemented in a FPGA by detecting the modulation of the received signal. This project was proposed by CAF Signalling, a spanish company that projects and manufactures high-speed and metro trains and is one of the seven full members
Figure 1.4: Block diagram of the communication between ERTMS and the STM. Adapted from [1].
of the UNISIG consortium that defines the technical specifications of ERTMS/ETCS.
1.3
Objectives
The objectives of this work are the development of a balise type detector that can identify signals transmitted by Eurobalises and KER balises, by identifying the FSK or ASK modula-tion of the signal, respectively. The requirements of this detector are not limited to the ability of correctly detecting the signal received, it also must be robust, meaning that in the presence of noise, which in the railway setting can refer to additive white gaussian noise (AWGN) or disturbance noise, this detector must classify the type of signal correctly or communicate to the system that it is receiving too much noise to correctly perform the detection, false pos-itives, when an ASK signal is classified as FSK or vice-versa, must be avoided. Finally, the output of the detector has a specific timing requirement.
1.4
Structure of the Dissertation
This dissertation is divided in organised in 5 chapters, divided in sections and subsections. In Chapter 1 consists of :
• brief introduction to ERTMS and the reasons and objectives that lead to the creation of the system;
• the motivations for the development of the modulation detector; • the requirements that the detector must fulfil.
Chapter 2 is a review of the concepts and techniques that will be used during the devel-opment of the algorithm, including:
• railway signalling systems;
• the interoperability requirements of ERTMS; • ASK and FSK modulation techniques;
• the types of noise that affect railway signalling systems; • overview of the SIL safety standard.
Chapter 3 is focused on the generation of the balise signals, the modelling, simulation and testing of the detector and covers :
• the process used to generate test signals; • validation of the test signals in the laboratory; • the real-world signals provided by CAF;
• the process used to add noise to test and real-world signals; • the high-level architecture of the modulation detector; • Simulink model components;
• simulation results with test and real-world signals.
Chapter 4 focuses on the implementation of the detector in the FPGA and the results of the tests of the final system and the setup used for testing. The last chapter, Chapter 5 presents the conclusions of the work done and suggestions for future work.
Chapter 2
Fundamental Concepts
This chapter presents an overview of the research performed to better understand the signalling systems and techniques used throughout this dissertation. It establishes the different components interacting with the balise type detector, the type of signals used to communicate and the requirements for interoperability between components from different systems.
The first section analyses both signalling systems, EBICAB and ETCS, including opera-tion, characteristics, components and communication between balises and trains. After comes a brief overview of the modulation techniques followed by the electrical characteristics of the modulated railway signals. To provide a full picture of the railway signalling environment the last part of this chapter focuses on defining the non-ideal/noise conditions the modula-tion detector will face, including carrier frequency deviamodula-tions and the safety standard used to evaluate performance in the last chapter.
2.1
Railway Signalling Systems
EBICAB and ERTMS are signalling systems that use magnetic coupling to exchange in-formation between trains and track equipment since trains operate in tracks with different signalling systems, this section reviews the fundamental characteristics of these systems and interoperability guidelines.
2.1.1 Balise
Balises are passive transponders used to transmit telegrams to the On-Board Transmis-sion Module (BTM) containing safety relevant information. Telegrams are the bitstreams containing speed and distance information stored in the balises.
Communication between the BTM and balises relies on magnetic coupling, for the BTM to receive a telegram from a wayside balise first it must activate the balise emitting a mag-netic 27 MHz signal, called the tele-powering signal, energy is induced in the balise reception loop/antenna, activating the balise that starts transmitting the up-link signal. The up-link signal is the magnetic signal with carrier frequencies between 3.8 and 4.7 MHz that can be ASK or FSK modulated, depending on the signalling system. After receiving the signal the BTM decodes the telegram.
This process happens while the train is passing over the balise at variable speeds causing the amplitudes of the tele-powering and up-link signals to change depending on the distance
between the train antenna and the balise causing a radiation pattern on the up-link signal, this pattern is analyzed in section 3.1.3.
Figure 2.1: Block diagram of the communication between train and balise. http://www. railsystem.net/balise/ [accessed October 10, 2019].
2.1.2 EBICAB
EBICAB is one of the legacy (KER) signalling systems developed and installed during the 1980s by Bombardier, currently it is still used in countries like Portugal, Spain, Sweden, Norway and Bulgaria. In many of these countries EBICAB was the first Automatic Train Protection(ATP) system installed and remains in place because of high switching costs. The system can fulfil the following tasks:
• Monitor train speed;
• Enforce temporary or permanent speed limits; • Inform when trains are manoeuvring on the track; • Provide authorisation to pass at a stop.
The communication between track and train is done using EBICAB balises, Figure 2.2, that transmit telegrams to the BTM of the train using ASK modulation. EBICAB balises are installed on that track in groups of two, so the system can determine the direction of circulation based on telegram order.
Figure 2.2: Train passing over an EBICAB balise. http://www.railsystem.net/balise/ [accessed October 10, 2019].
2.1.3 European Train Control System (ETCS)
ETCS is the railway signalling component of the European Railway Train Management System (ERTMS). Figure 2.3 shows some of ETCS trackside components, each one is tasked with a different function:
• Eurobalise: send FSK telegrams to the train, these can have fixed information or be changed when the balise is connected to the lineside electronic unit (LEU). Balises are mounted in groups where each one sends one telegram and the combination of telegrams forms the message;
• Euroloop: a component based on a leaky cable and a modem that send telegrams to train to complement Eurobalise signals;
• Lineside electronic unit (LEU): electronic device that generates telegrams to be trans-mitted. The information used to generate telegrams is received from external trackside systems. The LEU can also be connected to euroloops or radio infill units (RIU); • Trackside radio communication network (GSM-R): the GSM-R communication network
was originally developed for voice communications in the railways, but now it’s used for bi-directional exchange of information between sub-systems in the train and RBC or radio infill units;
• Radio block center (RBC): computer-based system that generates messages to be sent to the train based on information received from external trackside equipment (interlockings, block systems and level-crossings) and from the train on-board systems. These messages are used to communicate movement authority allowing safe movement of trains in the railway;
• Radio infill unit (RIU): transmission component that uses the GSM-R transmission to provide signalling information in regard to the next main signal in train running direction.
Figure 2.3: ETCS trackside components.
http://www.youngrailpro.com/yrp-attend-ertms-etcs-conference-2018/ [accessed October 11, 2019].
Depending on the equipment installed on the track ETCS has several levels of operation: • Level 0: provides minimal supervision of train movement for a train equipped with
ETCS operating on a line without ETCS or a national system installed;
• Level 1: ETCS is installed or superimposed on the track and provides continuous super-vision of train movement. Eurobalises or national balises are used for communications with trackside equipment;
• Level 2: GSM-R is used to transmit position data and receive signalling and speed information, making trackside signalling optional. Eurobalises are still used for train position information;
• Level 3: Similar to level 2 but train location and integrity can also be achieved using GSM-R.
a)
b)
c)
Figure 2.4: ETCS operation levels 1 (a), 2 (b) and 3 (c). http://www.railsystem.net/ balise/ [accessed October 10, 2019].
2.2
Interoperability
The strategy adopted in ERTMS to allow the ERTMS train to support several signalling systems relies on Specific Transmission Modules (STM). STMs are hardware interfaces ca-pable of managing the reception and processing of KER balise transmissions. As shown in Figure 2.5, if the BTM receives an up-link signal from a KER balise interface K performs the balise detection and forwards the transmission to the correct STM. The balise type detector developed in this dissertation takes the role of interface K.
Figure 2.5: Representation of the different signalling components on a train. Adapted from [17].
According to the Interface K reference document [15] the detector must perform a balise detection in the time corresponding to 32 ASK bits after the start of the reception.
32 × 1
50kHz = 640µs (2.1)
In practice this means the Interface K perform a balise detection within 640µs after start the reception therefore the balise type detector must be able to perform a classification in the same amount of time.
2.3
Digital Modulation Methods
Since the balises transmit digital modulated signals this section consists of a brief review of both modulation techniques and the electric characteristics of the signals.
Digital modulation is the process used to transmit a bitstream by varying the properties of a periodic waveform, the carrier signal. For the scope of this work only 2 types of digital modulations are considered Amplitude-shift Keying Modulation (ASK) and Frequency-shift Keying Modulation (FSK).
2.3.1 ASK Modulation
In this modulation each bit value is transmitted varying the amplitude of the carrier signal keeping the same frequency. The modulated signal (xp) can be expressed in the time domain
as:
xp[n] = Ap.cos(2πfcnT ) (2.2)
Where Ap is the amplitude of the signal depending on bit value, fcis the carrier frequency of
the signal and T represents the sampling period. 2.3.1.1 ASK Balise Signal Properties
The EBICAB balise also called ASK Balise transmits an ASK modulated signal with a frequency of 4.5 MHz where a 0 bit is transmitted with a high amplitude and a 1 bit with low or zero amplitude, the data rate is 50kbit/s. The envelope of the pulse for every bit decreases exponentially, Figure 2.6, the time it takes to decrease from 90% to 45%, is named t50, is 3.8 µs. 0 2 4 6 8 10 12 14 16 Time (us) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Amplitude
Figure 2.6: EBICAB ASK symbol.
2.3.1.2 ASK Balise Signal Deviations
The properties of the signal can vary due to equipment ageing and the frequency of the ASK signal and t50 can vary between 4 to 4.7 MHz and 2.0 and 5.0 µs, respectively.
2.3.2 FSK Modulation
In frequency-shift keying modulation different bit values (x[n]) are transmitted using dif-ferent frequencies. The modulated signal in the time domain can be expressed as:
xp[n] = A.cos(2πfcnT ) (2.3)
Where c and fcrepresent the value of the bit and the frequency associated with that value and
T represents the sampling period, then for an FSK system with that transmits 2 bit values: x[n] = 0 : xp[n] = A.cos(2πf0nT ) (2.4)
2.3.2.1 Continuous Phase Frequency-Shift Keying (CPFSK) Modulation
CPFSK is a special type case of FSK modulation used in Eurobalises, as the name suggests it’s used to avoid the discontinuities that are caused by frequency switching in regular FSK modulation, this results in a continuous waveform and better spectral efficiency.
The strategy used to implement a digital CPFSK modulator ahead in this work starts by assuming that every FSK bit can be expressed with the formula:
xp[n] = A.cos(2πφ[n]) (2.5)
Since the phase component for the n sample of the signal is φ[n] = fc
fsn, where fs is the
sampling frequency and fc the carrier frequency of a 0 or 1 the continuous phase φ[n] can be defined recursively as φ[n] = φ[n − 1] +fn
fs. Therefore the formula to generate a digital CPFSK
modulated signal is:
xp[n] = A.cos(2π(φ[n − 1] +
fn
fs
)) (2.6)
2.3.2.2 Eurobalise Signal Properties
The Eurobalise transmits a signal modulated with CPFSK modulation with a nominal centre frequency of (f1+ f0)/2 = 4.234 MHz and a nominal frequency deviation of (f1− f0)/2
= 282.24 kHz, so the carrier frequencies used to transmit the 0 and 1 bit values are 3.9 MHz and 4.516 MHz, respectively. The nominal data rate is 564.48 kbit/s.
2.3.2.3 Eurobalise Signal Deviations
The centre frequency and the frequency deviation of the Eurobalise have maximum devi-ations of ±175 kHz and ±20 kHz, respectively. The signal can be found in a range from 3.8 MHz to 4.7 MHz. The data rate can also have a maximum deviation of ±2.5%.
2.3.2.4 Comparing FSK and ASK Signals
FSK ASK
Characteristics Nominal Value Tolerance Range Nominal Value Tolerance Range
Centre Frequency 4.234 MHz ± 175 kHz 4.5 MHz +200/-500 kHz
Frequency Deviation 284.24 kHz ± 20 kHz
Bandwidth 616 kHz ± 80 kHz 100 kHz
Table 2.1: Comparing the electrical data of FSK and ASK signals.
2.4
Noise
Every telecommunications system is vulnerable to noise and railway signalling systems are no exception. As defined in the ERTMS standard the main disturbance that impacts ERTMS On-board systems damped sinusoidal pulses generated by high power switching mechanisms, comparison tests against AWGN were also performed.
2.4.1 Additive White Gaussian Noise (AWGN)
AWGN is a noise model used to mimic the occurrence of random events. This noise is called:
• Additive: as the noisy signal results of the sum between the original signal and the noise; • White: because it’s power is uniformly distributed across all frequencies;
• Gaussian: because the probability distribution of noise values follow a gaussian distri-bution.
Gaussian noise can be modelled mathematically by the probability density function: f (x) = e
−(x−µ2)/(2σ2)
√
2πσ2 (2.7)
Where µ represents the mean and σ the variance. As mentioned in the Eurobalise Test Specification [18], AWGN noise in railway communications has low signal power.
2.4.2 Disturbance Noise
In railway tracks noise sources like radiating cables, train traction and reflecting surfaces are responsible for a different type of noise, disturbance noise, this noise manifests as a series of damped sinusoidal oscillations that repeat at a fixed rate, Figure 2.7. The parameters of this oscillation are self frequency (Fs), decaying factor(Df) and the repetition rate.
Figure 2.7: Damped oscillation typical of disturbance noise. Retrieved from [16]. Self frequency is the frequency of the oscillation and can have the values of 1.0, 2.5, 3.9, 4.5 or 6.0 MHz. The decaying factor (Df) can be 5 or 30 cycles and refers to the number of cycles that take for the oscillations to go from 90% to 10% of the maximum amplitude and the repeating rate is the frequency of repetition of the oscillation, that frequency can be 1.5, 5 or 15 kHz.
Each damped oscillation can be mathematically defined by the following expression: x(t) = Aoe
−ln(0.9Ao/0.1)Fst
Df cos(2πF
st) (2.8)
2.5
Safety
Safety refers to the control of recognised hazards in order to achieve an acceptable level of risk. The balise type detector is a function of the BTM that is required to fullfil a fail rate less than 2 × 10−11 failures per hour [15].
2.5.1 Safety Integrity Level (SIL)
SIL is a safety measurement for a Safety Instrumentation Function (SIF), a function of the Safety Instrumentation System (SIS) responsible for reducing the risk of system failure. In the context of the ERTMS train, the balise type detector is the SIF to the BTM that is the SIS, since a failure in the operation of the detector can result in wrong data acquisition and a possible train malfunction.
The SIL rating of the detector according to the Probability of Failure on Demand (PFD), the probability of the detector giving a classification that can compromise the operation of the train, is presented in table 2.2.
Safety Integrity Level Probability of Failure on Demand (PFD)
SIL 4 10−5 to 10−4
SIL 3 10−4 to 10−3
SIL 2 10−3 to 10−2
SIL 1 10−2 to 10−1
Table 2.2: Safety Integrity Levels.
2.6
Conclusion
The review of the EBICAB and ERTMS signalling standards shows that ERTMS provides better train location, safety and protection features, better traffic management and higher train speeds. The electrical characteristic of the balise signals and non-ideal conditions point to signal bandwidth as the most robust feature of the EBICAB and ERTMS balises. Sig-nal bandwidth is smaller in EBICAB sigSig-nals (aprox. 100 kHz) and significantly higher in Eurobalise signals (between 500 kHz and 700 kHz).
Chapter 3
Architecture Modelling and
Simulation
The architecture of the balise type detector, shown in Figure 3.1, relies on detecting the modulation of the received signal by calculating the signal bandwidth, signals are classified as ASK or FSK according to their bandwidth, as ASK signals have a much smaller bandwidth (approximately 100 kHz) than FSK signals (approximately 600 kHz). The modulation detector uses a sampling and operating frequency of 25 MHz.
The initial step to develop the algorithm was the creation of the Matlab Test Signal Generator (TSG), which generates signals used for testing the performance of the algorithm. A separate Matlab script was used to compare the frequency spectrum of the ASK and FSK test signals. Through this comparison, bandwidth was identified as the feature that was different between both types of signals and robust to carrier frequency variations. The frequency spectrum of ASK signal has the maximum at the carrier frequency and smaller peaks at ± 50 kHz so the bandwidth of the signal is 100 kHz. The bandwidth of the FSK signal is in the 500-700 kHz range and results of the deviation between the two carrier frequencies. An edge case exists when a FSK balise only transmits one type of bit (either a 0 or a 1), this causes the result of the bandwidth calculation to be 0, since the frequency spectrum of this signal is a tone at the carrier frequency, so in the presence of a signal if the bandwidth is bellow 10 kHz the algorithm classifies it as a FSK signal.
3.1
Balise Reference and Test Signals
Test signals were necessary to evaluate the behaviour of the detector under variations of train speed, carrier frequency and telegram content and were generated using telegram data present in the Eurobalise Test Specification [18]. The last step is the validation of the test signals in the RF Lab and the analysis of real-world signals provided by CAF Signalling.
Figure 3.1: High lev el diagram of the arc hitecture of the detector.
3.1.1 Test Signal Generator
The Matlab app in Figure 3.3 was developed to generate signals used for the development and testing of the algorithm. The main reason behind the development of the app was the need for a tool that allowed both the generation of signals in accordance to ERTMS and EBICAB specifications but also the visualisation and quick editing of each signal, this helped to identify the differences between the signals and the identification of key features for signal detection, namely signal bandwidth.
Figure 3.2: Signal generator block diagram.
Figure 3.3: Test signal generator app.
3.1.1.1 Telegram Step
The first step to generate a balise test signal is providing the app with the bitstream of the telegram that the signal must transmit. Two input methods are supported, the user can either input the telegram or import an excel file with the test telegrams sourced from the Eurobalise Test Specification document [18].
3.1.1.2 Signal Electrical Characteristics
The next step is to call the function that generates the signal. The arguments for this function are the electrical characteristics of the signal such as:
• Frequency Deviation; • FSK/ASK Modulation; • Signal Amplitude.
The user can use the several knobs and edit fields to adjust these characteristics and create different signals for later testing.
3.1.1.3 Balise Passage Step
The passage of the train by the balise creates a radiation pattern like the one seen in Figure 3.4. To create a realistic signal with the generator, radiation patterns obtained from laboratory tests at CAF are imported from an excel file and applied to the signal generated in the previous step. The duration of the balise passage and the number of telegrams sent are calculated based on train speed.
Figure 3.4: Balise radiation pattern depending on air-gap distance.
3.1.1.4 Output Step
The Test Signal Generator can output the signal to the Matlab plot featured in the App, a Matlab array or to a Vector Signal Generator connect by Ethernet cable provided the IP address of the equipment.
3.1.2 Noise Generation
To simulate the performance of the balise type detector under non-ideal conditions Matlab scripts were created to generate signals with the adequate noise components.
3.1.2.1 Adding AWGN
Real and test signals with AWGN noise were created using a Matlab script represented by the diagram in Figure 3.6. The script starts with the desired energy per bit to noise power ratio (Eb/N0) and calculates the signal to noise ratio (SNR) finally a preexisting Matlab function adds noise with the specified noise power.
Figure 3.5: AWGN generator block diagram. 3.1.2.2 Adding Disturbance Noise
A signal with added disturbance noise is created with the same code used to create an ASK symbol but with the self frequency (Fs) as the carrier frequency, the t50 is calculated
based on the decaying factor (Df), the number of pulses is calculated based on the length of the signal and the repetition rate, the peak disturbance amplitude to peak signal amplitude was set as 3.
Figure 3.6: Disturbance noise generator block diagram.
3.1.3 Validation of Test Signals with Laboratory Equipment
To ensure that the test signals can be used in the development and testing of the algorithm first they must go through a validation step. To perform the validation test signals are uploaded from Matlab, via Ethernet connection, to a vector signal generator (VSG), the R&S SMJ100A, connected with a coaxial cable to a Spectrum Analyzer, like the R&S FSQ. Fig.3.7 illustrates the setup used.
Figure 3.7: Diagram of the setup used for validation.
3.1.4 Results
The validation of the signals consists of comparing the frequency spectrum obtained from laboratory tests with real-world signals captured from operating ASK and FSK Balises. The
objective was to achieve in the test signals a peak-to-average value close to the real-world signals using the same measurement conditions in the equipment. The peak-to-average value consists of the difference in dB from the peak of the spectrum to the average. The objective was a peak to average value of about 10 dB in each of the test signals.
Comparing the screen captures from Figure 3.8 the peak-to-average value in the ASK signals is 17 dB, real and test signal, in the FSK signal the value is of 13 dB for the real and 10 dB for the test signals. The test signals were considered valid to develop and test the algorithm.
a) b)
c) d)
Figure 3.8: Frequency Spectrum of a) ASK Test Signal, b) ASK Real Signal, c) FSK Test Signal, b) FSK Real Signal.
3.1.5 Real-World Signals
Real-world signals are two signals from operating balises provided by CAF, an ASK and a FSK balise signal, captured using CAF’s radio frequency (RF) front-end. These signals provide simulation results that are closer to reality than those obtained using test signals, the latter are still relevant to test the detector’s performance for a larger number of signals and carrier frequency deviations that occur with the ageing of the balises. Figure 3.9 shows the plots of the real-world signals.
a) 0 2 4 6 8 10 12 14 time (ms) -1.5 -1 -0.5 0 0.5 1 Signal Amplitude b) 0 10 20 30 40 50 60 70 time (ms) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Signal Amplitude
3.2
Algorithm Components
For a better understanding of the high level architecture of the modulation detector every component of the algorithm is explained in detail.
3.2.1 Fast Fourier Transform (FFT)
The Fast Fourier Transform (FFT) is an algorithm used to implement the discrete Fourier transform (DFT), the aim of this operation is to convert the balise signal at the input from the time to the frequency domain. To calculate the DFT of an input x of N samples the following expression is used:
Xk= N −1 X n=0 xne −i2πkn N k = 0, ..., N − 1 (3.1)
Where k represents each frequency being calculated, the results of the operations are the complex values to frequency domain of the signal at the input.
This operation carries heavy computational cost so nowadays the FFT is used, throughout this work the FFT HDL Optimized block from Simulink was used to calculate the results quicker.
3.2.2 Frequency Zoom
The electrical data of FSK and ASK signals presented in table 2.1 shows that only frequen-cies between 3.8 and 4.7 MHz are of interest to the modulation detector. So after performing the operation all the frequencies outside the range of interest are ignored, Figure 3.10.
a) b)
Figure 3.10: Frequency zoom of example : a) ASK Spectrum, b) FSK Spectrum.
3.2.3 Frequency Thresholding
To calculate the bandwidth first the algorithm isolates the frequency components 6 dB or less below the peak of the zoomed spectrum converting all other points of the FFT to 0, as shown in Figure 3.11. This step is called frequency thresholding.
a) b) Figure 3.11: Frequency thresholding of example : a) ASK Spectrum, b) FSK Spectrum.
3.2.4 Bandwidth Calculation
The bandwidth of the spectrum is calculated after frequency thresholding and is equivalent the maximum deviation (in kHz) between the two frequency points.
3.2.5 Signal classification
The signal is classified as ASK, FSK or no signal depending on the value of the bandwidth calculated in the previous step. Bandwidth values are classified as follows:
• Below 10 kHz: Classified as FSK signal, this refers to the rare case were a Eurobalise only transmits 1s or 0s;
• Above 10 kHz and bellow 200 kHz: Classified as ASK signal; • Above 200 kHz and bellow 700 kHz: Classified as FSK signal;
• Above 700 kHz: Classified as no signal since this bandwidth exceeds the possible band-width of the signal.
3.2.6 Majority decision
This part of the system is used to eliminate possible errors in signal classification and reduce the influence of noise on the output of the algorithm. This module has to output the detection result within the 640µs required by Interface K so the maximum number of classifications that can be stored within the required time interval was calculated. The algorithm stores the last 7 outputs of the signal classifier and outputs the mode.
Tclassif ier =
2048
25M Hz = 82µs (3.2)
640µs
82µs = 7.81 (3.3)
3.3
Simulink Model
A Simulink model in Figure 3.14 was implemented to replicate the architecture of the mod-ulation detector with the objective of conversion into VHDL code and FPGA deployment in later stages, using the HDL Coder package. This model was used to simulate the performance of the balise type detector with test and real-world signals and different noise conditions.
3.3.1 Filtering
To remove unnecessary components present in the signal the two Chebyshev type 2 digital filters presented in Figure 3.12 were designed with the Matlab filter design tool and added to the Simulink model. A 6-th order band-pass filter that only allows frequencies between 3.8 and 4.7 MHz to pass and an 8-th order band-stop filter that removes all frequencies between 5 and 7 MHz, including a 6.1 MHz tone present in the real-world signals added by the RF front-end.
Figure 3.12: Band-pass and band-stop filters.
3.3.2 FFT Block
To calculate the Fast Fourier Transform (FFT) of the signal received by the detector the FFT HDL Optimised was used in the Simulink model. This block receives the signal and outputs the FFT one sample at the time. The FFT has a length of 2048 points, this value was chosen to provide the necessary fine frequency resolution 25 MHz/2048 = 12 kHz (30 kHz is the minimum required).
Figure 3.14: Sim ulink mo del used to implem en t the detector .
3.3.3 Frequency Index Counter
The FFT block presents two challenges, the first one is it only outputs the points with the complex values of the FFT and not the frequency of said point, so we have no way to select and store the frequencies of interest. The second challenge is that since only the frequencies of interest are necessary while the FFT is calculating those values the algorithm can be performing other tasks, like calculating the bandwidth or classifying the signal. The solution is a counter with the reset connected to the start port of the FFT block that outputs the frequency index of each FFT point, compare blocks are used to solve the second challenge and control the instant at which every other step of the algorithm happens.
This block, shown in Figure 3.14, is composed of an HDL Counter whose reset is connected to the Start port of the FFT block and several compare blocks that decide which step of the algorithm based on the value of the HDL Counter.
3.3.4 Complex to Absolute Block
This block, Figure 3.15, converts the output of the FFT Block from complex to absolute squared value. The Complex-to-Real-Imag block is used to separate the components of the complex value, each component is squared using a multiplier and the sum block adds them to output the absolute squared value.
Figure 3.15: Complex to absolute conversion block.
3.3.5 Frequency Zoom Block
The block shown in Figure 3.16 stores in memory the FFT points for frequencies between 3.8 and 4.7 MHz, that way the Frequency Thresholding and Bandwidth Calculation blocks after will only operate on the frequencies of interest. The points of interest are stored using the discrete block from Simulink that stores a given number of samples. To store the correct points the block is enabled between points 303 and 393 (inclusive) of the FFT, as these points correspond to the frequencies of interest.
Figure 3.16: Frequency zoom block.
3.3.6 Frequency Thresholding Blocks
Two different steps are used to implement Frequency Thresholding, since calculating the logarithm of each point would take unnecessary computational power, the first step is used to calculate the adaptive threshold by multiplying the maximum FFT output with the detection threshold of 6 dB or 10−0.6, the next step is used to set all value bellow the threshold to 0.
The first block in Figure 3.17 receives a vector 91 samples (points of interest) and uses the maximum block to find the peak of the spectrum, the peak is multiplied with the detector threshold (10−0.6) to set the minimum, the outputs of the first block are the vector with points of interest and the minimum. In the second block, each point of interest is compared with the threshold value using the Relational Operator block if they are above the threshold the Switch block outputs the value else it outputs 0.
Figure 3.17: Frequency Thresholding blocks.
3.3.7 Bandwidth Calculation Block
This block uses a Matlab function to calculate the bandwidth based on the distance be-tween the two frequencies different than 0 that are the furthest apart.
3.3.8 Signal Type Block
This block receives the bandwidth value from the previous block and uses a Matlab function to classify the signal as ASK, FSK or no signal. Bandwidth values are classified as follows:
Figure 3.18: Bandwidth calculation blocks.
• Below 10 kHz: Classified as FSK signal, this refers to the rare case were a Eurobalise only transmits 1s or 0s;
• Above 10 kHz and bellow 200 kHz: Classified as ASK signal; • Above 200 kHz and bellow 700 kHz: Classified as FSK signal;
• Above 700 kHz: Classified as no signal since this bandwidth exceeds the possible band-width of the signal.
Figure 3.19: Signal type block.
3.3.9 Majority Decision Block
The majority decision block, Figure 3.20, takes the last 7 signal classifications and outputs the classification that occurred the most. The inputs of this block are the signal classifications from Signal Type block and output of the Disturbance Detector block, the Matlab function finds the mode of the classifications, when the output of the Disturbance Detector is 1 the function sets the next signal classification as 0 (No signal).
3.3.10 Disturbance Detector Block
The block shown in Figure 3.21 is used to detect disturbance noise, the first block calculates the sum of all elements of FFT points within the frequencies of interest, the second block compares the sum of the current frequencies with the previous one and the last block checks if the current is twice the value of the previous one. If disturbance noise is detected this block resets the output of the Majority Decision Block to No Signal (0).
Figure 3.20: Majority decision block.
Figure 3.21: Disturbance noise detection block.
3.4
Behaviour Simulation with Test Signals
The performance of the algorithm was first tested using test signals as the input of the Simulink model that implements the algorithm. Starting with noiseless signals and then signals with AWGN and disturbance noise. The output of the algorithm (Signal classification) is plotted on figures below as Signal classification using 3 different possible values :
• 0 : No signal;
• 1 : FSK signal detected; • 2 :ASKsignal detected.
3.4.1 Ideal Conditions
Figures 3.22 and 3.23 are simulation results to signals without any noise added. Figures 3.24 and 3.25 plot the output of the algorithm to receiving ASK and FSK signals in suc-cession. In ideal conditions the performance of the detector has very stable performance, it classifies the signal correctly and keeps the classification until the reception ends, when it re-ceives two signals with different modulations in succession the detector switches to the correct classification within the required 640 µs.
0 5 10 15 20 25 30 35 40 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 5 10 15 20 25 30 35 40 time (ms) -1 0 1 2 3 Signal Classification ASK No Signal
Figure 3.22: Simulation result for an ASK test signal without noise.
0 10 20 30 40 50 60 70 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 10 20 30 40 50 60 70 time (ms) -1 0 1 2 3 Signal Classification FSK No Signal
0 10 20 30 40 50 60 70 80 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 10 20 30 40 50 60 70 80 time (ms) -1 0 1 2 3 Signal Classification FSK ASK No Signal
Figure 3.24: Simulation result for a FSK test signal followed by an ASK test signal without noise. 0 10 20 30 40 50 60 70 80 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 10 20 30 40 50 60 70 80 time (ms) -1 0 1 2 3 Signal Classification ASK FSK No Signal
Figure 3.25: Simulation result for an ASK test signal followed by a FSK test signal without noise.
3.4.2 Added AWGN
To measure performance under AWGN noise, noisy signals were created following the process explained in section 3.2.1 so that Matlab adds noise to the original signal resulting in a signal with the desired SNR.
For the first test, the noisy signal consists of an ASK signal followed by a FSK signal. Figure 3.26 plots the output with a noisy signal (Eb/N0 = 2) when compared to Figure 3.25 with equivalent signals and ideal conditions in the lower amplitudes of the signal AWGN noise augments the signal amplitude and makes the detector take longer to make a successful classification. 0 10 20 30 40 50 60 70 time (ms) -2 -1 0 1 2 Signal Amplitude 0 10 20 30 40 50 60 70 time (ms) -1 0 1 2 3 Signal Classification FSK ASK No Signal
Figure 3.26: Simulation result for an ASK test signal followed by a FSK test signal with AWGN noise (Eb/N0 = 2).
A second test was conducted using 6 consecutive ASK and balise passages and varying the speed of the train passage and the SNR of the AWGN noise. The figures bellow display the percentage of successful classifications for each Eb/N0, each curve represents a different velocity.
Analyzing both plots the conclusion is that the detector performs better detecting FSK test signals than ASK test signals and the percentage of successful classifications is lower at higher speeds, in part due to the fact that the detector has a fixed setup time. In this tests no false positive or false negative was found, meaning that the detector never classified an ASK/FSK signal as FSK/ASK and it never classified noise or absence of signal as ASK/FSK signal.
a)
b)
Figure 3.27: Detector performance for a) ASK and b) FSK test signals with different train speeds.
3.4.3 Added Disturbance Noise
To measure the effect of disturbance noise the process displayed in section 3.2.2 is imple-mented. Bellow are the results for the performance of the algorithm under disturbance noise using test signals with a peak disturbance amplitude 3 times the amplitude of the signal. Due to the use of filters at the input of the detector only noise with 3.9 and 4.5 MHz frequencies produced changes in the detector’s performance.
a)
b)
Figure 3.28: Disturbance noise test for test FSK(a) and ASK(b) signals (Peak disturbance to signal = 3).
Analysing plots in Figure 3.28 it’s clear that the percentage of unsuccessful classifications is higher with higher repetition rates and/or decaying factors because these increase the amount of noise in the signal.
The disturbance noise caused false positive classifications, ASK signal detected as FSK, and false negative classifications, noise signal classified as FSK signal, this only happened with the highest decaying factor (30) and repetition rate (15 kHz) and in a very small percentage.
a)
b)
Figure 3.29: False positive classifications with test ASK signals(a) and false negatives with test FSK signals(b) (Peak disturbance to signal = 3).
3.5
Behaviour Simulation with Real World Signals
To obtain results that are closer to reality the performance of the detector was measured with signals captured with a RF front-end. Due to the fact that these signals were captured in a practical setting and the inherent characteristics of the front-end used by CAF they already include small amounts of noise and different frequency components added by the front-end. The output of the algorithm (Signal classification) is plotted on the figures below. Signal classification can have 3 different possible values :
• 0 : No signal;
• 1 : FSK signal detected; • 2 : ASK signal detected;
0 2 4 6 8 10 12 14 16 18 20 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 2 4 6 8 10 12 14 16 18 20 time (ms) -1 0 1 2 3 Signal Classification ASK No Signal
Figure 3.30: Simulation result for a real ASK signal without noise.
In noiseless signals the performance of the detector, again, has very stable performance, although due to the small amounts of noise included it doesn’t classify the signal in very low amplitude this is negligible it represents a very small percentage of the signal.
0 10 20 30 40 50 60 70 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 10 20 30 40 50 60 70 time (ms) -1 0 1 2 3 Signal Classification FSK No Signal
Figure 3.31: Simulation result for a real FSK signal without noise.
0 10 20 30 40 50 60 70 80 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 10 20 30 40 50 60 70 80 time (ms) -1 0 1 2 3 Signal Classification ASK FSK No Signal
Figure 3.32: Simulation result for a real FSK signal followed by a real ASK signal without noise.
0 10 20 30 40 50 60 70 80 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 10 20 30 40 50 60 70 80 time (ms) -1 0 1 2 3 Signal Classification ASK FSK No Signal
Figure 3.33: Simulation result for a real ASK signal followed by a real FSK signal without noise.
3.5.1 Simulation results - added AWGN
The same procedure used to add noise to test signals was used to add AWGN noise to the real world signals. Figure 3.34 plots the output with a noisy real-world signal (Eb/N0 = 2), the effects on the detector performance are similar to the test noisy signal, the detector takes longer to make a successful classification at low amplitudes.
0 10 20 30 40 50 60 70 80 time (ms) -2 -1 0 1 2 Signal Amplitude 0 10 20 30 40 50 60 70 80 time (ms) -1 0 1 2 3 Signal Classification No Signal FSK ASK
Figure 3.34: Simulation result for a real ASK signal followed by a real FSK signal with AWGN noise (Eb/N0 = 2).
As plotted in Figure 3.35 that the algorithm has a better performance on the AWGN test for real world signals. Both with the test signals and real signals the system never classified an ASK signal as FSK or a FSK signal as ASK, every time noise affected signal classification the output defaulted to 0 (No Signal). This supports the robustness of the algorithm. Figure 3.34 shows the output for the worst case tested (Eb/N0 = 2).
3.5.2 Simulation results - Disturbance Noise
Bellow are the results for the performance of the algorithm under disturbance noise using real world signals. Figures 3.36 and 3.37 display the performance of the detector after receiving and ASK signal followed by a FSK with added disturbance of different characteristics.
Bellow are the results for the performance of the algorithm under disturbance noise using test signals. Due to the use of filters at the input of the detector only noise with 3.9 and 4.5 MHz frequencies produced changes in the detector’s performance.
Comparing the results in Figure 3.38 to the simulation results in Figure 3.28 the conclusion is that under the same noise conditions the detector performs slightly better for real-world signals than test signals.
The disturbance noise also caused false positive classifications and false negative classifica-tions with the real-world signals although in a slightly smaller percentage, this only happened with the highest decaying factor (30) and repetition rate (15 kHz).
Figure 3.35: Simulation of real signals under different Eb/N0. 0 10 20 30 40 50 60 70 80 time (ms) -4 -2 0 2 4 Signal Amplitude 0 10 20 30 40 50 60 70 80 time (ms) -1 0 1 2 3 Signal Classification No Signal FSK ASK
Figure 3.36: Disturbance noise test for real world signals Fs = 4.5 Mhz, Df = 30 and repetition rate = 1.5 kHz.
0 10 20 30 40 50 60 70 80 time (ms) -4 -2 0 2 4 Signal Amplitude 0 10 20 30 40 50 60 70 80 time (ms) -1 0 1 2 3 Signal Classification FSK ASK No Signal
Figure 3.37: Disturbance noise test for real world signals Fs = 3.9 Mhz, Df = 30 and repetition rate = 1.5 kHz.
a)
b)
a)
b)
Figure 3.39: False positive classifications with real-world ASK signals(a) and false negatives with FSK signals(b).
3.6
Response Time
As mentioned in subsection 2.2 ERTMS requires that a balise detection must take less than 640µs therefore a test for the response time of the signal was conducted. The test consists of running the detector with a sample of the real-world and test signals whose output is known, so there is no noise that can delay the output of the algorithm, and measuring the response time. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 0 1 2 3 Signal Classification ASK No Signal
Figure 3.40: Response time test of an ASK test signal.
Observing Figures 3.40, 3.41, 3.42 and 3.43 we can conclude the system is able to perform a balise detection in 540 µs, within the required time interval.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 0 1 2 3 Signal Classification FSK No Signal
Figure 3.41: Response time test of an FSK test signal.
3.7
Conclusion
The High level architecture of the modulation detector was established and so a Simulink model was created to model the architecture. During this step of the work, a platform to generate test signals and different types of noise was created and validated. Reference signals are also provided and analyzed. In the final part of this chapter, the performance of the Simulink model was evaluated using test and real-world signals. These performance tests of the model occur under ideal and non-ideal conditions, AWGN and disturbance noise.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 0 1 2 3 Signal Classification ASK No Signal
Figure 3.42: Response time test of a real-world ASK signal.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 -0.5 0 0.5 1 Signal Amplitude 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ms) -1 0 1 2 3 Signal Classification FSK No Signal
Chapter 4
Implementation and Testing
The objective of this chapter is the conversion of the Simulink model to VHDL code to implement the detector in the FPGA board. During this chapter several decisions were made to speed the implementation and testing of the system: using an FGPA development kit, using automated code generation techniques to convert the Simulink Model into VHDL code, using automated data type conversion tool. The processes used for the conversions are explained in detail. In the final part of the sections, the tests of the balise type detector running on the FPGA kit are displayed and analyzed. The testing setup is also explained in detail.
4.1
VHDL Code Generation
The Fixed-Point Tool (FPT) and HDL Coder are used to convert the Simulink model into synthesizable VHDL code. The FPT assigns fixed-point data types to all floating-point data types in the design and HDL Coder is the Matlab toolbox used to convert Matlab functions and Simulink models into synthesizable VHDL code.
4.1.1 Fixed-Point Data Convertion
The model implemented in Simulink uses doubles as the data type by default, but to achieve efficient FPGA implementation each floating-point variable must be converted to a suitable fixed-point data type that meets the quantization requirements. The Fixed-Point Tool (FPT), Figure 4.2, is a Matlab tool that converts floating-point data types to fixed-point.
The model was prepared for data type conversion following the steps of the Fixed-Point Advisor, Figure 4.1, in order to:
• ensure all Simulink blocks and model configurations chosen are compatible with fixed-point conversion;
• acquire a base line floating-point data set including real signals, test signals with and without added noise;
• evaluate block specific configurations;
• log minimum and maximum information to every block of the model. To analyse the floating-point data set the FPT is used in the following steps :
Figure 4.1: The different steps of the Fixed-Point Advisor 1. Propose Data Types: suggests a data type for each Simulink block 2. Apply Proposed Data Types: applies the suggested data types
3. Simulate with Embedded Types: the model is simulated using embedded types
4. Compare Results: The results of the previous simulation are compared to the original floating point results to check if they are within a tolerance of 2%
At the end of this step the Simulink model is ready to be converted to synthesizable VHDL code using Matlab HDL Coder.
4.1.2 HDL Coder
HDL Coder is a Matlab toolbox that generates HDL code to program FPGAs based of Matlab functions or Simulink models. The advantages HDL Coder presents to the development of this project are :
• High-level Hardware Design: a system is designed from an High-level perspective using Simulink blocks and Matlab Functions;
• Faster Hardware Development: algorithm and hardware design are done simultaneously which avoids time checking HDL syntax and coding rules;
• Earlier Verification: the behaviour of hardware blocks is verified earlier speeding the debugging process.
To generate the VHDL code and test bench the user follows the steps of the HDL Workflow Advisor, Figure 4.3.
Figure 4.2: Fixed-Point Tool.
4.2
Functional Simulation
A Functional Simulation was performed in Xilinx Vivado to confirm that the outputs of the Simulink model match the outputs of the VHDL code. In the previous step, HDL Coder generated a VHDL test bench and files with the signal inputs and expected outputs of the VHDL module. The Functional Simulation compares the outputs of the simulation, using the inputs provided by HDL Coder, with the expected outputs. Figure 4.4 displays the results of the functional simulation in Vivado, as expected the outputs of the functional simulation matched the outputs of the Simulink model and so the testFailure variable stayed at 0.
4.3
Synthesis and Implementation
Since the FPGA board is a Nexys-4, Xilinx Vivado was used to perform the synthesis and implementation of the VHDL code. Figures 4.5 and 4.6 show that the timing constraints were met and the utilisation of the board was around 50%.
Figure 4.5: Timing summary of the design.