Aula 25 - Chaves, sensores e schimitt trigger

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Aula 25 - Chaves, sensores e schimitt trigger

Prof. Renan Sebem

Disciplina de eletrônica digital Departemanto de engenharia elétrica Centro de Ciências Tecnológicas (CCT) Universidade Do Estado de Santa Catarina (UDESC)

Joinville-SC Brasil

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Itens da aula

Avisos

Chaves

Eliminação de ruídos

Encoder

Avisos

Referências

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Avisos

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Entrega do desenho da placa do trabalho nal dia 10/06/16;

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A aula de laboratório desta semana será sobre o trabalho nal;

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Quem possuir laptop deve trazer para a aula de lab;

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Chaves

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Chaves

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Chaves

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Chaves

Push Button & resistor de Pull Up

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Valor de saída normalmente em 1, usa-se resistor de pull-up;

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O push button sempre deve possuir um resistor de pull-up ou pull

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Chaves

Push Button & resistor de Pull Down

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Chaves

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Eliminação de ruídos

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Debounce RC (eliminando ruídos)

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Relembrando - Limites de tensão TTL

The meaning of the parameters above was seen in Section 1.8 and is repeated below.

V_IL: Maximum input voltage guaranteed to be interpreted as '0'.

VIH: Minimum input voltage guaranteed to be interpreted as '1'. VOL: Maximum output voltage produced by the gate when low. VOH: Minimum output voltage produced by the gate when high.

The noise margin can then be determined as follows, where NML represents the noise margin when

low and NMH represents the noise margin when high.

NML = VIL − VOL (10.1)

NM_H = V_OH − V_IH (10.2)

For TTL, NML = NMH = 0.4 V results. This means that any noise added to the input signals, when

having an amplitude under 0.4 V, is guaranteed not to corrupt the system.

10.4

Emitter-Coupled Logic

The last BJT-based family is ECL, which was developed for high-speed applications. Due to its perma-nent emitter current, it belongs to a category called CML (current-mode logic). In spite of its large power consumption and large silicon area (for transistors and resistors), ECL has the advantage of being the fastest of all logic circuits (employed, for example, in the construction of very fast registers, shown in Chapter 13).

An OR gate, constructed with traditional ECL, is depicted in Figure 10.8. The supply voltage is

VEE = −5.2 V, and the circuit also contains a reference voltage of −1.3 V. The logic levels are also unusual,

'0' = −1.7 V and '1' = −0.9 V. Its operation is based on a differential amplifi er (formed by BJTs with coupled

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FIGURE 10.7. (a) Supply and minimum/maximum signal voltages for the TTL family; (b) Corresponding noise margins.

10.4 Emitter-Coupled Logic 225

The meaning of the parameters above was seen in Section 1.8 and is repeated below.

V_IL: Maximum input voltage guaranteed to be interpreted as '0'.

VIH: Minimum input voltage guaranteed to be interpreted as '1'. VOL: Maximum output voltage produced by the gate when low. VOH: Minimum output voltage produced by the gate when high.

The noise margin can then be determined as follows, where NML represents the noise margin when

low and NMH represents the noise margin when high.

NML = VIL − VOL (10.1)

NM_H = V_OH − V_IH (10.2)

For TTL, NML = NMH = 0.4 V results. This means that any noise added to the input signals, when

having an amplitude under 0.4 V, is guaranteed not to corrupt the system.

10.4

Emitter-Coupled Logic

The last BJT-based family is ECL, which was developed for high-speed applications. Due to its perma-nent emitter current, it belongs to a category called CML (current-mode logic). In spite of its large power consumption and large silicon area (for transistors and resistors), ECL has the advantage of being the fastest of all logic circuits (employed, for example, in the construction of very fast registers, shown in Chapter 13).

An OR gate, constructed with traditional ECL, is depicted in Figure 10.8. The supply voltage is

VEE = −5.2 V, and the circuit also contains a reference voltage of −1.3 V. The logic levels are also unusual, ■

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FIGURE 10.7. (a) Supply and minimum/maximum signal voltages for the TTL family; (b) Corresponding noise margins.

10.4 Emitter-Coupled Logic 225

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Relembrando - Limites de tensão CMOS

10.6.4 Fan-In and Fan-Out

The defi nitions of fan-in and fan-out were seen in Section 10.3 (see Figure 10.6). As mentioned there, LS TTL (Figure 10.5) is used as the standard load for fan-out comparison. Because an LS input can sink 20 !A or source 0.4 mA, while an HC/HCT output can source or sink 4 mA, the HC/HCT’s fan-out is 10 (which is the smallest of 4/0.4 and 4/0.02).

10.6.5 Supply Voltage, Signal Voltages, and Noise Margin

The supply voltage and maximum/minimum allowed signal voltages constitute another important set of parameters for any logic family because they determine the power consumption and the noise margins. For example, it was seen in Section 4.2 that the dynamic power consumption of a CMOS inverter is given by Equation 4.6, so any change of VDD highly impacts the power consumption.

It was also seen in Section 10.3 that the noise margins when low and when high are given by

NML = VIL − VOL and NMH = VOH − VIH, respectively. For the HG family, these calculations are illustrated

in Figure 10.11(a), where gate A communicates with gate B. The bar on the left shows the voltage ranges that can be produced by A, while the bar on the right shows the voltage ranges that are acceptable to B. The nominal supply voltage is VDD = 5 V, and the worst case (4 mA) allowed maximum/minimum signal

voltages are VOL = 0.26 V, VOH = 4.48 V, VIL = 1 V, and VIH = 3.5 V. Consequently, NML = 1 − 0.26 = 0.74 V and NMH = 4.48 − 3.5 = 0.98 V result, which are listed in Figure 10.11(b).

Note that in Figure 10.11(a) it was assumed that gate A is sourcing/sinking a high current to/from gate B, so the output voltages are relatively far from GND and VDD (observe in Figure 10.10 that two sets

of values were defi ned for VOL and VOH, one for low current, the other for high current). In case B were a

CMOS gate (or several CMOS gates), A would operate with very small currents, so VOL and VOH would

be at most 0.1 V far from the rail voltages, yielding higher noise margins.

10.6.6 Low-Voltage CMOS

As mentioned above, modern designs employ almost exclusively low-voltage CMOS circuits. Even though their general architecture is still that seen in Chapters 4, 9, and again in this chapter, the sup-ply voltage was reduced from 5 V to 3.3 V, then to 2.5 V, 1.8 V, and 1.5 V. Recently, it was further reduced

10.6 CMOS Logic 229

FIGURE 10.11. (a) Voltage ranges for the HC CMOS family; (b) Corresponding noise margins.