Verilog HDL Introduzida em 1985 pela Gateway Design System Corporation Após 1990, passou a ser de domínio público, e em 1995 passou a ser padrão IEEE

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Verilog HDL

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Introduzida em 1985 pela Gateway Design

System Corporation

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Após 1990, passou a ser de domínio público,

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Verilog HDL vs. VHDL

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Verilog HDL é mais próxima a C

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VHDL é mais próxima a ADA

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Considerada mais fácil de aprendizado, pois

necessita de menos código para especificar

projeto

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module simple;

reg [0:7] A, B;

reg C;

initial begin: stop_at

#20; $stop;

end

initial begin: Init

A = 0;

$display("Time A B C");

$monitor(" %0d %b %b %b", $time, A, B, C);

end

always begin: main_process

#1 A = A + 1;

#1 B[0:3] = ~A[4:7];

#1 C = &A[6:7];

end

endmodule

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule 0 1 2 3 … 20 $stop

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule 0 1 2 3 … 20 $stop A=0 $display $monitor

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule 0 1 2 3 … 20 $stop A=A+1 $monitor

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule 0 1 2 3 … 20 $stop B[0:3] = … $monitor

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule 0 1 2 3 … 20 $stop C = &A[6:7] $monitor

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule 3 4 5 6 … 20 $stop A=A+1 … $monitor

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule 3 4 5 6 … 20 $stop B[0:3] = … … $monitor

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 3 4 5 6 … 20 $stop C = &A[6:7] $monitor

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module simple; reg [0:7] A, B; reg C; initial begin: stop_at #20; $stop; end initial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C); end always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule … 20 $stop

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Resultado do Primeiro

Exemplo

_{Time A B C} 0 00000000 xxxxxxxx x 1 00000001 xxxxxxxx x 2 00000001 1110xxxx x 3 00000001 1110xxxx 0 4 00000010 1110xxxx 0 5 00000010 1101xxxx 0 7 00000011 1101xxxx 0 8 00000011 1100xxxx 0 9 00000011 1100xxxx 1 10 00000100 1100xxxx 1 11 00000100 1011xxxx 1 12 00000100 1011xxxx 0 13 00000101 1011xxxx 0 14 00000101 1010xxxx 0 16 00000110 1010xxxx 0 17 00000110 1001xxxx 0 19 00000111 1001xxxx 0 Stop at simulation time 20

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Números e Comentários

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549 // decimal number

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'h 8FF // hex number

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'o765 // octal number

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4'b11 // 4-bit binary number 0011

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3'b10x // 3-bit binary number with least

/* significant bit unknown */

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5'd3 // 5-bit decimal number

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Descrição em Verilog

HDL

module <module name> (<port list>); <declares> <module items> endmodule ■

inputs

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outputs

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inouts

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Descrição em Verilog

HDL

module <module name> (<port list>); <declares> <module items> endmodule ■

regs + wires

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memories

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functions + tasks

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initial + always

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assinalamentos contínuos (assign)

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instâncias de módulos

Descrição em Verilog

HDL

module <module name> (<port list>); <declares>

<module items> endmodule

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Exemplos

module NAND(in1, in2, out); input in1, in2; output out; // continuous assign statement assign out = ~(in1 & in2); endmodule

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Exemplos

module AND(in1, in2, out); // Structural model of AND gate from two NANDS input in1, in2; output out; wire w1; // two instantiations of the module NAND NAND NAND1(in1, in2, w1); NAND NAND2(w1, w1, out); endmodule

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Exemplos

module test_AND; reg a, b; wire out1, out2; initial begin // Test data a = 0; b = 0; #1 a = 1; #1 b = 1; #1 a = 0; end initial begin $monitor("Time=%0d a=%b b=%b out1=%b out2=%b", $time, a, b, out1, out2); end AND gate1(a, b, out2); NAND gate2(a, b, out1); endmodule

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Referências e

Concatenações

initial begin: int1 A = 8'b01011010; B = {A[0:3] | A[4:7], 4'b0000}; end C = {2{4'b1011}}; //C = 8'b10111011 C = {{4{A[4]}}, A[4:7]}; // first 4 bits are sign extended

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Memórias

reg [31:0] Mem [0:1023];

Mem[0]

A = Mem[0]; B = A[3:1];

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Operações

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Operações similares a C

~ Bitwise negation & Bitwise AND

| Bitwise OR ^ Bitwise XOR ~& Bitwise NAND ~| Bitwise NOR

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Operações Unárias

& AND

| OR reduction ^ XOR reduction ~& NAND reduction ~| NOR reduction ~^ XNOR reduction

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Fluxo de Controle

if (A == 4) begin B = 2; end else begin B = 4; end case (sig) 1'bz: $display("Signal is floating"); 1'bx: $display("Signal is unknown"); default: $display("Signal is %b", sig); endcase

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Fluxo de Controle

for(i = 0; i < 10; i = i + 1) begin $display("i= %0d", i); end i = 0;_{while(i < 10)} begin $display("i= %0d", i); i = i + 1; end repeat (5) begin $display("i= %0d", i); i = i + 1; end

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Controle de Tempo

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Delay

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#10 a = 3;

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Ocorrência de eventos

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@ (posedge clock2) A = B&C;

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Referencias

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Cver

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http://www.pragmatic-c.com/gpl-cver/

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Tutorial Verilog

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http://www.asic-world.com/verilog/veritut.html

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Informacoes Gerais

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http://en.wikipedia.org/wiki/Verilog

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Projeto RTL

Blocos Lógicos Combinacionais

always @(a or b or c)

begin

case (a)

2’b00: d = b + c;

2’b01: d = b – c;

2’b10: d = b * c;

2’b11: d = b / c;

endcase

end

00 01 10 11 d + b c b c * c b c b /

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Projeto RTL

Registradores

always @ (posedge clk)

d = a;

D Q clk d a

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Projeto RTL

Registradores

always @ (posedge clk)

begin

case (a)

2’b00: d = b + c;

2’b01: d = b – c;

2’b10: d = b * c;

2’b11: d = 0;

endcase

end

00 01 10 11 + b c b c * c b 0 D Q clk d

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Projeto RTL

Memória

reg [15:0] R [0:7];

AD[3:0] DI[15:0] WR DO[15:0]

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module uRISC; reg [15:0] PC;

reg IF, ID, EX, WB, CLK;

always @ (posedge CLK) {IF,ID,EX,WB} = {WB,IF,ID,EX}; always @ (posedge CLK) PC = (IF)?PC+1:PC;

initial begin

IF = 1; ID = 0; EX = 0; WB = 0; PC = 0; CLK = 0;

$display("%10d: CLK=%d IF=%d ID=%d ...", $time,CLK,IF,ID,EX,WB,PC);

forever begin #10 CLK = 1;

# 0 $display("%10d: CLK=%d IF=%d ID=%d ...", $time,CLK,IF,ID,EX,WB,PC);

#10 CLK = 0;

# 0$display("%10d: CLK=%d IF=%d ID=%d ...", $time,CLK,IF,ID,EX,WB,PC);

if ($time > 100) $finish; end

end