[PENDING] Physical Design Issues in 3-D Integrated Technologies Vasilis F. Pavlidis, Eby G. Friedman
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![Fig. 2. Different forms of 3-D integration (not to scale), (a) system-in-package (SiP) [17] and (b) a 3-D circuit with dense through silicon vias [20], [21]](https://thumb-eu.123doks.com/thumbv2/1bibliocom/475775.77804/4.892.178.706.608.867/different-forms-integration-scale-package-circuit-dense-silicon.webp)
![Fig. 3. Examples of a through silicon via (not to scale) used in (a) SiP and 3-D CMOS technologies [14], [22] and (b) 3-D SOI processes [21]](https://thumb-eu.123doks.com/thumbv2/1bibliocom/475775.77804/5.892.338.574.473.656/fig-examples-silicon-scale-used-cmos-technologies-processes.webp)
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![Fig. 6. Multi-level routing for 3-D circuits. The technique can be adapted to include multiple objectives for routing a 3-D circuit [48]](https://thumb-eu.123doks.com/thumbv2/1bibliocom/475775.77804/10.892.222.687.257.511/routing-circuits-technique-adapted-include-multiple-objectives-routing.webp)
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