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[PDF] Top 20 AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN

Has 10000 "AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN" found on our website. Below are the top 20 most common "AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN".

AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN

AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN

... drive adiabatic dynamic CMOS logic. It uses two clocks as power supplies with 180° phase difference between ...from low to high or from high to low or remain unchanged ...varying power ... See full document

15

Implementation of an Efficient Ripple Carry Adder by Low  Power Techniques for Ultra Applications

Implementation of an Efficient Ripple Carry Adder by Low Power Techniques for Ultra Applications

... new low power solutions for very large scale ...the power dissipation which shows increasing growth with the scaling down of the ...the design process have been implemented to reduce the ... See full document

4

Design and Implementation of Low-Power and Area-Efficient for Carry Select Adder (Csla)

Design and Implementation of Low-Power and Area-Efficient for Carry Select Adder (Csla)

... simple approach is proposed in this paper to reduce the area and power of SQRT CSLA ...and power of the 64-b modified SQRT CSLA are significantly reduced by ...17.4% an 15.4% respectively. The ... See full document

9

Design of High speed Low Power Reversible Vedic multiplier and  Reversible Divider

Design of High speed Low Power Reversible Vedic multiplier and Reversible Divider

... become an essential property in future circuit design ...other design presented a fault tolerant reversible 4x4 multiplier ...and full adders. [7] Has proposed a design of reversible ... See full document

5

Low Power Reversible Parallel Binary Adder/Subtractor

Low Power Reversible Parallel Binary Adder/Subtractor

... in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical ...plays an important role when energy efficient computations are ...Binary Adder/Subtractor with Design I, ... See full document

12

An Efficient Power Optimized 1-bit CMOS Full Adder

An Efficient Power Optimized 1-bit CMOS Full Adder

... of full adder using different logic ...that design based on adiabatic PFAL logic gives superior performance when compared to other logic styles even though their transistor count is high in ... See full document

5

Area Efficient and A High Bit Rate Serial-Serial  Multiplier With On-the-Fly Accumulation by  Asynchronous Counters

Area Efficient and A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters

... new approach to form the entire partial product matrix in just n sampling cycles for an N x N multiplication instead of at least 2n cycles in the conventional serial-serial ...new approach to serial ... See full document

5

A Novel Argument to Use 8-BIT Media Processor for Low Power VLSI Design

A Novel Argument to Use 8-BIT Media Processor for Low Power VLSI Design

... The paper brings to light a novel argument of the use of a 8 bit processor in place of 32 bit or 64 bit processors, for low power chip design. The main point of consideration is that the designer has ... See full document

6

Design, Analysis, Implementation and Synthesis of 16 bit  Reversible ALU by using Xilinx 12.2

Design, Analysis, Implementation and Synthesis of 16 bit Reversible ALU by using Xilinx 12.2

... the design of programmable reversible logic gate structures, targeted for the ALU implementation and their use in the realization of an efficient reversible ...lowering power consumption of logic ... See full document

6

J. Microw. Optoelectron. Electromagn. Appl.  vol.14 número2

J. Microw. Optoelectron. Electromagn. Appl. vol.14 número2

... optical power transfers from one guide to another guide ...maximum power transfers from one guide to another occurs, is determined by the optical and geometrical parameters of the coupler and also, by the ... See full document

9

Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique

Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique

... VLSI Industry is witnessing rapid change of technology in past few years. As the CMOS channel is continuously scaling down into nanoscale region for concern of low power ,small area and high speed. While ... See full document

5

Interplay of Communication and Computation Energy Consumption for Low Power Sensor Network Design

Interplay of Communication and Computation Energy Consumption for Low Power Sensor Network Design

... with low data rate applications such as temperature and pressure ...have power efficient algorithms at the system as well as network ...dynamic power management (DPM) while making a routing ...find ... See full document

8

RF CMOS Transmitter Front-end with Output Power Combiner

RF CMOS Transmitter Front-end with Output Power Combiner

... of all the linear amplifiers. Although the efficiency grows when the conduction angle is lowered, the amplifier becomes less linear because turning off the transistor increases the number of higher harmonics generated ... See full document

79

Laboratory investigation of the effect of a new labyrinth with different length and width in the wing length of a triangular-shaped labyrinth weir

Laboratory investigation of the effect of a new labyrinth with different length and width in the wing length of a triangular-shaped labyrinth weir

... Vermilton and Tsang studied the efficiency of polyhedral weirs during aeration and increase of dissolved oxygen in the river. They came to the conclusion that polyhedral weirs, in comparison with linear weirs, have a ... See full document

5

Binding energies of excitons trapped by ionized donors in semiconductors

Binding energies of excitons trapped by ionized donors in semiconductors

... good adiabatic variable since it is related to the particles moment of inertia, which changes slowly ~adiabatically! compared to a ...The adiabatic approach using the HS coordinates is developed ... See full document

9

J. Braz. Soc. Mech. Sci. & Eng.  vol.34 número especial a05v34nspe

J. Braz. Soc. Mech. Sci. & Eng. vol.34 número especial a05v34nspe

... time, an on-off closed-loop control law was experimentally implemented with the prototype ...requires an “arrow” input signal from the strain gauges that measure the output load of the ... See full document

7

A low power engine test stand

A low power engine test stand

... the power flow, making possible control the dc-link voltage by controlling the power flow of the ...represents an advantage because it eliminates transformers and some other passive ... See full document

91

An Ultra Low Power Amplifier-less Sigma-Delta Modulator for Audio Applications

An Ultra Low Power Amplifier-less Sigma-Delta Modulator for Audio Applications

... less power and occupying less space, rendering this disadvantage ...achieve an relatively low E ffective Number of Bits (ENOB) of around 10 bits but at really high frequencies, oversampling ... See full document

143

An Ultra Low Power High Accuracy Current-Mode CMOS Squaring Circuit

An Ultra Low Power High Accuracy Current-Mode CMOS Squaring Circuit

... Many circuits have been implemented based on this principle using BJTs and MOS transistors in strong and in weak inversion regions [9, 10]. A family of a very low- power and low-voltage analog ... See full document

3

ADOBE ILLUSTRATOR AND GIMP - AN APPROACH TO GARMENT DESIGN

ADOBE ILLUSTRATOR AND GIMP - AN APPROACH TO GARMENT DESIGN

... garments design is Addobe ...tools an apparel designer needs to draw fashion design sketches, technical flat sketches, CAD presentations, graphic artworks, design embroideries ...to ... See full document

4

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