Top PDF Design of High speed Low Power Reversible Vedic multiplier and Reversible Divider

Vedic mathematics is the ancient Indian system of mathematics which mainly deals with Vedic mathematical formulae and their application to various branches of mathematics. Vedic mathematics was reconstructed from the ancient Indian scriptures (Vedas) by Sri Bharati Krisna Tirtha after his research on Vedas [16]. He constructed 16 sutras and 16 upa sutras after extensive research in Atharva Veda. The most famous among these 16 are Nikhilam Sutram, Urdhva Tiryakbhayam, and Anurupye. It has been found that Urdhva Tiryakabhayam is the most efficient among these. The beauty of Vedic mathematics lies in the fact that it reduces otherwise cumbersome looking calculations in conventional mathematics to very simple ones. Reversible logic is one of the promising fjelds for future low power design technologies. Since one of the requirements of all DSP processors and other hand held devices is to minimize power dissipation multipliers with high speed and lower dissipations are critical. This paper proposes an implementation of Reversible Urdhva Tiryakabhayam Multiplier which consists of two cardinal features. One is the fast multiplication feature derived from Vedic algorithm Urdhva Tiryakabhayam and another is the reduced heat dissipation by the virtue of implementing the circuit using reversible logic gates. Also we propose a new reversible division circuit. This proposed divider is unsigned division hardware. Our proposed reversible divider composed of reversible components like reversible multiplexer, reversible PIPO left-shift register, reversible register, reversible register with

Power dissipation is recognized as a critical parameter in modern VLSI design field. To satisfy MOORE’S law and to produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary. Fast multipliers are essential parts of digital signal processing systems.The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. In the past multiplication was generally implemented via a sequence of addition, subtraction, and shift operations. Multiplication can be considered as a series of repeated additions. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. In most computers, the operand usually contains the same number of bits. When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one collects and adds them. The basic multiplication principle is twofold i.e. evaluation of partial products and accumulation of the shifted partial products. It is performed by the successive additions of the columns of the shifted partial product matrix. The ‘multiplier’ is successfully shifted and gates the appropriate bit of the ‘multiplicand’. The delayed, gated instance of the multiplicand must all be in the same column of the shifted partial product matrix. They are then added to form the product bit for the particular form. To extend the multiplication to both signed and unsigned numbers, a convenient number system would be the representation of numbers in two’s complement format.

In the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversible Full adder using combination of all optical Toffoli and all optical TNOR and to compare it with the Full adder designed using all optical Toffoli gate in terms of optical cost. All optical TNOR gate can work as a replacement of existing NAND based All optical Toffoli Gate (TG). The gates are designed using Mach- Zehnder Interferometer (MZI) based optical switch. The proposed system is developed with the basic of reversibility to design all optical full Adder implemented with CMOS transistors. The design is efficient in terms of both architecture and in power consumption.

F. J. Chih et al [4] described that adders are fundamental building blocks and often constitute part of the critical path. In this paper, they proposed four high-speed ripple carry adder designs using the dynamic circuit techniques. The SPICE simulation shows that the proposed dynamic ripple carry adders are at least two times faster than the conventional static ripple carry adder. T. Himanshu et al [7] described that the reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This work proposed a new 4 × 4 reversible gate called “TSG” gate. The proposed gate was used to design efficient adder units.

With ever increasing applications in mobile communications and portable equipment, the demand for low-power, high-performance VLSI systems is steadily increasing. Digital signal processors and application specific integrated circuits rely on the efficient implementation of arithmetic circuits (adder and multiplier) to execute dedicated algorithms such as convolution, correlation and filtering [1]. A multiplier design using decomposition logic is presented here which improves speed when compared to the tree structured Dadda multiplier with very little power penalty. Pipelining is often used to improve the throughput of a design. A novel concept of modifying an adder to have latched outputs is presented to reduce the overheads of implementing pipelined structures.

The design of low power and high speed microprocessors requires that its components should consume less power. Arithmetic and Logic Unit (ALU) is one of the most power consuming components in a microprocessor. So, to reduce the power consumption of the entire ALU each of its components should consume less power. Here we concentrate on a 16 bit ALU implementation to perform 13 different operations which includes an adder/subtractor module using carry look ahead adder, a multiplier module using array multiplier, a shifter with 4 different shift operations and a logic unit by using reversible logic gates, heat dissipation due to information loss can be avoided if the circuit is designed using reversible logic gates.

Analog multiplier, Figure 1 is an important basic building block in communication systems like analog signal processing systems; for example frequency mixers, variable gain amplifiers, adaptive filters, phase-locked loop, amplitude modulators, frequency doublers, rectifiers and demodulators etc. It is necessary to design an analog multiplier circuit which is suitable for low power, low voltage and high speed applications with better linearity.

Thapliyal and Ranganathan [5] proposed the design of Reversible Binary Subtractor using TR Gate. The particular function like Binary Subtraction is implemented using TR gate effectively by reducing number of Reversible gates, Garbage outputs and Quantum Cost. Thapliyal and Ranganathan [6] presented a design of Reversible latches viz., D Latch, JK latch, T latch and SR latch that are optimized in terms of quantum cost, delay and garbage outputs.. Lihui Ni et al., [7] described general approach to construct the Reversible full adder and can be extended to a variety of Reversible full- adders with only two Reversible gates. Irina Hashmi and Hafiz Hasan Babu [8] designed an efficient reversible barrel shifter which is capable of left shift/rotate used for high speed ALU applications. Robert Wille et al., [9] explored two techniques from irreversible equivalence checking applied in the reversible circuit domain. (i) Decision diagram Technique equivalence checking for quantum circuits and (ii) Boolean satifiability checking for garbage input/outputs. Noor Muhammed Nayeem et al., [10] presented designs of Reversible shift registers such as serial-in serial-out, serial-in parallel-out, parallel-in serial-out, parallel-in parallel-out and universal shift registers. Majid Mohammadi, Mohammad Eshghi et al., [11] proposed a synthesis method to realize a Reversible Binary Coded Decimal adder/subtractor circuit. Genetic algorithms and don’t care concepts used to design and optimize all parts of a Binary Coded Decimal adder circuit in terms of number of garbage inputs/outputs and quantum cost.

Currently, fast decimal arithmetic is gaining popularity in the computing community due to the growing importance of commercial, financial, and internet-based applications, which normally process decimal data. Low power designs with high performance are given prime importance by researchers, as power has become a first-order design consideration. While efforts are being made to reduce power dissipation due to leakage currents, alternate circuit design considerations are also gaining importance. In recent years, reversible logic has emerged as one of the most important approaches for power optimization. Landauer’s principle states that a heat equivalent to kT*ln2 is generated for every bit of information lost, where k is the Boltzmann’s constant and T is the temperature [1]. Bennett showed that energy dissipation would not occur if the computations were carried out using reversible circuits [2] since these circuits do not lose information. Classical logic gates such as AND, OR, and XOR are not reversible. Hence, these gates dissipate heat and may reduce the life of the circuit. So, reversible logic is in demand in high-speed power aware circuits.

This design is advantageous than the previous two methods because, this design need not of connecting an extra bypassing circuitry since we are taking multiplicand bits instead of multiplier bits, and also with the help of BOOTH recoding unit we can definitely have at least one ‘0’ in the multiplicand. If multiplicand contains more zeros, higher power reduction can be achieved. Instead of bypassing rows of full adders, we propose a multiplier design in which columns of adders are bypassed. There is two advantages of this approach. First, it eliminates an extra correcting circuit needed; second, the modified Half Adder and Full Adder are simpler than that are used in the row-bypassing multiplier. Consider the multiplication shown in below figure, which executes 1010×1111. Here, in the first and third diagonals (enclosed by dashed lines), two out of the three input bits are 0: the “carry” bit from its upper right FA, and the partial product aibj (note that a0 = a2 = 0). As a result, the output carry bit of the FA is 0, and the output sum bit is simply equal to the third bit, which is the “sum” output of its upper FA. In this approach we propose Booth Recoding Unit will force multiplicand to have number of zeros, if does not have a single zero. The advantage here is that if multiplicand contains more successive number of one’s then booth- recoding unit converts these ones in zeros. More the number of zero’s more the power reduction can possible with high executing speed. Example for column bypassing:

ABSTRACT: Quantum Dot cellular Automata (QCA) is an emerging, promising alternative to CMOS technology that performs its task by encoding binary information on electronic charge configuration of a cell. All circuit based on QCA has an advantages of high speed, high parallel processing, high integrityand low power consumption. Reversible logic gates are the leading part in Quantum Dot cellular Automata. Reversible logic gates have an extensive feature that does not lose information. In this paper, we present a novel architecture of half subtractor gate design by reversible Feynman gate. This circuit is designedbased on QCA logic gates such as QCA majority voter gate, majority AND gate, majority OR gate and inverter gate. This circuit will provide an effective working efficiency on computational units of the digital circuit system.

In many real-time DSP applications number of complex multiplications are involved, in which high performance is a prime target. However, achieving this may be done at the expense of area, power dissipation and accuracy. The performance in terms of throughput of the processor is limited by the multiplication. So efforts have to be made to decrease the number of multipliers and to increase their speed. A high speed complex number multiplier design using Vedic Mathematics (Urdhva Tiryakbhyam sutra) is implemented using VHDL. This sutra is applicable to all cases of multiplication. The results show that Urdhva Tiryakbhyam sutra with less number of bits may be used to implement high speed complex multiplier efficiently in digital signal processing algorithms.

With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.

In digital co mputer system a major p roble m has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic c ircuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states . Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of th is reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so ma ny applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design imp le mentations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have imp le mented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family. Keywords: Lo w Po wer Consumption, Reversibility, NSG, Constant Input, Garbage Output, ALU.

In this paper, an area efficient multiplier architecture is presented. The architecture is based on Ancient algorithms of the Vedas, propounded in the Vedic Mathematics scripture of Sri Bharati Krishna Tirthaji Maharaja. The multiplication algorithm used here is called Nikhilam Navatascaramam Dasatah. The multiplier based on the ancient technique is compared with the modern multiplier to highlight the speed and power superiority of the Vedic Multipliers.

3. Dr. Syed Abdul Sattar, is presently working as a Dean of Academics & Professor of ECE department, RITS, Chevella, Hyderabad. He has completed his B.E. in ECE in 1990 from Marathwada University, Aurangabad, M. Tech. in DSCE from JNTU Hyderabad, in 2002, and did his first Ph.D. from Golden state University USA, with Computer Science in 2004, and second Ph.D. from JNTU Hyderabad, A. P. India with ECE in 2007. His area of specialization is wireless communications and image Processing. He has about 21years of experience in teaching and industry together and recipient of national award as an Engineering Scientist of the year 2006 by NESA

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then the second law of thermodynamics guarantees that no heat dissipation occur in the circuit[4]. In the synthesis of reversible circuit’s direct fan out and feedback is not permitted. A reversible circuit should be designed using minimum number of reversible logic gates in order to achieve efficiency and less complexity. There are some parameter in reversible circuit design for determining the complexity and performance of circuit, such as garbage output, quantum cost, constant inputs and total logical calculation [5]. Some important terms used in reversible logics are Garbage Output refers to the number of unused outputs present in a reversible logic circuit.

The presence of involutory symmetries and involutory reversing symmetries is very common in physical systems, for example, in classical mechanics, quantum mechanics and thermodynamic (see Lamb and Roberts 1996). The theory of ordinary differential equations with symmetry dates back from 1915 with the work of Birkhoff. Birkhoff realized a special property of his model: the existence of a involutive map R such that the system was symmetric with respect to the set of fixed points of R. Since then, the work on differential equations with symmetries stay restricted to hamiltonian equations. Only in 1976, Devaney developed a theory for reversible dynamical systems.