Low power is becoming more and more crucial and in many aspects becoming the number 1 priority when de- signing new applications. Ultralowvoltage CMOS is an approach for producing very low-power CMOS circuits by reducing the supply voltage to several hundred milli- volts [1, 2]. To maintain good performance at low sup- ply voltages, the threshold voltages of MOS transistors must also be reduced [3–5]. Unfortunately, this requires a change in the CMOS fabrication process. Because vari- ations in V th , when operating in a low-V dd and low-V th
the oscillator will also be changed. In Standard Logic CMOS 90nm process, the top metal is not ultra thick metal (UTM) and there are no standard inductors in foundry design kit (FDK). Therefore an accurate electro-magnetic (EM) simulation for inductor design is necessary and important.
The relatively low data rate in conjunction with small probe leads input capacitances minimize the transient current of the output drivers of the DUT. To help minimize this transient current even more, which is beneficial to generate less digital noise, series re- sistors, R36 to R44, are placed between the output drivers of the DUT and the probe leads connector, JP 18. These series resistors interact with the input capacitance of the probe leads and the parasitic capacitance of the PCB traces creating a low-pass filter that smooths the rising and falling edges of the output digital signals [15, pp. 743, 744]. A set of configuration switches (push-buttons), S1 to S6, permits to configure the system according to distinct testing scenarios, as explained in Appendix A. The configu- ration circuit in the PCB is very simple because each input digital driver has an enabled pull-down resistor, leading to a normally lowlogic level, unless the corresponding push- button is pressed. Furthermore, each input driver has a Schmitt trigger circuit enabled, which turns the digital inputs more insensitive to noise. The robustness against noise is enhanced even more with on-chip synchronous sampling, on the clock edges opposite to those related to the output data updates (i.e., after the supply of the output drivers has partially, or completely, settled).
V. ARCHITECTURE OF 32X32 BIT REVERSIBLE VEDIC MULTIPLIER The digitallogic implementation of the 2X2 vedic multiplier using the reversible logic gates is as shown in figure 4. This design does not consider the fan outs. The circuit requires a total of six reversible logic gates out of which five are Peres gates and remaining one is the Feynman Gate. The quantum cost of the 2X2 vedic multiplier is enumerated to be 21. The number of garbage outputs is 9 and number of constant inputs is 4. The reversible 4X4 vedic multiplier design emanates from the 2X2 multiplier. Similarly, the reversible 8X8 vedic multiplier design emanates from the 4X4 multiplier. The reversible 16X16 vedic multiplier design emanates from the 8X8 multiplier. The reversible 32X32 vedic multiplier design emanates from the 16X16 multiplier.
Transmission gate based delay element  is fast due to relatively low resistive path between input and output. It is power and area efficient and has full swing output. However, the delay increases quadratically with the number of cascaded transmission gates . Differential DE based on low noise Source Coupled Logic (SCL)    mitigates the common mode noise, which is prevalent in CSI. They are fast but have partial output swing and are power inefficient due to the high static current. In addition, they require a complex bias circuitry for delay variation. This paper presents a design of voltage controlled delay element based on modified version of Current Balanced Logic (CBL)  and is referred here as Modified CBL (MCBL) delay element. The salient features of this delay element are identical delays in the rising and falling edge transitions, highspeed, area efficient, less contribution in the generation of ‘di/dt’ switching noise and low power consumption as compared to other architectures of differential delay elements.
Looking at most converters reported from the year 1997 onwards, in both Interna- tional Solid-State Circuits Conference (ISSCC) and Symposium on VLSI Circuits (VLSIC), and plotting each converter’s resolution versus its sampling speed (Fig. 2.20), it’s possible to observe that the architectures more suited for specifications such as moderate-to-high resolution (> 8 bits) and moderate-to-high-speed (> 10 MS/s), are indeed either the Pipeline and SAR structures. Despite Σ∆Ms reaching resolutions in the 12-to-16 bit inter- val, they are noticeably slower, usually more power-hungry and present limited dynamic range, the latter being a consequence of the notorious potential for instability that charac- terizes this architecture. Considering that BPΣ∆Ms require double the order of their BB equivalents in order to reach a similar performance, this becomes even more of a issue.
The high-quality (i.e., very low phase noise) external analog input is provided by an RF signal generator, Marconi Instruments 2041. In order to remove the harmonics of the generated signal (intrinsic to this kind of generator), the analog input is bandpass or low-pass filtered before being applied to the test board. In this work, the following Mini-Circuits passive filters were used: SBP-10.7, SLP-100+, SLP-250+, SLP- 550+, and SLP750+. The external clock signal, both for ADC clocking or for the reference clock of the PLLs, is provided by another RF signal generator, Rohde&Schwarz SMB100A/SMB-B112. This generator also has very low phase noise. For instance, the integrated rms jitter in the bandwidth from 100 Hz to 2 GHz at 1 GHz is merely 210 fs. The ADC output data are captured with a logic analyzer, Agilent 16702B/16715A, and the data are then remotely transferred to a personal computer and processed in MATLAB. A set of on-board push-button switches allows the configuration of the system and the selection of the desired test mode.
A multiplier is an important part of digital signal processing systems, like frequency domain filtering (FIR and IIR), frequency-time transformations (FFT), Correlation, Digital Image processing etc. Multipliers have large area, long latency and consume considerable power. While many previous works focused on implementing high-speed multipliers, recently there have been many attempts to reduce power consumption . This is due to the increased demand for portable multimedia applications, which require low power consumption as well as highspeed.
CMOS differential logic style with voltage boosting has been described. The BCDL provides higher switching speed than the conventional logic style at low supply voltage. By allowing a single boosting circuit to be shared by complementary outputs the BCDL minimizes the area overhead. Comparison results in a 0.180- μm technology of Mentor Graphics EDA tool indicated that the energy– delay product of the proposed logic style was improved when compared with conventional logic styles. Here present two high-speed and low-power full-adder cells designed. Logic styles that lead to have a reduced power-delay product (PDP). The experiment result for a adder designed with BCDL logic style revealed an reduction in the addition time. The practical application in ripple carry adder proves that it can operate in low supply voltages with a decrease in propagation delay. So BCDL is a best choice for adders especially for ripple carry adders which is the slowest among all the adders.
With ever increasing applications in mobile communications and portable equipment, the demand for low-power, high-performance VLSI systems is steadily increasing. Digital signal processors and application specific integrated circuits rely on the efficient implementation of arithmetic circuits (adder and multiplier) to execute dedicated algorithms such as convolution, correlation and filtering . A multiplier design using decomposition logic is presented here which improves speed when compared to the tree structured Dadda multiplier with very little power penalty. Pipelining is often used to improve the throughput of a design. A novel concept of modifying an adder to have latched outputs is presented to reduce the overheads of implementing pipelined structures.
Abstract — In this paper a wideband MOS quadrature oscillator constituted by two multivibrators is presented. Two different forms of coupling, named here as soft and hard, are investigated. Simulations are performed in a 0.13 µm CMOS technology to obtain the tuning range, the synchronization transients, and the influence of mismatches in timing capacitors and charging currents on synchronization. It is found that hard coupling reduces the quadrature error (about 1º, with 5% mismatches in timing capacitors and charging currents) and results in a low phase-noise (about 2 dB improvement) with respect to soft coupling. Either a single multivibrator or coupled multivibrators can be locked to an external synchronizing harmonic frequency, and the locking range is investigated by simulations. The simulations are done for oscillators covering the WTMS frequency bands.
Dynamic characteristics of the priority control system are of great influence to the control effect, response speed, and working stability of the high-speed on–off digital valve. The main focus of this study is on revealing the dynamic proper- ties of the priority control system for a developed high-speed on–off digital valve. In this article, a detailed introduction to the high-speed on–off digital valve and its priority control system is performed first, which includes the system func- tion, structural composition, and operation principle. Thereafter, a simulation model of the priority control system is established using the AMESim software and the dynamic characteristics are simulated. Simulation results including the variations in the pulse-width modulation signal, coil current, and the main spool displacement of the directional valve are presented and discussed. They indicate that the opening time of the main spool increases with the duty ratio of the vol- tage signal. Moreover, the main spool displacement is basically equal in one single pulse-width modulation signal cycle, and thus, it is proportional to the cycle number of the pulse-width modulation signal. As a consequence, the priority control system possesses a good dynamic characteristic for the high-speed on–off digital valve as a pilot valve to achieve proportional control of main spool displacement for the directional valve.
Abstract — A new current-mode squaring circuit that can be used as a basic building block in analog signal processing systems is proposed. The design is based on MOS operating in the subthreshold region to assure lowvoltage and low power consumption. The performance of the design was confirmed by HSPICE simulation in 0.18m CMOS process. The circuit is operated by ±0.7V supply voltage and consumes 0.2µW and maximum linearity error of 1.4%.
detected, probably due to the high wear rate that removes any crack that appears at the contact surface. The wheel material presents a higher wear rate than the rail material, which is more noticeable in dry tests. This difference in the wear rate is the cause of the corrugations observed in the contact surfaces of the discs tested in dry conditions (Fig. 5), due to the fact that the used twin disc machine imposes the same rotating speed in the two discs and if one has higher wear it’s diameter will be different than the other disc, consequently the tangential speed of the two discs on the contact will be different and sliding is verified. No significant influence of the extraction position of discs from the real wheel and rail profiles was detected on the results.
The Transmission gate is designed using PMOS and NMOS transistors in 180nm technology and the dynamic body bias is provided by means of a potential divider using poly resistors. The widths of the transistors are fixed as 15 and 30nm for N and PMOS respectively. The design is implemented in 180nm using Cadence Tools. The decoder is designed by AND gates using sub threshold source coupled logic. The output of the decoder drives the Transmission gates. The responses of the decoder Transmission gates and multiplexer and are shown in Fig’s 8, 9 &11 respectively. The total power dissipation is measured as 337nW upto a frequency of 4 KHz. This circuit can be used to acquire EEG signals from 16 channels as mentioned in Table 1 consisting maximum frequency of 70Hz and are sampled at 250Hz. The circuit designed is simulated with a maximum switching frequency of 4 KHz to accommodate all 16 channels and the total power consumed is measured as 337nW. Since the maximum power consumed is by the decoding circuitry a different technique can be utilized to reduce this power consumption. A CKNOWLEDGEMENTS
Color is an important characteristic of extruded foods. Color changes can give information about the extent of browning reactions such as caramelization, Maillard reaction, degree of cooking and pigment deg- radation that take place during the extrusion process (Altan et al., 2008). Analysis of the starch color com- ponents before and after extrusion evidenced that the values of the L* component from extruded starch var- ied from 72.08 to 82.98, indicating a decrease in lu- minosity after extrusion when compared with the ini- tial luminosity of 92.21. Out of the parameters that constitute the regression model, barrel temperature and feed moisture affected luminosity. The interaction be- tween barrel temperature and screw speed also had a significant effect.
Abstract- In this paper, a low-voltage current mirror with neuron MOSFETs is proposed. The proposed circuit can decrease a variation of an output current of the current mirror by monitoring an error of the output current caused by the mismatch of MOSFETs. In addition, the proposed circuit can avoid a trade-off between an accuracy and an output swing. The proposed circuit is fabricated in phenitec 0.6μm CMOS process.
20. Kotecha A, Elsheikh A, Roberts CR, Zhu HG, Garway-Heath DF. Corneal thickness- and age-related biomechanical properties of the cornea measured with the ocular response analyzer. Invest Ophthalmol Vis Sci [Internet]. 2006[cited 2012 May 21]; 47(12):5337-47. Available from: http://www.iovs.org/content/47/12/5337.long 21. Ambrósio R Jr., Ramos I, Luz A, Faria FC, Steinmueller A, Krug M, et al. Dynamic ultra-
machining of Ti-6Al-4V alloy with 883 inserts under dry cutting conditions where low surface roughness was obtained with the increase in cutting speed. In addition, at higher spindle speed, the chip will break away with less material deformation at the immediate tool tip, which in turn preserves the machined surface properties leading to minimal surface roughness. However, it is believed that the spindle speed should be controlled at an optimum value, as the influence of high temperature would significantly affect the chip formation mode, cutting forces, tool life and surface roughness. The surface roughness could be improved by increasing cutting speed, though the improvement is very limited at higher cutting speed (100-150 m/min). Producing an enhanced surface finish at elevated cutting speed is eminent in metal cutting. The conventional explanations are related to built-up-edge (BUE); i.e., the formation of BUE is favored in a certain range of cutting speed. By increasing cutting speed beyond this region, BUE is eliminated and as a result, the surface finish is improved. During our current investigations on Ti-6Al-4V alloy machining, the cutting speeds are higher than those favoring BUE formation. According to Chen 40 and Bouacha et al. 9 , the deformation
The modelling framework proposed in this paper is inspired by a set of projects for the development of highspeed rail (HSR) lines in Europe. The structuring nature of the projects for the countries involved; the need to renew the railway sector; the huge amounts of money needed; the uncertainty about the timings to invest and the economic challenge inherent in developing a conceptual setting for a decision that needs to be taken in the interest of the entire set of European taxpayers, all play a part in providing relevance to the study of the embedded option to defer and the optimal timing to invest.