Charge Coupled Devices

The charge coupled devices (CCDs) are a major technology for digital imaging in-vented in 1969 by Willard S. Boyle and George E. Smith [95] at Bell Telephone Labo-ratories. Initially conceived to operate as an electronic analog of the magnetic bubble memory, Boyle and Smith's invention was quickly perceived as an imaging semiconductor circuit. A complete review of the CCD functioning is presented in [96].

Figure 3.5: Compilation of WIMP-nucleon spin-independent cross section limits (solid curves) and hints for WIMP signals (shaded closed contours) obtained by dierent ex-periments. The projected sensitivity for upgraded versions of some experiments are rep-resented by dotted lines. The orange line is called the neutrino oor, a limit for which the experiments will be also sensitive to neutrino coherent scattering, an interaction with signature identical to the one expected for dark matter. Figure taken from [94]

In a CCD sensor, the important physical quantity is a packet of charges, electron-hole pairs (e-h), that can be generated in a semiconductor. A metal-oxide-semiconductor (MOS) capacitor is a structure that can store this packet. The CCD circuit is a two di-mensional array of MOS capacitors placed very close together such that, by manipulating the voltages on the gates of the capacitors, the charge can be moved from one capacitor to the next (thus the name charge-coupled device). At the end of this chain, a charge detection amplier detects the presence of the charge packet, providing an output voltage that can be processed to obtain the image¹.

1In the original memory device idea, the charge packet represents the bit of the information. The voltage manipulation provides a data reading and erasing mechanism, while the charge could be injected at the MOS capacitors (writing) using an input diode next to the CCD gate

The basic structure of the CCD is the MOS capacitor. Generically, this device consists in a doped semiconductor substrate with a dielectric layer grown above it and a conductor gate. To relate directly with DAMIC CCD, this text assumes a device with a n-doped silicon substrate, a silicon dioxide SiO2 insulator and doped polysilicon conductor gate.

An schematic view of the device is shown in gure 3.6. When a negative bias voltage is applied in the gate, holes will accumulate at the Si-SiO2 interface while electrons are driven way from it. This leaves behind a region depleted from charge carriers. The depletion region is non-conductive, acting as a insulator with a capacitance C = ε_Si/x_d (innite plates), where x_d is the thickness of the depletion region. Moreover, because of the lack of charge mobiles, any electron-hole pair generated in this region will be trapped in the potential well since they will not recombine. The size xd of the depletion region depends on the bias voltage, reaching its maximum value, or full depletion, for a given value of the voltage.

The simplest way to arrange an array of MOS capacitors in a CCD imager is called the three phase conguration. In this arrangement, the CCD pixel is composed by three MOS capacitors. The gates are placed in parallel and each of them separately is connected to phase 1, 2 and 3 of the clock. Every triplet of capacitors is connected to the same clock driver as depicted in gure 3.6. An appropriate manipulation of the voltages (1,2,3) at the gates allows to transfer charge from pixel to pixel up to a sense node, an structure capable of measure the charge stored in each pixel. Figure 3.7 displays the time diagram of a three-phase device.

The CCD array can be visualized as rows and columns. Columns or vertical regis-ters are separated by potential barriers called channel stops which prevent the spread of the charge between adjacent columns. The rows of pixels are separated by conductive electrodes responsible for the readout clock. The charge transfer is done by rst moving vertically each row of pixels up to a nal row called the horizontal register. At the hor-izontal register, the charge is moved from column to column and measured at the sense node. A scheme for the CCD structure involved in this charge transfer mechanism is

++

Figure 3.6: Left: Sketch of a silicon MOS capacitor, the basic unit of a CCD. Applying a negative bias voltage, drives the electrons way from the Si-SiO2 interface and create a depletion region which acts as a capacitor. Right: The three phase conguration and the voltage manipulation scheme responsible to transfer charge collected at the potential well from MOS capacitor to MOS capacitor and, ultimately, pixel to pixel.

shown in gure 3.8. An ecient charge transfer procedure is critical for the proper CCD functioning. Virtually no charge must be lost in this process as the net result of such loss over many pixels could complete destroy the image. Modern CCDs can easily achieve a charge transfer eciency larger than 99.99999%.

The readout system is the nal step to obtain an image. The charge of each pixel is dumped onto a small capacitor connected to an output FET (Field Eect Transistor) amplier, a point in the CCD called the sense node. The output amplier generates a

1 2 3

t

Figure 3.7: Time diagram of a three-phase device. The clock square waveform is shifted between the phases (1 → 2,2 → 3and 3 → 1 of the next pixel) by 1/3 of the period necessary to transfer charge from one pixel to another.

3x3 pixel

1 2 Vertical Register 3

Horizontal Register

Channel stop

Sense node 1 2 3

Figure 3.8: CCD structure for the charge transfer mechanism. The physical delimitation of a pixel is done by the channel stop potential barrier and clock electrodes.

voltage for each pixel proportional to the signal charge transferred. The amplier's gain and therefore the output signal is related to the capacitance at the sense node. Over the years, a huge eort was made to develop an output capacitor extremely small.

The CCD performance is determined by four primary tasks involved in the CCD operation: charge generation, collection, transfer and measurement. Each of these char-acteristics and its limitations will determine the CCD scientic application.

The charge generation is related with the internal quantum eciency (QE), a function which measures the fraction of incident photons that are converted in useful charge for detection. The QE can be understood initially in terms of the photon absorption length, the mean distance traveled by a photon inside a material before being absorbed. This function has a dependency on the photon wavelengths. Figure 3.9 shows the photon ab-sorption length as function of the light wavelengths for silicon. For wavelengths below 500 nm, silicon has relatively small absorption length meaning that the photon is immediately absorbed on the material surface. Close to the boundary, the CCD has a thin silicon layer (a few microns) not active for detection. With this prompt absorption photons can not pass this dead layer and are not converted in charge, thus reducing the QE. Above 900 nm, silicon becomes increasingly transparent to the light, also lowering the QE value. At this

region, some improvement in the detector QE are achieved by designing thicker devices.

Also, the photon absorption length indicates the QE for a pure silicon CCD. However, another mechanism may prevent the photon conversion in charge pairs for detection. For example, in the case that the detector exposed area is the side with the polysilicon gates, some photons will be lost in these conductors, lowering the QE. For this reason, CCDs are back illuminated, i.e, the exposed area is the bulk silicon.

Figure 3.9: Absorption length in silicon as function of the incident photon wavelength.

For wavelengths below 500 nm, the absorption length is less than a micron meaning that the photon is immediately absorbed on the material's surface. Above 900 nm, silicon becomes increasingly transparent to the photon. Figure taken from [97]

Any electron-hole pair created in the depletion region will be collected by the MOS capacitor potential well. The main issue for the charge collection is the bias condition for a fully depleted CCD, the detector size and the well capacity. Beside the cost limitation, there are two physical aspects that should be considered to determine the CCD size.

First, detectors with larger thickness require higher bias voltage to achieve full depletion.

Thicker devices are produced with a low donor density in the silicon substrate. This allows

for a high resistivity substrate, leading to a fully depleted operation at low values of bias voltages. The CCD xy size would be restricted by long readout time and charge transfer ineciency. Then, the well total capacity, maximum number of holes that a pixel can hold, is determined by the pixel size. While small pixels gives greater image resolution, big pixels have more well capacity. The CCD design is a compromise solution of these aspects.

It was previously stated that no charge can be lost in the charge transfer process.

Over many pixels, such loss completely destroys the CCD image. In the CCD architecture presented in gure 3.6, the charge packet is stored on Si-SiO2 surface. The losses during the charge transfer for a CCD in this conguration will be huge, and the device inecient.

To avoid this problem, the buried channel, a extra layer of p-type silicon added inside the Si-SiO2 surface, was developed. With this modication the potential well is shifted away from the gates and the charge packet is held at the p-n junction. The losses during the charge transfer are strongly reduced in a device with a buried channel. Also, one should note that an ecient charge transfer process impacts at the readout time. The clock controlling the voltage manipulation at the gates should have a maximum frequency in order to prevent sudden changes in the potential well that could lead to charge loss.

The charge measurement at the sense node is a critical task for the CCD performance.

The CCD success as a low energy threshold detector is determined by the sources of noise in the device. The array of MOS capacitors itself is passive in the sense that it does not require power to work. A xed bias voltage is applied to create the depletion region and the potential well, not adding noise in the charge packet. However, some charge may be thermally excited from valence to conduction band, an eect called dark current. In practical application, the term leakage current is also used, meaning any charge generated in absence of ionizing radiation. This broader denition includes spurious charge that may be created by some component in the CCD circuit or in mechanical stress for example.

This eect is minimized at cryogenic temperatures. The charge transfer process is assumed to be ecient and therefore does not aect the charge collected. On the other hand, the

sense node is an active element that requires power, being the major source of noise in a CCD. An example of readout node circuit is shown in gure 3.10. This design applies the Correlated Double Sampling (CDS) technique, providing a powerful noise reduction.

A signicant component of the noise is introduced at the end of the pixel readout, when a reset pulse is used to eliminate the pixel charge after the measurement. In the CDS, the pixel voltage is measured a rst time just after the reset pulse, and a second time after the charge has been moved into the pixel. When making the dierence between these two voltage levels, the reset noise is canceled. With appropriate optimization of the integration time windows for the charge measurement, readout noise of a few electrons is achieved.

Figure 3.10: Schematic of a CCD readout node, with the sequence of voltage levels used for the Correlated Double Sampling technique.

An important remark is that additional artifacts can be added to the CCD allowing the monitoring and reduction of the noise and leakage current levels. By using two identical output ampliers, one to actually measure the charge collected at the CCD exposure and another to perform a measurement after the collected charge being reset by the rst, a two sided image is obtained. One side (the right will be used by convention) is the image obtained at the exposure. The other side (left) is only noise generated by the sense node (there is a dark current component that may occur during the readout process that is being neglected). More than that, after the readout process is concluded, one can use the

same process but for an eectively 0 second exposure. This produces a blank image for which the charge observed in the images is purely readout noise. An important technique called overscan can be used as well. The CCD size denes the clock used to do the charge transfer. One can over-read the CCD by setting the clock for an image larger than the physical one. This produces extra columns and rows at the end of the physical images that are also a measurement of the noise from the sense node. Chapter 4 presents an analysis that made use of all of these artifacts to process images acquired by DAMIC CCDs and further details are found there. Lastly, another important method to increase the signal to noise ratio in a CCD, is to degrade the spatial resolution. Instead of using all pixels separately, what will be called 1×1 mode (maximum spatial resolution possible), one can re-bin the image to dumpN pixels in just one, producing ann×m image². This procedure reduces the charge uctuations.