O simulador AIMSPICE é estudado e usado neste trabalho para realizar o estudo comparativo do ruído fliker (1/f) entre amplificadores operacionais de transcondutância implementados tecnologia convencional e GC SOI nMOSFET, pois incorpora um modelo de terceira geração para dispositivos SOI MOSFETs (BSIM3SOI) e também o modelo de ruído unificado (LEVEL=19), que é fundamental para a realização desta obra.
É estudada a metodologia de desenvolvimento de projeto de circuitos integrados analógicos, que usa a curva universal gm/IDSxIDS/(W/L) para uma determinada tecnologia.
A descrição do projeto de amplificadores operacionais de transcondutância com tecnologia convencional e GC SOI nMOSFET são realizados mediante a utilização da metodologia de projeto gm/IDSxIDS/(W/L).
A calibração dos parâmetros SPICE do BSIM3SOI foi realizada utilizando os resultados experimentais de curvas características em corrente contínua e de resposta em freqüência (AVxf e Fasexf) descritas na literatura.
A calibração do modelo do ruído flicker (1/f) unificado do BSIM3SOI é realizada também a partir de resultados experimentais do SOI nMOSFET convencional e GC SOI nMOSFETs que também são descritos pela literatura. A validação do circuito equivalente do GC SOI nMOSFET (associação série entre dois transistores SOI nMOSFETs convencionais) para o estudo do ruído flicker (1/f) foi realizada com sucesso e conseguiu reproduzir os resultados experimentais descritos na literatura.
Este trabalho realiza um estudo comparativo do ruído flicker (1/f) entre OTAs implementados com SOI nMOSFET convencional e GC com razão LLD/L=0,33, por
simulação SPICE, usando o modelo BSIM3SOI, e calibrado por resultados experimentais, considerando três condições de simulação ou objetivos de projeto (DT) diferentes. O uso do GC SOI nMOSFET ao invés SOI nMOSFET convencional nos OTAs, de similar comprimento de máscara, melhora o ganho de tensão de malha aberta (AV0), sem degradar a
margem de fase, mas em contrapartida piora a densidade espectral de ruído flicker (1/f), devido ao seu menor comprimento efetivo de canal. Aumentando-se o comprimento de máscara do canal dos GC SOI nMOSFETs para obter um comprimento efetivo de canal semelhante ao convencional, o nível de ruído torna-se semelhante e preserva um maior ganho de tensão de malha aberta, porém com a desvantagem de aumentar a área de silício (5%), devido ao aumento do comprimento efetivo de canal. Fixando a freqüência de ganho de
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tensão de unitária, o comprimento efetivo de canal e o nível do ruído flicker, pode-se decrescer em até 33% a largura de canal do GC SOI nMOSFET (migrando o regime de inversão do GC SOI nMOSFETs no sentido da inversão forte), no qual resulta numa importante redução de área de máscara do OTA de aproximadamente 19 %, sem degradar a margem de fase e a tensão de corrente contínua na saída do amplificador, ou seja, preservando a máxima excursão do sinal de saída.
Anexo A
Exemplos de simulação SPICE usados na calibração do trabalho usados no software AIM SPICE usando nível 19 para BSM3SOI :
a) Arquivo SPICE usado para simulação OTA Convencional para análise de ganho de tensão de malha aberta e em função da freqüência
Amplificador Operacional (OTA/High Frequency) utilizando SOI Convencional - Data: 15/02/2006.
* Bias Voltage Vdd 1 0 4V
* Differential Mode Voltage VINNEG 8 0 DC 1 AC 1 VINPOS 13 0 DC 1 ****** Differential Circuit Icc 2 3 2.40mA * Charge Capacitor CL 15 0 7p
* Current source transistors
M09 3 3 0 0 tipon W=600E-6 L=3E-6
M10 10 3 0 0 tipon W=600E-6 L=3E-6
* Active Charge of Differential Stage
M03 6 6 1 0 tipop W=300E-6 L=3E-6
M04 11 11 1 0 tipop W=300E-6 L=3E-6
M05 4 6 1 0 tipop W=300E-6 L=3E-6
M06 14 11 1 0 tipop W=300E-6 L=3E-6
M07 5 5 0 0 tipon W=200E-6 L=5E-6
M08 15 5 0 0 tipon W=200E-6 L=5E-6
* Differential Pair
M01 7 8 9 0 tipon W=600E-6 L=3E-6
M02 12 13 9 0 tipon W=600E-6 L=3E-6
****** Fontes de tensao em 0V (amperimetro) V1 1 2 0 V2 4 5 0 V3 6 7 0 V4 9 10 0 V5 11 12 0 V6 14 15 0 ****** Transistors Models * n-MOSFET
.MODEL tipon NMOS +LEVEL=19
+MOBMOD=2 SHMOD=0 DDMOD=0
+TNOM= 27 TOX= 30e-9 TSI= 80e-9 TBOX = 390e-9
+VTH0= 0.4
+NCH= 1e17 NSUB=1e17 NGATE = 0
+RBODY = 0 RBSH = 0
+CDSC = 0 CDSCB = 0 CDSCD = 0
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* Parametros para Tensao de Early
+VSAT = 1.6e5 PVAG = -100 LINT = 0.5E-7 WINT = 0.5e-9
+A0 = 1 AGS=0 A1=0
+A2 = 0.99 KETA = 3.2e-2
+K1 = .59 KT1 = -.28 KT1L = 8e-9 +KT2 = -.0646 K2 = 0 K3 = -3.5 +K3B = 0 W0 = 0 +NLX = 6.3E-8 DVT0 = 200 DVT1 = 3.72 +DVT2 = 0.19 DVT0W = 0 DVT1W = 0 +DVT2W = 0 DROUT = 3.617 DSUB = 0.56
+UA = 1.2e-8 UA1 = 3.37e-10 UB = 2.2e-18 +UB1 = -3.12e-18 UC = -5E-10 UC1 = -6.1e-10 +U0 = 660 UTE = -1.6
+VOFF = -.13 DELTA = 0.01 PRT = 10
+RDSW = 175 PRWG = 0 PRWB = -0.0176 +ETA0 = 0 ETAB = -.1605 PCLM = 1.8804 +PDIBLC1 = 20 PDIBLC2 = 0 PDIBLCB = -0.05 +WR = 1 DWG = 0 DWB = 0 +B0 = 0 B1 = 10
+NDIODE = 1.00
+NTUN = 25 ISDIF = 2e-6 ISREC = 13 +ISTUN = 1e-5
+ISBJT = 4e-3 +XDIF = 1.15
+XBJT = 1.08 XREC = 0.95 XTUN = 0 +ALPHA0 = 1E-08 BETA0 = 0
+AGIDL = 0
+RTH0 = .01 CTH0 = 0
+CLC = 1e-7 CLE = 0.6 XPART = 0.0 +DWC = -0.0217e-6 DLC = 0.0120e-6
* Capacitancias intrinsecas do SOI
+CGSO = 0 CGDO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 0 +MJSWG = 0 PBSWG = 0 +TT = 0 CJSWG=0.7e-11 +KB1 = 0 CSDMIN = 0 *Parametros de Ruido +NOIMOD = 2 +EM = 4.1e7 AF = 1 +EF = 1 KF = 0
+NOIA=1E20 NOIB=5E4 NOIC=-1.4E-12
* p-MOSFET
.MODEL tipop PMOS +LEVEL=19
+MOBMOD=2 SHMOD=0 DDMOD=0
+TNOM= 27 TOX= 30e-9 TSI= 80e-9 TBOX = 390e-9
+VTH0= -0.4
+NCH= 6e16 NSUB=6e16 NGATE = 0
+RBODY = 0 RBSH = 0
+CDSC = 0 CDSCB = 0 CDSCD = 0
+CIT = 0 NFACTOR = 1 XJ = 5E-08 * Parametros para Tensao de Early
+VSAT = 1.6e5 PVAG = -100 LINT = 10E-7 WINT = 0.5e-9
+A0 = 1 AGS=0 A1=0
+A2 = 0.99 KETA = 3.2e-2
+K1 = .59 KT1 = -.28 KT1L = 8e-9 +KT2 = -.0646 K2 = 0 K3 = -3.5 +K3B = 0 W0 = 0
+NLX = 6.3E-8 DVT0 = 200 DVT1 = 3.72 +DVT2 = 0.19 DVT0W = 0 DVT1W = 0
+DVT2W = 0 DROUT = 3.617 DSUB = 0.56 +UA = 1.2e-8 UA1 = 3.37e-10 UB = 2.2e-18 +UB1 = -3.12e-18 UC = -5E-10 UC1 = -6.1e-10 +U0 = 330 UTE = -1.6
+VOFF = -.13 DELTA = 0.01 PRT = 10
+RDSW = 175 PRWG = 0 PRWB = -0.0176 +ETA0 = 0 ETAB = -.1605 PCLM = 1.8804 +PDIBLC1 = 20 PDIBLC2 = 0 PDIBLCB = -0.05 +WR = 1 DWG = 0 DWB = 0 +B0 = 0 B1 = 10
+NDIODE = 1.00
+NTUN = 25 ISDIF = 2e-6 ISREC = 13 +ISTUN = 1e-5
+ISBJT = 4e-3 +XDIF = 1.15
+XBJT = 1.08 XREC = 0.95 XTUN = 0 +ALPHA0 = 1E-08 BETA0 = 0
+AGIDL = 0
+RTH0 = .01 CTH0 = 0
+CLC = 1e-7 CLE = 0.6 XPART = 0.0 +DWC = -0.0217e-6 DLC = 0.0120e-6
* Capacitancias intrinsecas do SOI
+CGSO = 0 CGDO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 0 +MJSWG = 0 PBSWG = 0 +TT = 0 CJSWG=0.7e-11 +KB1 = 0 CSDMIN = 0 *Parametros de Ruido +NOIMOD = 2 +EM = 4.1e7 AF = 1 +EF = 1 KF = 0
+NOIA=9.9E18 NOIB=2.4E3 NOIC=1.4E-12 .CONTROL
OP SHOW ALL .ENDC
* .DC Vinneg 0 1 1 .AC DEC 40 1 1e10
*.noise V(15) Icc DEC 10 1 1e8 1 *.plot NOISE INOISE ONOISE *.print NOISE INOISE ONOISE .PRINT AC Vdb(15) VP(15) .PLOT AC Vdb(15) VP(15) *.extract phmrgn(v(15)) *.PRINT DC V(5) I(Vdd) * .PLOT DC V(5) I(Vdd) * .TRAN 10NS .2MS * .PRINT TRAN V(15) .END
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b) Simulação OTA GC SOI nMOSFET LLD/L=0.33 análise de ruído flicker
AMPLIFICADOR OPERACIONAL HF (L=3UM) UTILIZANDO SOI GC - LLD/L=0.33 Leff * BIAS VOLTAGE
VDD 1 0 4V
* DIFFERENTIAL MODE VOLTAGE VINNEG 11 0 DC 1 AC 1 VINPOS 18 0 DC 1
****** DIFFERENTIAL CIRCUIT * CURRENT SOURCE RESISTOR Icc 1 2 2.4mA
* CHARGE CAPACITOR CL 20 0 7P
* CURRENT SOURCE TRANSISTORS (W=600UM E L=3UM com LLD/L=0.33) - Leff
M09L 2 2 4 0 tiponl W=600E-6 L=1.5E-6
M09H 4 2 0 0 tiponh W=600E-6 L=3E-6
M10L 13 2 14 0 tiponl W=600E-6 L=1.5E-6
M10H 14 2 0 0 tiponh W=600E-6 L=3E-6
* ACTIVE CHARGE OF DIFFERENTIAL STAGE (W=300UM E L=3UM)
M03 8 8 1 0 tipop W=300E-6 L=3E-6
M04 15 15 1 0 tipop W=300E-6 L=3E-6
M05 5 8 1 0 tipop W=300E-6 L=3E-6
M06 19 15 1 0 tipop W=300E-6 L=3E-6
* ESPELHO DE CORRENTE DA CARGA ATIVA (W=200UM E L=5UM com LLD/L=0.33)- Leff = 3um
M07L 5 5 7 0 tiponl W=200E-6 L=2.5E-6
M07H 7 5 0 0 tiponh W=200E-6 L=5E-6
M08L 20 5 21 0 tiponl W=200E-6 L=2.5E-6
M08H 21 5 0 0 tiponh W=200E-6 L=5E-6
* DIFFERENTIAL PAIR (W=600UM E L=3UM com LLD/L=0.33)- Leff = 3um
M01L 8 11 10 0 tiponl W=600E-6 L=1.5E-6
M01H 10 11 12 0 tiponh W=600E-6 L=3E-6
M02L 15 18 17 0 tiponl W=600E-6 L=1.5E-6
M02H 17 18 12 0 tiponh W=600E-6 L=3E-6
****** FONTES DE TENSAO EM 0V (AMPERIMETRO) * V1 1 2 0 * V2 5 6 0 * V3 8 9 0 V4 12 13 0 * V5 15 16 0 V6 19 20 0 ****** TRANSISTORS MODELS * n-MOSFET
.MODEL tiponl NMOS +LEVEL=19
+MOBMOD=2 SHMOD=0 DDMOD=0
+TNOM= 27 TOX= 30e-9 TSI= 80e-9 TBOX = 390e-9
+VTH0= -0.4
+NCH= 1e15 NSUB=1e15 NGATE = 0
+RBODY = 0 RBSH = 0
+CDSC = 0 CDSCB = 0.004 CDSCD = 0.1
+CIT = 0 NFACTOR = 1 XJ = 5E-08 * Parametros para Tensao de Early
+VSAT = 1e4 PVAG=-25 LINT = 0.865E-9 WINT = 0.5e-9
+A2 = 0.99 KETA = 3.2e-2 +K1 = .59 KT1 = -.28 KT1L = 8e-9 +KT2 = -.0646 K2 = 0 K3 = -3.5 +K3B = 0 W0 = 0 +NLX = 6.3E-8 DVT0 = 200 DVT1 = 3.72 +DVT2 = 0.19 DVT0W = 0 DVT1W = 0 +DVT2W = 0 DROUT = 3.617 DSUB = 0.56
+UA = 1.2e-8 UA1 = 3.37e-10 UB = 2.2e-18 +UB1 = -3.12e-18 UC = -5E-10 UC1 = -6.1e-10 +U0 = 1200 UTE = -1.6
+VOFF = -.13 DELTA = 0.01 PRT = 10
+RDSW = 175 PRWG = 0 PRWB = -0.0176 +ETA0 = 0 ETAB = -.1605 PCLM = 1.8804 +PDIBLC1 = 20 PDIBLC2 = 0 PDIBLCB = -0.05 +WR = 1 DWG = 0 DWB = 0 +B0 = 0 B1 = 10
+NDIODE = 1.00
+NTUN = 25 ISDIF = 2e-6 ISREC = 13 +ISTUN = 1e-5
+ISBJT = 4e-3 +XDIF = 1.15
+XBJT = 1.08 XREC = 0.95 XTUN = 0 +ALPHA0 = 1E-08 BETA0 = 0
+AGIDL = 0
+RTH0 = .01 CTH0 = 1.46e-5
+CLC = 1e-7 CLE = 0.6 XPART = 0.0 +DWC = -0.0217e-6 DLC = 0.0120e-6
* Capacitancias intrinsecas do SOI
* Parametro CJSWG é importante para a análise AC
+CGSO = 0 CGDO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 0 +MJSWG = 0 PBSWG = 0 +TT = 0 CJSWG=0.7e-11 +KB1 = 0 CSDMIN = 0 *Parametros de Ruido +NOIMOD = 2 +EM = 4.1e7 AF = 1 +EF = 1 KF = 0
+NOIA=1E20 NOIB=5E4 NOIC=-1.4E-12 * n-MOSFET
.MODEL tiponh NMOS +LEVEL=19
+MOBMOD=2 SHMOD=0 DDMOD=0
+TNOM= 27 TOX= 30e-9 TSI= 80e-9 TBOX = 390e-9
+VTH0= 0.4
+NCH= 1e17 NSUB=1e17 NGATE = 0
+RBODY = 0 RBSH = 0
+CDSC = 0 CDSCB = 0.004 CDSCD = 0.1
+CIT = 0 NFACTOR = 1 XJ = 5E-08 * Parametros para Tensao de Early
+VSAT = 6e4 PVAG=-20 LINT = 0.865E-6 WINT = 0.5e-6
+A0 = 1 AGS=0 A1=0
+A2 = 0.99 KETA = 3.2e-2
+K1 = .59 KT1 = -.28 KT1L = 8e-9 +KT2 = -.0646 K2 = 0 K3 = -3.5 +K3B = 0 W0 = 0 +NLX = 6.3E-8 DVT0 = 200 DVT1 = 3.72 +DVT2 = 0.19 DVT0W = 0 DVT1W = 0 +DVT2W = 0 DROUT = 3.617 DSUB = 0.56
+UA = 1.2e-8 UA1 = 3.37e-10 UB = 2.2e-18 +UB1 = -3.12e-18 UC = -5E-10 UC1 = -6.1e-10
87
+U0 = 660 UTE = -1.6
+VOFF = -.13 DELTA = 0.01 PRT = 10
+RDSW = 175 PRWG = 0 PRWB = -0.0176 +ETA0 = 0 ETAB = -.1605 PCLM = 1.8804 +PDIBLC1 = 20 PDIBLC2 = 0 PDIBLCB = -0.05 +WR = 1 DWG = 0 DWB = 0 +B0 = 0 B1 = 10
+NDIODE = 1.00
+NTUN = 25 ISDIF = 2e-6 ISREC = 13 +ISTUN = 1e-5
+ISBJT = 4e-3 +XDIF = 1.15
+XBJT = 1.08 XREC = 0.95 XTUN = 0 +ALPHA0 = 1E-08 BETA0 = 0
+AGIDL = 0
+RTH0 = .01 CTH0 = 1.46e-5
+CLC = 1e-7 CLE = 0.6 XPART = 0.0 +DWC = -0.0217e-6 DLC = 0.0120e-6
* Capacitancias intrinsecas do SOI
* Parametro CJSWG é importante para a análise AC para que a curva fique sem deformações +CGSO = 0 CGDO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 0 +MJSWG = 0 PBSWG = 0 +TT = 0 CJSWG=0.7e-11 +KB1 = 0 CSDMIN = 0 *Parametros de Ruido +NOIMOD = 2 +EM = 4.1e7 AF = 1 +EF = 1 KF = 0
+NOIA=1E20 NOIB=5E4 NOIC=-1.4E-12 * p-MOSFET
.MODEL tipop PMOS +LEVEL=19
+MOBMOD=2 SHMOD=0 DDMOD=0
+TNOM= 27 TOX= 30e-9 TSI= 80e-9 TBOX = 390e-9
+VTH0= -0.4
+NCH= 6e16 NSUB=6e16 NGATE = 0
+RBODY = 0 RBSH = 0
+CDSC = 0 CDSCB = 0.004 CDSCD = 0.1
+CIT = 0 NFACTOR = 1 XJ = 5E-08 * Parametros para Tensao de Early
+VSAT = 1.6e5 PVAG = -100 LINT = 10E-7 WINT =
0.5e-9
+A0 = 1 AGS=0 A1=0
+A2 = 0.99 KETA = 3.2e-2
+K1 = .59 KT1 = -.28 KT1L = 8e-9 +KT2 = -.0646 K2 = 0 K3 = -3.5 +K3B = 0 W0 = 0 +NLX = 6.3E-8 DVT0 = 200 DVT1 = 3.72 +DVT2 = 0.19 DVT0W = 0 DVT1W = 0 +DVT2W = 0 DROUT = 3.617 DSUB = 0.56
+UA = 1.2e-8 UA1 = 3.37e-10 UB = 2.2e-18 +UB1 = -3.12e-18 UC = -5E-10 UC1 = -6.1e-10 +U0 = 330 UTE = -1.6
+VOFF = -.13 DELTA = 0.01 PRT = 10
+RDSW = 175 PRWG = 0 PRWB = -0.0176 +ETA0 = 0 ETAB = -.1605 PCLM = 1.8804 +PDIBLC1 = 20 PDIBLC2 = 0 PDIBLCB = -0.05 +WR = 1 DWG = 0 DWB = 0 +B0 = 0 B1 = 10
+NDIODE = 1.00
+NTUN = 25 ISDIF = 2e-6 ISREC = 13 +ISTUN = 1e-5
+ISBJT = 4e-3 +XDIF = 1.15
+XBJT = 1.08 XREC = 0.95 XTUN = 0 +ALPHA0 = 1E-08 BETA0 = 0
+AGIDL = 0
+RTH0 = .01 CTH0 = 0
+CLC = 1e-7 CLE = 0.6 XPART = 0.0 +DWC = -0.0217e-6 DLC = 0.0120e-6
* Capacitancias intrinsecas do SOI
* Parametro CJSWG é importante para a análise AC
+CGSO = 0 CGDO = 0 CGSL = 0 +CGDL = 0 CKAPPA = 0 +MJSWG = 0 PBSWG = 0 +TT = 0 CJSWG=0.7e-11 +KB1 = 0 CSDMIN = 0 *Parametros de Ruido +NOIMOD = 2 +EM = 4.1e7 AF = 1 +EF = 1 KF = 0
+NOIA=9.9E18 NOIB=2.4E3 NOIC=1.4E-12 .CONTROL OP SHOW ALL .ENDC *.DC VINNEG 0 1 1 *.PRINT DC I(VDD) *.PLOT DC V(5) I(VDD) * Analise AC
*.AC DEC 40 1 1E10 *.PRINT AC VDB(20) *.PLOT AC VDB(20) * Análise de ruido
.noise V(20) VINNEG DEC 10 1 1e8 1 .plot NOISE
.print NOISE .END
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Anexo B
Artigo apresentado no Congresso EUROSOI 2007 em Louvain – Bélgica para o Estudo de Ruído Flicker em OTAs Convencional e GC SOI nMOSFET.
Flicker Noise Analysis in CMOS OTA Using Fully
Depleted Graded-Channel SOI nMOSFET
Salvador Pinillos Gimenez1,2, Rogerio Laureano Gomes1 and Marcelo Antonio Pavanello1,2
1 Centro Universitário da FEI,
Av. Humberto de Alencar Castelo Branco, no 3972, 09850-901, São Bernardo do Campo, Brazil, sgimenez@fei.edu.br
2 Laboratório de Sistemas Integráveis,
Escola Politécnica da U. de São Paulo, Av. Prof. Luciano Gualberto, trav. 3, 158, 05508-900, São Paulo, Brazil
Abstract
This paper performs a flicker noise comparative study in CMOS OTAs implemented with conventional and Graded Channel (GC) SOI nMOSFETs based on SPICE simulations. Two design targets are taken into account fixing die area and transconductance to drain current ratio. It is verified that GC OTAs present similar flicker noise spectral density than those implemented with conventional one with the same effective channel length leading to an important die area reduction up to 27 % while keeping similar performance.
1. Introduction
The use of GC SOI nMOSFET in analog and RF applications is clearly established as reported in the literature [1]. In saturation, the effective channel length (Leff) can be approximated by the highy doped region
length (LHD) (Leff=LHD =L-LLD, LLD being the length of
lightly doped region) [1]. Reference [2] performed a comparative study between the high gain (HG) and high frequency (HF) single-stage OTAs implemented with conventional (conventional OTA) and GC SOI nMOSFETs (GC OTA), based in experimental results and SPICE simulations, concluding that OTAs implemented with GC SOI present improved open-loop voltage gain (AV0), without degrading the unity-gain
frequency (fT), phase margin (PM) and slew rate (SR),
with an expressive die area reduction, depending on the LLD/L ratio used. Reference [3] shows that input-
referred flicker noise spectral density (SVG) of GC SOI
with different LLD/L is higher than conventional SOI at
10 Hz, in saturation region, regarding fixed the mask channel length of 3 µm. The goal of this paper is to perform a comparative study between CMOS OTAs implemented with conventional and GC SOI nMOSFETs in order to verify the flicker (1/f) noise. The base for comparison bas been the OTA design developed in reference [4] for conventional SOI transistor, whereas only the nMOSFET devices are replaced by GC SOI with LLD/L ratio equal to 0.33. Two
different design targets (DT) are taken in account, the first one with similar die area (DTI) and the second with fixed gm/IDS (DTII). Both DT have same power
dissipation, by fixing the differential pair drain current (IDS). In DTI, the die area is maintained constant by
fixing the mask channel length (L) of conventional and GC SOI nMOSFETs. In this situation the gm/IDS is
different because the conventional SOI Leff are higher
than GC SOI nMOSFET (LHD). In DT II, gm/IDS is fixed
by GC SOI nMOSFETs channel length (LHD) increase,
in order to reach the same conventional SOI nMOSFET Leff, resulting GC OTA with larger die area.
2. SPICE BSIM3SOI Models Calibration
Table 1 presents the dimensions (W/L), in micrometers, of each transistor used in the implementation of conventional and GC OTAs, used to perform the SPICE BSIM3SOI v. 3.1 [5] flicker noise (1/f) comparison study.
Table I: W/L ratios of transistor used in conventional and GC
OTAs for DT I an II.
HF OTA 1 2 3 4 LLD/L - 0.33 0.33 0.33 M1-M2 600/3 600/3 600/4.5 400/4.5 M3-M4 300/6 300/6 300/6 300/6 M5-M6 300/6 300/6 300/6 300/6 M7-M8 200/5 200/5 200/7.5 134/7.5 M9-M10 600/3 600/3 600/4.5 400/4.5
Note: The shaded cells regard GC SOI nMOSFETs W/L ratios As proposed in ref. [6], the series association of two conventional SOI nMOSFETs is used to represent the GC SOI nMOSFET. Each conventional SOI nMOSFET represents one channel part, with its respective channel length (LLD and L-LLD) and threshold voltage (VtL and
VtH). These calibrations are performed by adjust of the
SPICE parameters in order to reproduce the same experimental results of the OTAs DC bias and the frequency response [open-loop voltage gain (AV0) and
phase as a function of the frequency (f)] as presented in figure 1. A good agreement between SPICE simulated and experimental results has been obtained.
For the noise simulation the parameters of BSIM3SOI unified flicker (1/f) noise model (NOIMOD=2) [5] of conventional and GC SOI were adjusted based on experimental results of ref. [3] (Table II). The comparison has been made for devices with L=3 µm. Performing the flicker noise analysis for conventional and GC SOI nMOSFETs with LLD/L=0.33 (Leff=2 µm),
10 Hz, biased in saturation region (IDS=10 mA,
VGS=0.6V and VDS ≈ 1 V), in agreeement with the
experimental results of ref. [3]. The flicker noise model [5] available in BSIM3SOI expresses the flicker noise spectral density as inversely proportional to effective channel length square. Following the results of table II one can see that the influence of Leff dominates the
cause of higher 1/f noise for GC SOI with LLD/L in the
order of 0.33 as the noise increases by a factor of 2.3 whereas the 1/Leff2 increases by a factor of 2.2. As
demonstrated in ref. [3], the dominating noise mechanism changes from the mobility-fluctuations (∆µ model) in conventional SOI to carrier-flutuations (∆n model) in GC SOI mainly with larger LLD/L values.
100 101 1 02 1 03 104 105 106 107 108 109 0 5 10 15 20 25 30 35 40 45 0 50 100 150 200 250 300 350 Ph a s e ( o ) frequency (H z) AV (d B )
High Frequency OTA
Experim enta l Res ults C onve ntional LL D/L =0.3 3 SP IC E S im u latio ns
C onve ntional LL D/L =0.3 3
Fig. 1: SPICE Calibration: Operation point and frequency reponse (Av and Phase x f)
Table II: SPICE flicker noise model calibration: Input-refered
Noise Spectral density (V2/Hz) – 10 Hz.
V2/Hz Experimental SPICE Simulation
Conv. SOI 1.15x10-11 1.13x10-11
GC SOI – LLD/L=0.33 2.65x10-11 2.68x10-11
On the other hand, similar comparison between 1/f noise of GC SOI with LLD/L=0.33 and conventional
SOI, both with the same Leff, shows practically the same
results in the range of 1-10KHz with differences smaller than 1% in dB.
3. OTAs Flicker (1/f) Noise Analysis
The OTAs flicker (1/f) noise analyses are performed for both DT, for the first time, in order to quantify and compare the flicker (1/f) noise behavior in OTAs, by using conventional and GC SOI nMOSFETs. Figure 2 presents the input-referred and output noise spectral density (S) curves as a function of the frequency for conventional and GC OTAs with LLD/L=0.33
considering both DTs. Analysing fig. 2, one can observe that the GC OTA of DT I presents higher flicker noise than the conventional OTA. The input-referred noise at 10 Hz changes from -1.48x 10-10 V2/Hz for conventional
OTA to -2.94x 10-10 V2/Hz for GC OTA. As already
mentioned this can be linked to the smaller Leff in GC
SOI of DT I.On the other hand, the GC OTA of DT II (similar Leff) presents practically the output-referred
noise behavior than conventional one (maximum difference of 1.5% in dB). As the GC OTA open-loop voltage gain is larger than conventional OTA its input-
refered noise spectral density (S) is smaller (≈1% in dB) than for conventional OTA (output noise spectral density/AV0). The main disadvantage of using the GC
SOI nMOSFET in DT II is the higher area than the conventional SOI nMOSFET. In order to overcome this issue, it is possible to reduce channel width up to approximately 33% for LLD/L=0.33 to compensate the L
increase and reach similar AV0, moving the transistors to
operate deeper in strong inversion regime (smaller gm/IDS) at similar bias current and consequently
reducing the GC OTA AV0. The impact of W reduction
on DT II results are also presented in figure 2.
100 101 102 103 104 105 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 O n pu t- re fe rr ed N oi se S pec tr al D ens ity [V 2 /H z] Conventional OTA DT I: L=3µm GC LLD/L=0.33 DT II Leff=3µm GC LLD/L=0.33 GC LLD/L=0.33 - W reduced 33% Frequency [Hz] In pu t- re fe rr ed N oi se S pec tr al D ens ity [V 2/H z]
Fig. 2: Sxf of conventional and GC OTA for both DTI and
DTII, also regarding reduced W.
The DT II design with reduced W presents similar input and output-referred noise levels than the conventional OTA as well as power dissipation, AV0 and phase
margin. However, the reduction on W in this range can represent a die area improvement up to 27 %.
4. Conclusions
Flicker noise analysis in CMOS OTAs implemented with GC SOI nMOSFETs has been performed based on SPICE simulations calibrated by experimental results. The use of GC SOI with similar mask channel length improves the voltage gain but worsens the OTA noise response due to the effective channel length reduction in GC SOI. Increasing the mask channel length in GC SOI to obtain similar effective channel length improves the noise level while preserving the larger voltage gain in GC OTA with the penalty of larger die area. Fixing the voltage gain, the effective channel length and the noise performance on conventional and GC OTA the channel width of GC SOI can be decreased up to 33 %, which represents a die are reduction around 27 %.
References
[1] M A Pavanello et al, Solid-State El., v 44, 1219 (2000). [2] S P Gimenez et al, Microelectronics J., v 37, 31 (2006).
[3] E. Simoen at al, 2nd EUROSOI 2006, 105 (2006).
[4] J-P Erggermont et al, IEEE J. of Solid-State Circuits, v 31, 179 (1996).
[5] P. Su at al, MOSFET Model of California, version 3.1, Berkley, (2003).
[6] M A Pavanello et al, Proc. of ICCDCS on Devices, D030-
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