Sinais de transação da interface escrava

Definição dos sinais de resposta de transação enviados ao barramento por um escravo.

enum Bus_HRESP_Type{ OKAY = 0, ERR, RETRY, SPLIT }

[1] ARM. AMBA Specification rev. 2.0, IHI-0011A, May 1999. 2

[2] AXYS Design Automation Inc. MaxSim developer suite user’s guide ver 5.0, March 2004. 3.3.1

[3] R. AZEVEDO, S. RIGO, M. BARTHOLOMEU, G. ARAUJO, C. ARAUJO, and E. BAR- ROS. The ArchC architecture description language and tools. Int. J. Parallel Program., 33(5):453–484, 2005. 1,4.1

[4] F. BALARIN, M. CHIODO, H. HSIEH, A. JURESKA, L. L. C. PASSERONE, A. SANGIOVANNI-VINCENTELLI, E. SENTOVICH, K. SUZUKI, and B. TABBARA. Hardware-software co-design of embedded system: The polis approach. In Norwell, MA: Kluwer, 1997. 3.4.1

[5] L. BENINI and G. D. MICHELI. Powering networks on chips. In Proceedings of the Int. Symp. Syst. Level Synthesis, pages 33–38, 2001. 1.1

[6] D. C. BLACK and J. DONOVAN. SystemC: From the Groung Up. In Kluwer Academic Publishers., 2004. 1,2.4

[7] J. BUCK, S. HA, E. A. LEE, and D. D. MASSERCHMITT. Ptolemy: A framework for simulating and prototyping heterogeneous systems. In Int. J. Comput. Simul., pages 155–182, 1994. 3.4.1

[8] CADENCE and COWARE. Convergensc / incisive design flow. white paper. rev. 2. dis- ponível em: http://www.cadence.com. 1

[9] Y.-S. CHO, E.-J. CHOI, and K.-R. CHO. Modeling and analysis of the system bus la- tency on the SoC platform. In Proceedings of the international workshop on System-level interconnect prediction, pages 67–74, 2006. 1.1,3.3,3.3.1

[10] J. CONNELL and B. JOHNSON. Early Hardware/Software Integration Using SystemC 2.0. Disponível em: http://www.synopsys.com. 2002. 5.1,5.1

[11] J. DAVEAU, T. B. ISMAIL, and A. A. JERRAYA. Synthesis of system-level communi- cation by an allocation based approach. In Proceedings of the Int. Symp. System Level Synthesis, pages 150–155, September 1995. 3.3

[12] S. DEY and S. BOMMU. Performance analysis of a system of communication proces- ses. In Proceedings of the Int. Conf. Computer-Aided Design, pages 590–597, November 1997. 3.3

[13] F. DUMITRASCU, I. BACIVAROV, L. PIERALISI, M. BONACIU, and A. A. JER- RAYA. Flexible MPSoC Platform with Fast Interconnect Exploration for Optimal System Performance for a Specific Application. In Proceedings of the conference on Design, au- tomation and test in Europe (DATE), 2006. 3.2

[14] R. DÖMER, A. GERSTLAUER, and D. GAJSKI. Specc methodology for high-level modeling. In 9th IEEE/DATC Electronic Design Processes Workshop, 2002.1

[15] ECLIPSE. Eclipse open source community. disponível em: http://www.eclipse.org. 1

[16] H. EL-REWINI and M. ABD-EL-BARR. Advanced computer architecture and parallel processing. In John Wiley & Sons, Inc., 2005.1.1

[17] M. GASTEIER and M.GLESNER. Bus-based communication synthesis on system level. In ACMTrans. Design Automation Electronic Systems, pages 1–11, January 1999.3.3

[18] F. E. GUIBALY. Design and analysis of arbitration protocols. In IEEE Transactions on Computers, pages 161–171, 1989. 1.1

[19] M. R. GUTHAUS, J. S. RINGENBERG, D. ERNST, T. M. AUSTIN, T. MUDGE, and R. B. BROWN. Mibench: A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization, 2001. 5.1

[20] E. R. HAROLD. Xml bible. wiley, 2001.1

[21] A. HAVERINEN, M. LECLERCQ, N. WEYRICH, and D. WINGARD. SystemC based SoC Communication Modeling for the OCP Protocol. Techical Report, 2002. 4.2.1

[22] J. HENKEL. Closing the SoC Design Gap. In NEC Laboratories, Princeton, 2003.1

[23] R. HO, K. W. MAI, and M. A. HOROWITZ. The future of wires. In Proceedings of the IEEE, vol. 89, pages 490–504, April 2001. 1.1

[24] A. A. JERRAYA. Long term trends for embedded system design. In Proceedings of the CEPA 2 Workshop - Digital Platforms for Defence, pages 15–16, 2005. 1

[25] A. A. JERRAYA and W. WOLF. Multiprocessor systems-on-chips. In Morgan Kaufmann, September 2004. 1,1.1,3.1

[26] K. KEUTZER. System-level design: Orthogonalization of concerns and platform- ba- sed design. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000. 1

[27] S. KIM, C. IM, and S. HA. Schedule-aware performance estimation of communication architecture for efficient design space exploration. In Proceedings of the Intl. Conf. on Hardware/Software Codesign and System Synthesis, pages 195–200, 2003. 3.3,3.4.2

[28] S. KIM, C. IM, and S. HA. Efficient exploration of on-chip bus architectures and me- mory allocation. In Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 248–253, 2004. 3.4,3.4.2

[29] P. KNUDSEN and J. MADSEN. Integrating communication protocol selection with par- titioning in hardware/software codesign. In Proceedings of the Int. Symp. System Level Synthesis, pages 111–116, December 1998. 3.3

[30] K. LAHIRI and A. RAGHUNATHAN. Power analysis of system-level on-chip commu- nication architectures. In Proceedings of the Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 236–241, September 2004. 1.1

[31] K. LAHIRI, A. RAGHUNATHAN, and S. DEY. Efficient exploration of the SoC commu- nication architecture design space. In Proceedings of the Intl. Conf. on Computer Aided Design, pages 424–430, 2000. 1.1,3.1,3.4.2

[32] K. LAHIRI, A. RAGHUNATHAN, and S. DEY. System-level performance analysis for designing on-chip communication architectures. In IEEE Trans. on Computer-Aided De- sign of Integrated Circuits and Systems, pages 768–783, June 2001. 3.1,3.4,3.4.1

[33] C. LEE, M. POTKONJAK, and W. H. MANGIONE-SMITH. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In MICRO-30: Research Triangle Park, 1997. 5.1

[34] P. LIEVERSE, P. V. D. WOLF, and E. DEPRETTERE. A trace transformation technique for communication refinement. In Proceedings of the Conference on Hardware/Software Codesign and System Synthesis (CODES), 2001. 3.4

[35] D. L. LIU and C. SVENSSON. Power consumption estimation in CMOS VLSI chips. In IEEE Journal SSC, pages 1531–1549, 1994. 1.1

[36] M. LOGHI, F. ANGIOLINI, D. BERTOZZI, L. BENINI, and R. ZAFALON. Analyzing On-Chip Communication in a MPSoC Environment. In Proceedings of the conference on Design, automation and test in Europe (DATE)., 2004. 3.2,3.2.2,4.5

[37] G. MADL, S. PASRICHA, Q. ZHU, L. A. D. BATHEN, and N. DUTT. Formal perfor- mance evaluation of amba-based system-on-chip designs. In Proceedings of the 6th ACM and IEEE International Conference on Embedded Software, pages 22–25, 2006. 3.3.2

[38] G. MARTIN and H. CHANG. Winning the SoC Revolution: Experiences in Real Design. In Kluwer Academic Publishers, 2003. 1

[40] L. NULL and J. LOBUR. The Essencials of Computer Organization and Architecture. In Jones and Bartlett Publishers, 2003. 1.1,2.1,2.1,2.1

[41] O. OGAWA, S. B. NOYER, P. CHAUVET, K. SHINOHARA, Y. WATANABE, H. NI- IZUMA, T. SASAKI, and Y. TAKAI. A practical approach for bus architecture optimi- zation at transaction level. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2003. 3.2,3.2.1,3.2.3

[42] S. PASRICHA. Transaction Level Modeling of SoC with SystemC 2.0. In Synopsys User Group Conference (SNUG), 2002. 3.2.3

[43] S. PASRICHA, N. DUTT, and M. BEN-ROMDHANE. Using TLM for Exploring Bus- based SoC Communication Architectures. In International Conference on Application- specific Systems, Architectures and Processors (IEEE ASAP 2005), July 2005. 1.1, 2.5,

3.2,3.2.3,3.2.3,4.1

[44] S. I. G. PCI. PCI Local Bus Specification, Production Version. Rev. 2.1. disponível em: http://www.pcisig.com/specifications/conventional/, June 1995. 2.1

[45] PDESIGNER. PDesigner Framework. Disponível em: http://www.pdesigner.org. 2006.

1

[46] S. PRATA. C++ primer plus. 5th edition. sams. 2004.1

[47] V. RAGHUNATHAN, M. B. SRIVASTAVA, and R. K. GUPTA. A survey of techniques for energy-efficient on-chip communication. In Proceedings of the Design Automation Conf. (DAC), pages 900–905, 2003. 1.1

[48] H. ROCHA. SCExamine: Um mecanismo para introspecção de sistemas em SystemC. Dissertação de Mestrado - CIn/UFPE. 2006. 1

[49] J. A. ROWSON and A. SANGIOVANNI-VINCENTELLI. Interface based design. In Proceedings of the Design Automation Conference (DAC), pages 178–183, June 1997.

3.2

[50] RTEMS. Getting started with rtems Ed. 4.6.6, October 2003.3.2.2

[51] A. SANGIOVANNI-VINCENTELLI. Defining platform-based design. In EDesign of EETimes, 2002. 1

[52] A. SANGIOVANNI-VINCENTELLI, M. LAJOLO, A. RAGHUNATHAN, S. DEY, and L. LAVAGNO. A case study on modeling shared memory access effects during per- formance analysis of hw/sw systems. In Proceedings of the International Workshop on Hardware/Software Codesign (codes/CASHE), March 1998. 1.1

[53] T. SHANLEY and D. ANDERSON. EISA System Architecture, 2nd. ed. In Addison- Wesley Publishing Comp., 1995. 2.1

[54] C. SHIN, Y.-T. KIM, E.-Y. CHUNG, K.-M. CHOI, J.-T. KONG, and S.-K. EO. Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC design. In Proceedings of the conference on Design, automation and test in Europe (DATE), 2004.

3.2

[55] SPIRIT. Spirit consortium. http://www.spiritconsortium.org. 1

[56] D. SYLVESTER and K. KEUTZER. A global wiring paradigm for deep submicron de- sign. In IEEE Trans. Computer-Aided Design, pages 242–252, February 2000. 1.1

[57] F. VAHID and T. GIVARGIS. Embedded System Design: A Unified Hardware/Software Introduction. In John Wiley & Sons, Inc., 2002. 1.1,2.1

[58] P. VIANA. A methodology to explore memory hierarchy architectures for embedded systems. In Informatics Center/UFPE - PhD Thesis, August 2006.3.1

[59] VSIA. Virtual Component Interface Standard, Version 2 (OCB 2 2.0), April 2001. 2.1

[60] A. WIEFERINK, T. KOGEL, R. LEUPERS, G. ASCHEID, H. MEYR, G. BRAUN, and A. NOHL. A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms. In Proceedings of the Int. Conf. on Design, Automation and Test in Europe (DATE), February 2004. 3.1

[61] T. WILD, A. HEKERSDORF, and R. OHLENDORF. Performance evaluation for system- on-chip architectures using trace-based transaction level simulation. In Proceedings of the conference on Design, automation and test in Europe (DATE), pages 248–253, 2006. 3.4

[62] T. WILLIAMS and C. KELLEY. Gnuplot: An Interactive Plotting Program, Version 4.0. disponível em: http://www.gnuplot.info/docs/gnuplot.html, April 2004. 4.6

[63] J. XU, W. WOLF, J. HENKEL, and S. CHAKRADHAR. A methodology for design, mo- deling, and analysis of networks-on-chip. In IEEE International Symposium on Circuits and Systems ISCAS., pages 1778–1781, 2005. 1.1

[64] T. YEN and W. WOLF. Communication synthesis for distributed embedded systems. In Proceedings of the Int. Conf. Computer-Aided Design, pages 288–294, November 1995.