Chapter 4 Testbed
5.3 Prototype Implementation
PTP RTC PTP Engine BBU
Xilinx Virtex-7 FPGA
Tx/Rx Buffer IQ Frame Packer/
Unpacker
DMA
Ethernet MAC
RFS Controller
FH
RRU FMCOMMS2 Xilinx Virtex-7 FPGA
Interface Buffers Frame IQ
Packer/
Unpacker
AD9361
PTP Engine Ethernet
MAC
RFS Controller FH
PPS RTC
PTP RTC PPS RTC
ADC/DAC
Figure 5.4:Simplified block diagrams illustrating the BBU and RRU FPGA design.
This estimator assumes the worst-case realization of mini{x[i, j]}, which is when x[i, j] re- mains constant at its maximum specified value of+γ throughout the observation.
Nevertheless, on RRUs that use the same RTC for timestamping and RFS triggering, whereγ =, note that (5.11) reduces to:
ˆ
αul[j] = (j−1)(νf h+νipg) + 2+ max
i {d˜ul[i, j]}. (5.12) Finally, similar to (5.4), one can adopt a sub-optimal global time advance estimate:
ˆ
αul = max
1≤j≤J{αˆul[j]}. (5.13)
this block has to wait until the RFS controller asserts its time-advanced trigger before releasing the packets downstream. Once asserted, the trigger grants permission for transmitting a block ofnb IQ samples over the FH, over as many FH packets as necessary to convey them all. At this point, the BBU starts to transmit the packets in serving iterations, as illustrated in Fig. 5.2.
Meanwhile, at the RRU, the Frame Unpacker block continuously extracts IQ samples from the incoming FH packets. However, these samples are not immediately made available to the DAC for on-air transmission. Instead, they are only provided to the DAC when the RFS controller determines so. On every interval Tr, the RRU’s RFS controller will feednb/na IQ samples to the DAC for each of its AxCs.
In addition to IQ samples, the Frame Packer block adds relevant metadata to each FH packet that it generates. More specifically, it includes the packet’s departure timestamp4 and a sequence number. The timestamp allows the receive-end to measure the frame’s E2E delay.
The sequence number, in turn, enables verification of frame sequence integrity on tests.
Fig. 5.4 also shows the PTP and PPS RTCs available in the hardware, as discussed in Section 4.4. These RTCs can be flexibly routed to the hardware blocks based on SW config- urations. For example, it is possible to select which RTC provides time to the RFS controller (determining the RFS trigger) and which one provides time for the frame packer (determining the FH packet timestamps). This feature allows the evaluation of the RFS scheme under both PTP and PPS synchronization, as well as flexibility for the source of FH packet timestamps.
Lastly, an essential element of the implementation concerns the RRU interface buffers shown in Fig. 5.4 and detailed in Fig. 5.5. They consist of two layers of first-in first-out (FIFO) buffering between theFrame Unpacker(in DL direction) and the DAC. The first buffering stage stores samples that arrive from the FH and maintains these samples until an RFS trigger. After a trigger, the RFS controller authorizes the transport of samples from the first stage to the second.
The second stage, in turn, provides the CDC from the internal clock domain (on its write-side) to the external DAC’s clock domain (on its read-side). This dual-buffer circuit repeats for each I and Q component of each AxC since the DAC reads these components through parallel lanes.
Thus, e.g., for 2 AxCs, there are four circuits.
One motivation for this approach is simplicity in terms of CDC. Since the RFS controller regulates the path between the two FIFOs, it can operate entirely within the internal clock
4Unlike the PTP timestamps discussed in Section 4.3, the FH packet timestamps are taken at a high hardware level (above the MAC layer) instead of close to the physical medium.
1st Stage Buffer
De-jitter/
CDC Buffer RFS
Controller From
FH
To DAC
Internal Clock Domain DAC Clock Domain
Figure 5.5:Dual-buffer scheme used for RFS control in the RRU.
domain (see Fig. 5.5), while only the second-stage buffer crosses clock domains. More impor- tantly, this scheme facilitates dealing with problems that originate from fluctuations in the RFS trigger, as discussed in the sequel.
5.3.2 Solutions for Trigger Fluctuations
In the proposed mechanism, the BBU and the RRUs periodically assert trigger signals based on their local RTCs. However, since their RTCs are continuously time-disciplined, the interval between consecutive triggers can oscillate and deviate from the nominal intervalTr. Ad- ditionally, on the BBU end, when the time advance is continuously adapted, the time-advanced trigger fluctuates accordingly. Such fluctuations can create two disturbing scenarios: when the interval between consecutive triggers is significantly lower than the nominal interval Tr and the opposite scenario, when significantly higher thanTr. More specifically, the problem occurs when the fluctuation exceeds the sample periodTs= 1/fs.
The rationale is that the RFS controller regulates the samples transmitted per interval Tr. After a trigger, it ensures that onlynb samples cross between the FIFO stages in Fig. 5.5.
However, when the interval between triggers fluctuates by more thanTs, the nb samples may fail to traverse the FIFO stages on time or, in the other extreme, finish prematurely.
One way to avoid this condition is to adopt smooth RTC time corrections, i.e., corrections that do not exceed Ts in the course of any trigger interval Tr. This solution depends on the adopted clock disciplining algorithm and on the stability of the time offset estimates. If this smoothness is not guaranteed, other remedies may be applied, as discussed next.
When an RRU experiences a shorter trigger interval, the specific problem is that it may fail to complete the RF transmission of its sub-block of samples spanning intervalTr. In this case, when a new trigger comes, any remaining sample of the previous block can be deemed as delayed. To ensure that the RF transmission timing can be realigned among RRUs on every
trigger, an RRU must be capable of discarding such delayed samples.
The implemented RRU prototype detects and discards delayed samples by counting the samples that traverse the path between the two buffers of Fig. 5.5. Furthermore, it maintains the CDC (second-stage) buffer with its minimum possible occupancy. This strategy ensures that all the other samples are held at the first-stage FIFOs so that the RFS controller can drop them.
A similar problem of delayed samples can arise on the BBU due to short trigger intervals.
When the BBU increases its time advance, the new (more time-advanced) trigger can come before the BBU finishes transmitting the past data block. In this scenario, the BBU may either drop the delayed data while starting the new block immediately or burst the delayed data such that it catches up without data loss. The current version of the BBU prototype discussed in this work does not feature such a catch-up mechanism and, hence, this issue is out of scope.
The opposite problem is when an RRU experiences a longer interval between consecutive triggers, in which case the CDC buffers can underflow while waiting for the new trigger. One solution is to allow a small number of extra samples (in addition tonb/na samples per AxC) to traverse from first-stage buffers to CDC buffers during initialization. This way, if a trigger eventually comes too late, there is some backup of samples to avoid underflow. This strategy can be acceptable as long as all RRUs back up the same number of samples. Nevertheless, since the backup samples remain in the CDC buffers, they are not amenable to dropping, as the RFS controller can only drop samples traversing from the first to the second stage buffers. Hence, the backup samples can disturb the re-synchronization performance.
In this work, the CDC underflows are accepted instead of deliberately treated. The expec- tation is that the resulting gap on RF transmissions due to CDC underflows remains negligible for timing alignment. This issue is explored in Chapter 6.