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Ultra Low Power Capless Low-Dropout Voltage Regulator

(Master Thesis Extended Abstract)

Jo˜ao Justo Pereira

Department of Electrical and Computer Engineering

Instituto Superior T´ecnico - Technical University of Lisbon, Portugal Email: joao.miguel.pereira@ist.utl.pt

Abstract—Modern power management System-on-a-Chip (SoC) design demands for fully integrated solutions in order to decrease certain costly features such as the total chip area and the power consumption while maintaining or increasing the fast transient response to signal variations. Low-Dropout (LDO) voltage regulators, as power management devices, must comply with these recent technological and industrial trends.

An ultra low power cap-less low-dropout voltage regulator with resistive feedback network and a new dynamic biased, multi- loop compensation strategy is proposed. Its dynamic close-loop bandwidth gain and dynamic damping enhance the fast load and line LDO transient responses. These are assured by the output class-AB stage of the error amplifier and the feedback loop of the non-linear derivative current amplifier of the LDO.

The proposed LDO, designed for a maximum output current of 50 mA in TSMC 65 nm, requires a quiescent current of 3.7 µA and presents excellent line and load transients (<10%) and fast transient response.

Index Terms—low drop-out, ldo, low power, capless, dynamic biased, multiloop feedback.

I. INTRODUCTION

The consumer electronic industry has been undergoing severe pressures to adapt and to respond to new social and market demands. In addition, the rapid development of semi- conductor manufacturing process and its respective miniatur- ization continues to exert severe pressures to the industry.

Power Management, as an essential research area and as part of the solution, is rapidly changing in order to meet these rigorous demands [1].

SoC solutions bring the possibility to the electronic industry to integrate the same complete system onto a single IC. It aims mainly to achieve a more compact and robust system while speeding up the manufacturing process with even lower costs of production for the same technology [2]. Each internal block, integrated onto a single IC system, requires a clean regulated low-noise and precise voltage supply [3] in order to provide increased processing power and functionality for a longer period of time [4].

Low-Dropout (LDO) voltage regulators are usually em- ployed in voltage regulation due to their ability to regulate with a very small input-output differential voltage [5]. This advantage makes them the optimal solution for voltage regu-

lation in SoC applications where noise-sensitive circuitry exist and where current efficiency matters.

A. Motivation

High-performance ultra low power LDOs are part of the response to the emerging need of efficient and robust elec- tronic components. Concerning LDOs, many researchers are proposing different topologies with different compensation techniques. However, these techniques and analyses assume the small signal analyses and framework when, in fact, most of the transient voltage signals in the nonlinear pass device of the LDOs are not small [6].

B. Objectives

The objective of this thesis is to develop an ultra low power capacitor-less LDO voltage regulator capable of maintaining a steady operation under rigorous and uncertain loading con- ditions.

The LDO design is implemented in TSMC 65 nm CMOS technology. The software used to implement and design the proposed LDO was Cadence Virtuoso Custom IC Design, Hspice simulator, WaveView and CosmoScope waveform viewers.

C. Outline

The present paper is organized as follows: Section II:

The conventional LDO regulator characterization is presented.

The capacitor-less LDO regulators as an improvement of the former is also introduced. Section III: A theoretical macro- model of the design is given as starting point and a basic characterization of the proposed LDO is also provided. Section IV: The design simulation analysis are provided, explaining the results achieved. A comparison between this work and state of the art is also given. Section V: The layout of the proposed topology is given. Section VI: This section summarizes all the work done and all the options taken into account.

II. LDO VOLTAGEREGULATOR

The main blocks of the conventional LDO topology are the error amplifier, the pass device and the linear feedback network. The conventional LDO topology is presented in Figure 1. To operate, the LDO also needs a voltage reference.

Band Gap V_in

Error Amplifier

V R

R 1

2 div

PMOS Pass Device

Vout

Resr Cout

Low-Dropout Voltage Regulator

Off-Chip Capacitor

Fig. 1. Conventional LDO topology

The error amplifier is responsible for the voltage com- parison between the reference, set by a Band Gap, and the scaled down output voltage obtained by the resistive feedback network. It is also responsible for driving the pass device in function of the comparison result just stated.

The pass device is a power device whose only function is to control the amount of current flow to the load. Typically, while driving, a pass device supplies currents from 100 A to 100 mA as shown in Tsz Yin Man study [7].

Finally, a large capacitor exists at the LDO output in parallel to the load. This large capacitor, in conventional LDO topologies, acts like a charge source during fast load transients improving the response time of the regulator and its stability [8], [9], [10]. However, as referred earlier, this capacitor poses a problem due to the fact that it is too large to be an on-chip capacitor.

A. Pass Device

G. Rincn-Mora and P. Allen published a comparative study between LDO voltage regulators with different pass devices [11] where the advantages and disadvantages of each pass device were identified and its study deepened. This study results, together with contributions of other researchers [12], identified what is known and accepted today as the most suitable pass device for LDO application, the PMOS device.

B. Efficiency

Conventional LDOs perform reasonably well and are usually preferred to other types of voltage regulation because, among others, their applied voltages are low, which translates to low consumed, low dissipated power and therefore higher power efficiency, equation 1.

η= PO

PI

×100% = Vout

Vin

Iload

Iload+Iquiescent

×100% (1) Since V_out andI_load are well defined for each application, the only parameters left that can improve the LDO efficiency areVinandIquiescent. The efficiency is greatly improved when the quiescent power is reduced. Moreover, as introduced ear- lier, lower dropout voltages will permit lower input voltages, Vin, which, by examination of equation 1, will further improve the overall LDO efficiency.

C. Stability

Stability is one key aspect concerning LDO differentiation.

All the elements present in Figure 1 and their intrinsic charac- teristics are crucial for defining the LDO stability. As a result, stability is therefore, one of the most important trade-offs of LDOs.

The transfer function of the system is obtained from the abstraction model shown in Figure 2 where the feedback loop was broken for the purpose of the stability analysis.

The open-loop gain of the model shown is extracted as

Cgd

r_o C_gs V_od

r_op Co V_out -g

g

V_ref

+- -

m mp

Fig. 2. Conventional LDO abstraction model

shown in equation 2.

The minimal requirements that need to be true for the LDO to be stable are: the zero must be located below the unity gain frequency and all high-frequency poles must be located at least three times higher than the unity gain frequency [13], [14].

The zero and poles are given by equations 3 and 4 respec- tively.

Z= g_mp Cgd

(3)

P1' −_(C ¹

o+C_gd)r_op+(C_gs+C_gd)r_o+C_gd r_o r_op g_mp

P2' −_C ^gmp

o (C_gs+C_gd)

(4)

Figure 3 represents the frequency response of the conven- tional LDO in accordance with the mathematical model shown.

The dominant pole, the lower frequency pole, in conven-

Fig. 3. Conventional LDO frequency response

tional LDOs is set at the output of the LDO by the large capacitor. This capacitor exists in order to compensate the high output impedance of the LDO, providing a stronger and

Vout

Vref

=

g_mp g_mr_o r_op h

1−s ^C_g^gd

mp

i

s²

C_gdC_gs+ (C_gd+C_gs)C_o

r_or_op+s

r_o(C_gd+C_gs) +r_op(C_gd+C_o) +C_gdg_mpr_or_op + 1

(2)

a more reliable instantaneous source of current improving the LDO transient response. The non-dominant pole is defined by the pass device characteristics, namely at its gate terminal, and finally the zero which is defined by the pass device’s transconductance and gate drain capacitance. Furthermore, if a buffer is used between the error amplifier and the pass device a third high frequency pole will appear increasing the negative slope by a 20 dB per decade from its position forward, as shown in Rincn-Mora stability analysis [15].

Overall, low-dropout voltage regulators justify their pres- ence in SoC due to their chip size, fast transient responses, low-noise advantages, power efficiency and adjustable param- eters.

D. Capacitor-less LDO Voltage Regulators

Capacitor-less LDOs, are an alternative to the conventional LDO voltage regulator that aim to circumvent some of the non-desirable characteristics of the latter voltage regulator.

Removing the large capacitor from the conventional LDO and replacing it by a smaller one in the range of ten to hundreds of picofarad [16], easily implemented on-chip, a more suitable LDO is achieved according to modern design trends. On the other hand, removing the large capacitor leads to other constraints of the LDO responses and performance.

With the aforementioned replacement, some output filtering properties are lost.

III. CAPACITOR-LESSLDO DESIGN

A. Design Considerations and Principles

Recent studies regarding compensated capacitor-less LDOs have achieved incredible and promising experimental results.

The state of the art compensation topologies typically follow one of two strategies: (1) Active feedback compensation strategy [17], [18], [19], [20], [21] and (2) adaptive and dynamic adaptive biasing [22], [16], [23]. The first strategy aims to achieve higher loop responses by increasing the damping characteristics of the system. Miller pole-splitting compensation is also used in this strategy to provide the required stabilization. The second strategy aims to overcome the slew-rate limitations imposed by the error amplifier by embedding a class-AB amplifier inside the error amplifier or by embedding a buffer connected to the gate of the pass device as a push-pull stage [24], [4]. Both strategies also aim to improve the cap-less LDO transient response by sensing the output voltage through the derivative loop. The non-linear derivative loop will speed up the current amplification and therefore the transient response of the LDO.

Aiming to boost dynamically the bias current of the circuit and the slew-rate of the error amplifier, researchers have

recently proposed a hybrid strategy. The core technique behind the hybrid strategy is achieved by sensing and mirroring a current from the fast output voltage dependent derivative loop [7], [10].

The compensation of the ultra low power capacitor-less low- dropout voltage regulator in this work proposed consists on a new multi-loop feedback strategy with internal node sensing also based on both the above mentioned strategies.

The error amplifier used in the proposed topology is com- posed by two gain loops with a folded cascode amplifier [25]

and a symmetrical OTA with PMOS common-gate differential inputs instead of the usual common-source differential inputs.

B. Macro-model of the Capacitor-less LDO Regulator 1) Basic Characterization: The study of the present work began based on the macro-model shown in Figure 4. It represents the integral parts of the cap-less LDO as well as the pass device parasitic capacitors, gate-source and gate-drain capacitors, C_gs andC_gd respectively.

The error amplifier output current, i_G, is shown in equa- V_in

PMOS M

V_out C_out

V_Ref

V_OD P

C_gs

C_gd G i_G

I_out O

C_f i_f

Current amplifier

i_f’

Dynamic biasing interaction

i_D gm

Fig. 4. Basic components of the proposed capacitor-less LDO

tion 5 in accordance to the model presented and neglecting the channel modulation effects. In 5, g˜m represents the dy- namic transconductance of the model whileC˜f represents the dynamic active Miller capacitance.

iG = ˜gm vod+ ˜Cf dvout

dt = X

i=0 j=0

aij|vod|ⁱ

dvout

dt

j vod+

+ X

i=0 j=0

bij|vod|ⁱ

dvout

dt

jdvout

dt (5) To consider a wider and more generalist analysis where the operating point of the circuit is changed and the non-linear effects of the elements are taken into account, large signal analyses, this model admits these last parameters to be non-negative coefficient polynomial functions of |vod| and

dvout

dt

and where their first order coefficients, a00 and b00

are the conventional transconductance g_m and active Miller capacitanceC_f [10].

2) AC Analysis: To obtain the AC response of the model, a small signal analysis is required. From Figure 4 and know- ing that the continuity current condition at the pass device terminals needs to be respected, i_g and i_d can be extracted and considering that the pass device is operating deep in the saturation region and V_in and I_out are constant. By transcribing i_g and i_d to the complex domain, normalizing it and solving it to v_out, the close loop gain of the model can thus be achieved, 6.

Avc=^v_v^out

ref = ^ω2n

s²+

ω_n Q ^s+ω

2n

=

g_mpg_m C⁰out Cg s²+



 s

gmp C⁰²_gd gm C⁰out Cg

s gmp gm

C⁰out Cg



^s+

gmp gm

C⁰out Cg

(6)

where C⁰gd is the the effective Miller capacitance, Cg is the error amplifier capacitance and C⁰out is the pass device output capacitance, given respectively by C⁰gd =Cf+Cgd, Cg=Cgs+Cgd and finallyC⁰out =Cout+Cgd andωn and ς are the undamped natural frequency and the damping ratio respectively given by equations 7 and 8 respectively.

ωn = r gmp

C⁰_out gm

C_g (7)

ς = 1 2 Q =1

2 s

gmp

gm

C⁰²_gd C⁰out Cg

(8) One can observe that equation 6 is in fact the normalized transfer function of a bi-quadratic low-pass filter, as its denom- inator is a second order characteristic polynomial and therefore it will assume two poles. These two poles will be located at sp1 = −ωp1 = −^ω_ςⁿ and sp2 = −ωp2 = −ς ωn as long as ς = _2Q¹ 1 holds true, being Q the quality factor of the model.

Applying the previous analysis to the Figure 4, where g_m emulates a two-stage Miller OTA, the Bode magnitude response of the model is obtained.

The dashed line represents the open loop gain Bode response while the full dash represents the closed loop gain. To obtain the open loop gain the feedback loop was broken atXin Figure 4 thus cutting theVout dependency. In the closed loop gain Bode response,ωp1 assumes the value of gain bandwidth frequency, ωGBW, while ωp2 assumes the value of the high frequency pole,ωnd. On the other hand, in the open loop gain Bode response, the ωp1 assumes the value of the dominant pole, ωd, whileωp2 maintains the previous value ofωnd. The undamped natural frequency, ωn, can also be given by the geometric mean

ωn = √

ωGBW ωnd

of ωGBW and ωnd.

Fig. 5. Capacitor-less LDO closed loop gain Bode magnitude response

Similarly, the quality factor of the system,Q, can also be given by the square root of those frequencies

Q=q_ω

GBW

ωnd

. The gain bandwidth frequency and non-dominant pole frequency relate to the model parameters by the following equations, ωGBW =_C^g0^m

gd andωnd= _C^g0^mp out

C⁰_gd C_g .

The proposed topology uses a Miller pole-splitting compen- sation technique to stabilize itself. The stabilization is achieved by spreading the gain bandwidth pole and the non-dominant pole apart. The damping ratio,ς, is ultimately responsible for the poles location sp1 = −^ω_ςⁿ, sp2 = −ς ωn

and for that reason has a key role in the pole-splitting compensation due to its linear dependence ofCf.

3) PSR Analysis: In order to obtain the response of the system in the frequency domain one first needs to find its transfer function. Respecting the KCL at the pass device terminals, now in the model shown in Figure 6, namely at

V

g v

V

C

C

C

V

O

mp gs

gm

Fig. 6. Capacitor-less LDO small signal model for PSR analysis

theOnode, the linear small signal analysis imposes that:







gmvout=Cgd

d v−vout

dt +Cgs

d v−vin

dt

gmp v−vin

=Cout dv_out

dt +Cgd

d v−vout

dt

(9)

where the pass device is assumed to be operating deep in the saturation region.

The transfer function of the system given by 10, whereCg=

Cgs+Cgd, is then extracted from 9 by solving the system to v_out.

vout

v_in =

ωn

Q s s²+ωn

Q s+ω_n²

=

g_mp C_gd Cg Cout

s s²+s gmpCgd

C_g C_out+ gm gmp

C_g C_out (10) The above transfer function presents one zero and two poles.

The undamped natural frequency, ωn, and damping factor maintain their previous values and therefore the two existing poles obtained from the denominator of the transfer function s_p1 = −ωp1 = −^ω_ξⁿ and s_p2 = −ωp2 = −ξ ωn are still located approximately atω_GBW andω_nd. The zero is located at 0 Hz (s= 0condition).

Figure 7 represents the response of the PSR analysis. The bandwidth of the filter, represented by bin the PSR response, is defined as the frequencies between ωL andωU that are the lower and upper passband cutoff edges respectively.

Fig. 7. Capacitor-less LDO PSR response

4) Linear Transient Analysis: Figure 4 is the basic topology used to obtain the transfer function considering that the feedback loop is closed and that vref is constant, then the vout behavior will be given by:

d² vOD

dt² + 2 ς ωn

d vOD

dt +ω²_n vOD = 0 (11) In order to observe howvout changes to variations iniload, the analysis imposes a step in the load current with well defined amplitude of Iout = −Cout d vout

dt . The progress of vOD is then provided by:

v_OD =− Iload

ω_d C_out e^{− ς ωn t} sinω_d t (12) whereω_dis the damped frequency given byω_d=ω_n√

1−ς². 5) Global Transient Analysis: Starting with the linear tran- sient response of the proposed model, equation 11, applying a second order approximation of the gate current to the system, as shown in equation 5, and normalizing it both in voltage and in time, a more generalized equation is achieved 13.

In 13, the output voltage and time normalization were applied through the following change of variables v_ON = ^v_V^OD

Ov and τ = ωn t, being vON is the normalized output voltage and VO_v is the pass device overdrive gate-source voltage. In 13,

˜

ωN andς˜are the normalized undamped natural frequency and dynamic damping ratio respectively. K1 relates to the non- linear damping force, b01 of 5, K2 to the non-linear effects of the dynamic biasing over the damping feedback loop,b₁₀ of 5,K₃to the restoring force,a₁₀of 5, and finallyK₄to the dynamic biasing of the error amplifier by the derivative loop, a₀₁ of 5.

A study [6] was performed to illustrate the numerical solu- tions of 13, where the Krylov-Bogolyubov averaging method was applied to the equation at cause to obtain its asymptotic solutions. The study pinpointed that the averaging method employed shows that the average dynamical damping and the average undamping natural frequency increase linearly with the signal oscillation amplitudes.

6) Derivative Amplifier: Inside the derivative amplifier a small circuit like the one shown in Figure 8 exists. It enables the cap-less LDO active compensation.

The idea behind the topology present in Figure 8 is to

V _B

V _Y V _X

I

C

i

i

1:k

i

+ -

v _C

M ₁ M ₂

Fig. 8. Basic current derivative amplifier topology

provide a certain amount of current to its pending blocks when, and only when, it is needed, not supplying current otherwise.

The supplied current is proportional to the sensed output voltage variations thus enabling a faster derivative amplifier stabilization and therefore a faster LDO regulation.

Both M₁ and M₂ NMOS transistors should operate in the saturation region in order to act like controlled current sources to obtain the expected result of gm2 =k gm1 and therefore if =k(iB+iC).

To illustrate how sensitive the derivative output sensing block is to swings in the output of the cap-less LDO, a large signal analysis is given, providing that ∆iC ∆IB except

d² v_ON

dτ² + 2ς+k₁

d v_ON dτ

+k₂|vON|d v_ON

dτ + 1 +k₃|vON|+k₄

d v_ON dτ

v_ON = 0

⇐⇒ ^d2_dτ^vON2 + 2 ˜ς ^{d v}_dτ^ON + ˜ωN vON = 0

(13)

in the initial condition,t0, where iD=iB:







∆v_X= ∆v_C+ ∆q_i

D

β

∼= ∆v_C+_g^Cf

m1

d v_C dt

t=t₀+∆t

i_f =k(i_B+i_C) =k(i_B+C_f ^{d v}_dt^C)

(14) The system of equations 14 shows that by dynamically increasing the biasing current and assuming that the variations on the capacitor are much wider than the ones felt over the biasing current, iB, the derivative amplification range proves to be true even for large signal variations where the high pass pole is dynamically shifted to higher frequencies.

Figure 9 shows the basic topology of the non-linear current amplification used in the feedback damping loop.

When the overdrive voltage is positive, the error amplifier

V

M M

M M

M M

R R

5 6

1 2

3 4

1 2

X

gate

Y

Z

i

i

i

Fig. 9. Basic topology of a non-linear current amplifier

will produce the dominant current, i1, greater than i2, thus biasing M1 stronger and limiting M2, being entirely turned off as a limit case. The opposite will occur for negative overdrive voltages. To the case where, the overdrive voltage is zero, or close to zero, the produced currents i₁ andi₂ will have a small quiescent current contribution thus keeping M₁ andM₂ limited.

As the transistors M₁ and M₂ are more or less biased, the current will flow through the resistive path and through one of the transistors to ground. The amount of current that passes through the transistors and resistors is set by the overdrive voltage and is given by iD = icommon mode

and iR = ⁱdif f erential mode

2 respectively, where i common mode= ⁱ¹⁺ⁱ₂ ² andidif f erential mode=i1−i2[26].

From Figure 9, through the current mirrors the output current is obtained iGF = iD3 − iD4. This current is responsible for charging parasitic capacitors of the pass device and thus responsible for its reaction time to the drive

command.

7) Architecture with the proposed dynamic biased derivative amplifier: The proposed cap-less LDO voltage regulator is finally presented in Figure 10. It is composed by a PMOS pass device,MP D, an error amplifier that integrates two gain loops with a folded cascode amplifier [25], a symmetrical OTA with common-gate differential inputs, two identical voltage buffers (only one represented) and finally a fast dynamic loop.

Transistors M₁ −M₆ implement the two common-gate differential inputs of the symmetrical OTA. M₈ − M₉ implement the main current mirror of the amplifier and M₁₀ − M₁₁ are simple cascode transistors. The M₇ transistor assures the biasing current to the differential input transistors (M₁, M₂, M₅ and M₆) through M₃ and M₄ being iD7 = 200 nA. The core of the symmetrical OTA is composed by the transistors M14 −M17 plus R3 and R4

resistors. These implement the non-linear mirror explained earlier and enables the class-AB operation of the amplifier as the dynamic biasing for the output sensing block.

The current derivative amplifier (fast dynamic loop) is composed by transistors M18 − M29 and by resistors R5 − R6. The dynamic biasing of the high pass filters employed is achieved through transistors M20 and M21. As to its operation, for an overshoot in V_out one can verify that the conductance of M₁₉ is increased and the conductance in M₂₈ is decreased thus adjusting the response of the LDO.

Similarly, for an undershoot in V_out one can verify the opposite. The transistor M_cas serves to decouple the V_out node from swings in Vin typical in line transient analysis.

M28, M29 and the resistors R5 and R6 compose one other non-linear mirror in the output derivative sensing block to enhance its current amplification. Finally M23 and M25 are the output stage of the current derivative amplifier.

The represented voltage buffer implemented by transistors M30−M38serves mainly to isolate the input from the output and to supply enough current to its pending block, note that the input is done by the gate of the transistor M36.

Regarding R1 and R2, responsible for scaling down the output voltage, along with the output voltage buffer and its proper adjustment, different LDO output voltages can be achieved. This enables a comfortable degree of design customization serving a wider range of cap-less LDO applications.

Finally, Table I summarizes the design parameters values for the sub-threshold operation.

The design transistor sizes are defined having the size of the biasing transistors as reference. The biasing transistors size is given by ^W_L

B where their drain current, iD_B, is set

Vref Vin

Vout

M

M M M M

M

M M

M M M

M M

M M

M M

M M

M M M M

M M

M M

M

M C

C

R R

R R

M

1

2 3 4 5

6

7 Vbias1 Vbias2

8 9

12 13

10 11

3 4

5 6

1

2

22 23

18

20 28 29 21

24 25

26 27 19

14 15

16 17

PD

C_out

Error Amplifier Fast Dynamic Loop Buffer

M₃₀ M₃₁ M₃₂ M₃₃

Vbias1

M₃₄ M₃₅

M₃₆ M₃₇

M₃₈

R₁

R₂ M_cas

Fig. 10. Circuit schematic of the proposed cap-less LDO voltage regulator

TABLE I

DESIGN PARAMETER VALUES

VT_N ∼0.41 V

VT_P ∼0.61 V

R3, R4 : R5,R6 500kΩ : 1MΩ

C1, C2 2pF

M1−M6 : M7 : M8, M10, M12, M13 : M9, M11 : M14−17

1 : 2 : 1 : 10 : 1 ^W_L

B

M20, M21 : M18, M19, M22−24, M26−29 : M23, M25&Mcas

1 : 5 : 10 : 16 ^W_L

B

M30 : M31, M32, M34−38 : M33 6 : 1 : 2 ^W_L

B

to100 nA.

IV. RESULTS

In order to fully characterize the proposed cap-less LDO, the results of the performed simulations are presented. All simulations were executed for the minimum dropout voltage across the pass device of 200 mV, V_in = 1.4 V regulating to V_out = 1.2 V. It is assumed that the capacitance seen by the output node of the LDO forward is 100 pF. It includes the power line distribution capacitances as well as parasitics capacitances. Nevertheless, the proposed LDO is stable for all output capacitances up to 1 nF as it will be shown later.

The design passes all P-V-T corners and P-M Monte Carlo simulations showing a good compromise between its trade-offs.

A. Open loop GBW Simulations

Figure 11 shows the AC response of the design where the open loop gain, bandwidth and phase margin can be drawn to both light and heavy load conditions, Iout = 100 uAand Iout= 50mA respectively.

One can observe that, for the worst case scenario, the open loop gain, bandwidth and phase margin are always greater

(deg)

−600.0

−400.0

−200.0 0.0

(dBV)

−100.0 0.0 100.0

f(Hz)

1.0 10.0 100.0 1.0k 10.0k 100.0k 1meg 10meg 100meg 1g

(deg) : f(Hz) Phase(Vout)

Phase(Vout) (dBV) : f(Hz) dB(Vout)

dB(Vout) Iload = 50 mA

Iload = 100 uA

Iload = 50 mA

Iload = 100 uA

Fig. 11. Open loop frequency response of the proposed capless LDO under light and heavy load conditions

than60dB,370 kHzand66^◦ respectively.

B. PSR Simulations

The behavior of the proposed capless LDO to ripples in the power supply node is presented in Figure 12.

C. Line and Load Regulation Simulations

The input output voltage relationship presented in Figure 13 defines the line and load regulation of the presented voltage regulator. In fact, Figure 13 only represents the line regulation for both light and heavy load conditions of the capless LDO, 100 µAand50mA respectively.

However, in Figure 13, one can observe that the line regu- lation to light and heavy load conditions are not superimposed and therefore load regulation exists.

Applying a linear regression to the signals present in Figure 13, two linear slopes are obtained. The slope of the 100 µA load condition reveals a0.85mV /V line regulation to the light load condition while the slope of the 50 mA load condition reveals a 0.69 mV /V line regulation to the heavy load condition. The load regulation, on the other hand,

(dBV)

−70.0

−60.0

−50.0

−40.0

−30.0

−20.0

−10.0 0.0 10.0

f(Hz)

1.0 10.0 100.0 1.0k 10.0k 100.0k 1meg 10meg 100meg 1g

(dBV) : f(Hz) dB(Vout)

dB(Vout)

Iload = 100 uA

Iload = 50 mA

Fig. 12. Power supply rejection of the proposed capless LDO under light and heavy load conditions

is obtained by the difference felt in the output voltage for both light and heavy load conditions, measured as 3.02 mV /mA for the minimum dropout voltage.

Vin(V)

1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3

(V)

1.195 1.196 1.197 1.198 1.199 1.2

1.201 (V) : Vin(V)

Vout

Vout

Iload = 100 uA

Iload = 50 mA

Fig. 13. Line and load regulation response of the proposed capless LDO

D. Line, Load Transient and Output Voltage Ripple Simula- tions

Figure 14 presents the capless LDO load transient response of the proposed capless LDO. The simulation was performed to the minimum dropout voltage where the output current quickly (rise/f all_time = 500 ns) varied from 100 µA to 50mA and back again to100µA. Additionally, a simulation was performed to obtain the load transient response of the LDO without the proposed fast dynamic loop (derivative loop).

As expected, the output voltage suffered from an undershoot to the 100 µA−50 mA output current transition, and an overshoot to the 50mA−100 µAoutput current transition.

The settling time is approximately 625 ns for the output voltage undershoot case (measured when the output voltage is within ±10% of the regulation value) and approximately 1.16µsfor the output voltage overshoot case.

The line transient response of the LDO is presented in Figure 15. In this simulation the input voltage was quickly

changed from the minimum dropout (Vin = 1.4 V) to V_in = 1.9 V and then changed back again to the minimum dropout voltage for a constant output current of 50 mA. As before, an extra simulation was performed to show the impact of the fast dynamic loop in the proposed LDO.

The output voltage of the LDO recovers to ±10% of its

(A)

0.0 10.0m 20.0m 30.0m 40.0m 50.0m 60.0m

t(s)

0.0 2.5u 5u 7.5u 10u 12.5u 15u 17.5u 20u

(V)

0.0 0.25 0.5 0.75 1.0 1.25 1.5

(V)

0.9 1.0 1.1 1.2 1.3 1.4 1.5

(A) : t(s) Iload (V) : t(s) Vout (V) : t(s) Vout

Vout w/o Current Derivative Amplifier

Fig. 14. Load transient response of the proposed capless LDO

(V)

1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0

(V)

0.8 1.0 1.2 1.4 1.6

t(s)

0.0 2.5u 5u 7.5u 10u 12.5u 15u 17.5u 20u 22.5u 25u 27.5u

(V)

1.1 1.2 1.3 1.4

(V) : t(s) Vin (V) : t(s) Vout (V) : t(s) Vout

Vout w/o Current Derivative Amplifier

Fig. 15. Line transient response of the proposed capless LDO

final value within approximately0.7µsfor both overshoot and undershoot cases when the fast dynamic loop is employed.

A 169 mV output voltage overshoot is achieved for the 1.4V −1.9 V input transition while a98mV output voltage undershoot is achieved for the1.9V−1.4V input transition.

E. Comparison with previously reported works

In order to introduce the proposed work in the research contextual frame, a FOM has been adopted [27] (given by equation 15) and equally applied to this and other previously reported works.

F OM =C_out ∆V_out I_Q I_load²

max

(15) Cout is the estimated on-chip load capacitance, ∆Vout is the highest voltage spike detected for transient variations,IQis the quiescent current and finally,Iload_maxis the maximum output

TABLE II

PERFORMANCE SUMMARY AND COMPARISON WITH RECENTLY REPORTED WORKS

[28] [10] [27] [24] [7] [3] [29] [30] This work

Technology (µm) 0.35 0.35 0.09 0.35 0.35 0.35 0.11 0.35 0.065

I_load (mA) 100 50 100 100 50 100 200 100 50 V_DO (mV) 150 200 300 200 200 200 200 200 200

V_out (V) 2.35 2.8 0.9 1 1 1.6 2.25 2.8 1.2

C_out (pF) 100 0-100 600 100 >20 100 5000 1000000 100

I_Q (mA) 0.007 0.065 6 0.1 0.095 0.02 0.046 0.189 0.0037

∆Vout (mV) 236 <90 90 <50 <70 <98 1200 3 198 Tsettle (µs) ∼0.15 ∼15 N/A ∼30 ∼0.3 <9 0.067 ∼0.03 ∼1.16 F OM (f s) 16.5 234 32000 50 266 19.4 6900 17700 29

current that the voltage regulator is able to supply. A lower FOM implies a better overall performance. For this work the FOM obtained was 29f s.

Table II summarizes the individual characteristics and trade- offs of each work. It also presents an individual FOM for each reported work thus enabling better and fair comparison between works.

The FOM comparison given above strongly highlights the importance of the proposed improvements and trade-offs.

From equation 15, one can observe that lower FOMs are achieved when the output capacitance, the maximum output voltage variation and quiescent current are small, the smaller the better, while suppling large output currents. However, as previously showed, these parameters are related to each other in non-linear ways so imposed compromises are always present due to the nature of topology and its internal compo- nents.

The proposed topology can also be easily adapted to meet other specifications, concerning the output voltage, due to its resistive voltage divider. This feature allows this topology to be reused in different SoCs, or several times in the same SoC with different voltage regulations if required, thus saving design time.

The proposed capless LDO is suitable for practical im- plementation, presents low quiescent current as well as an excellent FOM and excellent line and load transient responses.

V. LAYOUT

The layout of a design, in this case of an LDO, represents the final product, represents all the simulations, all the efforts made and the real costs of fabrication. Therefore, it has to be robust to all simulations and it should be, ideally, small in area and in layers required. Special care needs to be paid to some issues in order to maintain the design performance.

Good layout techniques imply better protection of transis- tors against unavoidable mismatching issues during the fabri- cation process, imply improved techniques against switching and gradient issues across the design area. Current density over the layout area is also a very important concern. The use of dummy components is also very important to protect the actual components. Metal paths need to be designed accordingly with

their maximum tolerable current. By the use of several contact pins between two layers (i.e. Poly and Metal1) the routing resistance can be minimized and so the voltage drop [31]. This technique was extensively used in the pass device terminals. To enable interoperability and to avoid shorts circuits with other nearby blocks, odd metal layers have vertical displacement while even metal layers have horizontal displacement. To save resources this design uses only to the first two layers of metal.

A. Ultra low power LDO voltage regulator Layout

The inputs of the error amplifier have crucial importance in the LDO performance and so the offset voltage between each input transistor needs to be reduced. Some techniques exist to minimize the offset voltage between matched components, where the inter-digital and common-centroid techniques [31]

are the most employed. In this layout inter-digital techniques were preferred. Furthermore, guard rings were also used around each matched input pair in order to prevent changes from switching and thermal gradient effects.

In fact, large components such as the pass device and the 1 MΩ resistors were also broken several times to improve component yield and allow the use of guard rings to decrease the negative effects of their operation. An extra guard ring was employed around each large component to achieve further protection. Guard rings were also used in every sensitive area, inside the control core.

The capacitors of the derivative amplifier were implemented by MOScap transistors thus saving analog core area.

To further improve the proposed layout, ESD circuitry could be applied to each I/O pad in order to save the pass device and the control core from electrostatic discharges. For SoC integration, only the pads that need to be tapped from the outside of the chip need this type of circuitry.

VI. CONCLUSION

The design of an ultra low power capless LDO voltage regulator was the main objective of this work. Its specifications were defined having the State of the Art in consideration. Sev- eral topologies were studied and its improvements analyzed in order to add some insight and positive contribution to the present work. The multiloop strategy and dynamic biasing

Fig. 16. Layout of the proposed capless LDO

of the derivative amplifier proved to be the better choice.

Miller compensation was also included as well as the push- pull strategy.

In the end, a new capless LDO topology was successfully implemented based on a new theoretical macromodel. The above compensations and strategies led to significant gains in the overall LDO response. This fact is corroborated by the simulated results showed earlier that, for low quiescent currents, are said to be excellent overall results. The design output voltage undershoots and overshoots, in line and load transients, are excellent and their settling time minimal.

The performance comparison of the proposed LDO with the other previously reported works, through the adopted FOM, clearly showed the relevance of the proposed solution and the benefits of the compromises made. It also showed that the proposed capless LDO voltage regulator is a viable solution for SoC integration.

The proposed capless LDO voltage regulator was developed in TSMC^R 65 nm CMOS technology at INESC-ID^c, Lisbon, Portugal.

A. Achievements

The proposed capless LDO, with the fast derivative ampli- fier, achieved a maximum voltage spike of198 mV when the load current was changed from light to heavy load conditions (worst case scenario) in only 500 ns. Moreover, when Vin

changed from1.4V to1.9V, and back again to1.4V, the ob- tained output voltage variation was always inferior to170mV (worst case scenario). The power efficiency(η) obtained was around 85.7 %while the current efficiency(η_I) obtained was 99.9 %. Finally, while presenting excellent results for a3.7µA quiescent current, the proposed topology proved to be stable under all load conditions.

Table III summarizes the final results obtained with the proposed topology.

In addition, the author of this thesis co-authored a research

TABLE III

SUMMARY OF THE CAPLESSLDOVOLTAGE REGULATOR SIMULATION RESULTS

PARAMETER SYMBOL MIN TYP MAX UNITS

Technology - TSMC^R 65 nm

Core Area - 0.19 mm²

O. J. Temperature Tj -40 25 125 C

Supply Voltage Vi 1.35 1.4 3.3 V

Output Voltage Vo 1.07 1.2 1.4 V

Load Current Io 0 - 50 mA

Int. Capacitor Cout - - 100 pF

Line Regulation ∆Vo/∆Vi 0.69 - 0.85 mV/V

Line Transient ∆Vo V i−pk - - 169 mV

Load Regulation ∆Vo/∆Io - 3.02 - mV/mA

Load Transient ∆Vo Io−pk - - 198 mV

Ripple Rejection PSR -45 -25 -10 dB

Gain Bandwidth GBW 364 370 967 kHz

Phase Margin P M 43 66 69 ^◦

Startup Time Ts - - 6 µs

Res. Variation - 24.6 - 25.5 %

Cap. Variation - 19.8 - 22.7 %

CURRENT CONSUMPTION

All blocks ON IQ_ON - - 3.7 µA

All blocks OFF I_{QOF F} - - 27 pA

paper along with M. S. Jorge Esteves, Ph. D. Jlio Paisana and Ph. D. Marcelino Santos. The paper was submitted to Microelectronics Journal with the name of ”Ultra Low Power Capless LDO with Dynamic Biasing of Derivative Feedback”[6].

B. Future Work

As modern power management trends keep evolving, stronger and stronger forces are felt over the electronic design industry. As a result, improvements to the State of the Art topologies are always a question of time. The proposed concept represents a contribution to the State of the Art for capless LDO voltage regulators. However, concerning the proposed topology, much can still be done to complement this contribution and increase its performance. A few aspects of this work were not fully improved due to the different possible combinations of trade-offs and the limited time available. To mention a few:

• The derivative amplifier current driving capability could be improved allowing a faster source current and current sinking capability from the voltage regulator output node.

• In addition to the derivative amplifier, several clipping circuits exit and can be applied to the regulator, ensuring a much thinner output voltage variation range. As before, the compromise of quiescent current, output voltage and analog core area needs to be considered.

• The PSR response of the voltage regulator can be adjusted and further improved by increasing the impedance from

Vin toVout and decreasing the impedance from Vout to ground [32].

• In order to save the battery life, the reference of the capless LDO can be supplied by itself. It can only happen after the start up time and respective transient oscillations.

This option will add complexity to the circuit as it will have an extra loop with a control circuit, more analog area, more quiescent current, but will allow the power down of the Band Gap reference circuitry, so careful attention should be paid on this subject.

• As the lithographic processes are improved, the length of the transistors decrease allowing better results and perfor- mances. Porting the current design to better technologies will also lead to better results.

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