Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation

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Low-Voltage Low-Power CMOS Analogue Circuits for Gaussian and Uniform Noise Generation

G. Evans'.'. J. Goes','. A . Steiger-Gar@o'.', M D. Ortigueira"', N. Paulino',2 a n d J

Sousa

Lopes3

I UNINOVA - CRI Campus da FCT/UNL 2825 ^-I14 Caparica ^-PORTUGAL

Faculdade de CiBncias e Tecnologia Campus da FCTI"3L 2825 ^-I 14 Caparica ^-PORTUGAL

'

Department of Physics

Faculdade de Ciencias da Universidade de Lisboa Edificio C8, Campo Grande, 1749-016 - Lisboa E-mail: gevans(Z!fc.ul.~t E-mail: @,uninova.ut PORTUGAL. E-mail: gevans@fc.ul.pt Abstract

-

^ACMOS analogue circuit for Gaussian noise generu-

tion as well as a novel circuitfor transforming Gaussian noise into uniform noise, hoth.designed/or operating with a supply voltoge o/

I . S K arepresented. Both circuits are optimizedfor U 0 . 3 5 ~ stan- dord CMOS technology using an equation-based design methodol- ogy based on generic algorithms. Electrical simulations demon- strate that high noise amplinrdes together with reasonable hond- widths can be achieved with relatively low power dissipation. Po- tential applications include self-calihrution and on-chip self-testing of video-rate analogue-to-digital converters.

1. INTRODUCTION

A wide variety of applications require noise sources as building blocks namely, in electronic testing and measure- ment, communication systems and cryptography [ I]. Digital circuits can be employed to create pseudorandom numeric sequences but, for very stringent requirements such as data encryptation, pseudorandom noise is often inadequate [2].

Discrete implementations usually lead to larger power dissi- pations and die areas since a digital-to-analogue converter .and an anti-imaging low-pass filter are required to provide an analogue continuous-time output. Noise generators can be used for digital self-calibration of analogue-to-digital converters (ADCs) [3] and, since these generators have a uniform power spectral density, they are probably the best stimulus for on-chip full-speed characterization of video-rate ADCs through histogram tests [4].

This paper presents a CMOS analogue circuit for Gaussian noise generation as well as a new circuit for transforming Gaussian noise into uniform noise both operating with a single supply-voltage of 1.W. The Gaussian noise generator (GNG) is based in a fully-differential high-gain inverting configuration. The amplifier (opamp) used employs a three- stage topology comprising a folded-input stage followed by two differential common-source stages with offset cancellation of the first and second stages. Different realizations of GNGs based deterministic chaotic circuits have also been reported and can be found in [ I I]. However, a full descrip- tion of such technique as well as a comparison between it and the one used in this work is out of the scope of this paper. The specifications for the GNG require high closed-loop gain, a bandwidth of 10 MHz, an output swing of 0.8 V and an output-referred rms noise of, at least, two hundreds of mili-Volts. As shown in section 4 of this paper, this can be achieved by means of a powerhl circuit optimizer based on

genetic algorithms. The uniform noise generation can be then generated using a new low-voltage (LV) analogue circuit that transforms Gaussian noise into Uniform noise using two non-correlated GNG circuits. Finally, simulated results are presented and discussed.

2. LOW-VOLTAGE LOW-POWER CMOS GAUSSIAN NOISE GENERATOR (GNG)

A ) Circuit Principles and Topology

The GNG generator can be realized by a continuous-time or discrete-time implementation. Two possible circuits, corresponding to each case are shown in Fig. I (a) and (b), respectively. In this paper, for simplicity reasons, only the continuous-time version of GNG is described. However, the design of the switched-capacitor (SC) version is straightfor- ward. The continuous-time GNG shown in Fig. 1 (a), works by amplifying the thermal noise produced by large input resistors using a low voltage opamp in a high-gain closed- loop configuration. This method was reported in [2] but for the case of a GNG circuit supplied with 5V. Resistors R3 are used to generate wideband thermal noise in the form of kTIC,, , where k is Boltzmann's constant, T is absolute temperature and C;, represents the equivalent input capaci- tance of the opamp. The second source of input-referred thermal noise is the opamp itself which should be designed to have input transistors with very low transconductance, gm,, quite-large excess noise factor, y, and it should be op- timized in order to maximize the bandwidth (A/), the output- referred noise, V,,(rms), and the open-loop dc gain, A .

0-7803-7761-31031f17.00 02003 IEEE 1-145

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v''"(r"= RI +(RI R I + R 2 + R Z ) / A

.jlc.i,cn-

^I ⁽¹⁾ vices). The equivalent bandwidth of the opamp, AJ is approximately given by:

where & ( f ) represents the input-referred spectral noise A 1 (5) Af 3 - - .

density of the opamp. A schematic of the LV opamp is de- picted in Fig. 2. The circuit comprises a folded-input stage followed by two differential common-source stages with input offset cancellation. For the sake of simplicity, the out-

2 a ' ( T n , n + r n c m + r n F o / d +rnout2 +rno!dt3)

where G represents the closed-loop gain and 5.;".

r,,,,

5 m C n M , rHn,,,,, rn,,,,3 , are the time-constants associated

devices with large gate area. The undesirable effect of high lif noise because of using PMOS input devices with very low transconductance in the first stage is significantly at- tenuated by the high-pass response of the second and third stages due to the offset cancellation method employed. The poles of the LPFs can be placed at a frequency where the residual lifnoise is negligible. Note that for the previously referred applications in ADCs, the noise does not necessarily have to be white over the entire bandwidth as long as it re- mains Gaussian.

7

F i g . 2 - Schematic of the

I".

and 2"'. slages of rhe opamp used in The open-loop gain of the npamp is given by the product of the gain of all stages, yielding

the GNG. The 3" stage (nor shown) is e q u a l to the 2"'.

The input-referred spectral density of the opamp, vi;(/) _is defined by the folded-input stage and given by

2 2

v"i(f) = 4 . k .

T

_{y ,}

3 . g m ~ (3)

where gm, is the transconductance of the input PMOS differential-pair and y is approximately given by:

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which comprises basically the noise contributions of the current-sources of the folded-input stage (Micas and M2 de-

cdb3(3dslage) + 'dbl(3rd.stage) + Cdb6(3rd.stage) + 'L gdsI(3rd.stage) + gds4(1rd,stage) + gds6(3rd.stagc) + g L 7"0",3

Usually only one of these time-constants is dominant, typi- cally

rnin

or rnFold , depending on the sizing and on the load.

Finally the total power dissipated by this circuit, Pror, is given by (excluding the CMFB and the biasing circuitry):

PTOT = V D D . ( I S + ~ . I C A S + 2 . 1 2 + 2 . 1 2 ( 3 r d . s t a g e ) ) (7)

B)

Circuit

Optimization

The circuit was designed and optimised for a 0 . 3 5 ~ CMOS standard technology with VTp =-0.65V1 VTn = 0.52V and able to operate at a supply voltage of I .5 V. An equation- based design methodology for optimization using genetic algorithms such as the one reported in [5,6] was used since many performance parameters had to b e simultaneously op- timized ( A , A$, V,, , PTOr ) with a relatively high number of devices (variables). The fitness hnction, /(.?), was defined according to expression (8), taking into account the low- frequency gain, the bandwidth, the output-referred rms noise and the total power dissipation.

-(- )

f ( 2 ) *_d-;red ^-(- 4 )

) I O \

Af _desired A

X - e

The genes comprised in each chromosome,

X

, are basically the biasing currents

(Is,

IcAs. l2 and I3p,d. 3,0ge,). the channel

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lengths of all transistors, L;, as well as their saturation voltages, VDS~,.,.

3. Lv ANALOGUE CMOS

CIRCUIT FOR

TRANSFORMING

OF GAUSSIAN NOISE INTO UNIFORM NOISE

(G2U)

The proposed novel circuit implements the following transformation function:

( 9 )

)=

e - ( ( v : + " i J / 2 ) = e - ( v ? / 2 J , = - ( v ; / 2 J

f ( v 1 , v z

where v, and v2 are two uncorrelated Gaussian input variables. If vI and vz have a Gaussian distribution with zero mean and variance equal to one, N(O,I), then f ( v , , v 2 ) is uniformly distributed U(0.I) [7]. It should be noted that, a LV analogue implementation of the function e-((":+v;)/2) becomes impossible since factor -((.:+4)/2) has necessarily to be a voltage and possible values are distributed in the in- terval [(-(3-0)'/2), 01 with ^CJ= IV. However, this h n c - tion can be realized as a product of two Gaussian functions ( but it requires an additional multiplier as illustrated in the block diagram shown in Fig. 3. If the standard deviation of each GNG is smaller than 1 (for practical reasons), an additional constant, ^k,,should be introduced to compensate this reduction.

MULTIPLIER

'IP GAVSSiAN FUNCTION

Fig. 3: Block diagram reprexenting the c i ~ u i l that implemenrs the required rrans/ormation/unction ((32 U).

Each Gaussian function can have a fully-differential implementation using the circuit shown in Fig. 4 (a) comprising two source-coupled differential-pairs biased by the same tail current [SI. Two additional current-sources (Il and I>) with a nominal current of I& are required to make iiP and

6,

fully- differential current signals. Assuming vrP and v , ~ differential signals, due to the existence of resistors,

R,

the signal ap- plied to the gate of devices Mla and Mzb is always constant and equal to the input common-mode voltage. Since the biasing current, I,, is constant, the shape of the differential drain-current, ( i m

-

iiN), as a function of the differential input voltage, (viP

-

Y , ~ ) , becomes essentially Gaussian. However, the implementation of the Gaussian function is not precise,

since the referred currents have not an exact Gaussian form.

In fact, the function is described by [9]:

2 . K . I B ( i i p -iiN J =

2 . c o s h ( k 2 .(viP -viN )J+ K

where K represents the multiplicity of transistors M2 in par- allel ( K = 2 in this case) and

Q

represents an adjusting constant. For relatively small input signals and reduced biasing currents the relative error can be made small. In order to perform the product of both Gaussian functions the differential trans-linear multiplier shown in Fig. 4 (b) is used [IO].

Analyzing this circuit it can be found that its output is given hv

R I R

Q ^1'.

4

^(PI^-GAUSSIAN RRlCTlON V.'

v..

(b) . TRANSLINEAR MULTIPLIER

Fig. 4 ^{(a) -}Circuit u s e d f o r realizing the Gaussianfunction;

@) - Four-quadrnnl trans-linear current-mode multiplier.

4. CIRCUIT'S

SIZING AND SIMULATED RESULTS AJ The GNG ^block

Table 1 compares the obtained values of the GNG after the optimization described with post-simulated (ac simulations) values for the circuit using an electrical simulator. Using R3=100kR, gmr= 55pS, I, = ZOpA, IC,,= 47pA, ^I2= 37pA, I>,,,,, sicre, = 196pA, y = 12 and C,,= 0.1 pF a differential GNG with a= 232mV and with bandwidth of about IO MHz can be designed.

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Table I

I

Spccs.

1

Spccs,achieved

1

Elechicalsimu-

I

Y 1””,

A [dB]

I

80

I

^{1 2}

I

⁶⁴

df[MHzI

1

IO

I

8 to

Pmr[mW]

I

< s

I

0.87

I

^0.93

The major differences appear in the open-loop gain, A , as well as in the bandwidth,

4

The reason is mainly due to the equations used for the drain-source conductances, which are not precise for small drain-source voltages.

B) The G2U block

The complete circuit is designed for the same referred 0.35pm CMOS technology. Two of the GNG previously described designed with o = 0.25/3V are used. The circuit is supplied with VDD ⁼ I S V , the bias current is fixed at

I,

= l o o @ , and k, is adjusted to 72 by sizing M,,, Mlb, M2s. Mzb with W / H X M I . 4

( V D S ~ ~ ~ ( M , , , M ~ ~ ) - -

40mV ). De- vices M4a, M4b, Ms., Mlb, M-, Mab, M7a, M7b are sized with W/L=50/0.4 ( V D ~ ~ , ( M , , , M , , , M , , , M , , ) = IlOmV). Current- sources l,, I,, and 1, are implemented with simple NMOS and PMOS current-mirrors. The output current is converted to voltage through 5 k n resistors to achieve output-noise voltage amplitudes of about 100mV. Output loading capaci- tances ofO.2pF are used.

Fig. 5 (a) - Input differential Gaussian noise voltage and corre- sponding histogram; (b) - Output diflerential uniform noise volt-

age and corresponding histogram.

The transformation function, f ( v l , v 2 ) , was electrically simulated using two equal differential input ramp-signals producing a differential output current with less than 0.4%

of maximum relative error to the ideal function. This error was obtained using

where npts is the number of simulated points (npts =

IOOOO)

and, f.’(vI,vr)and fi(vl,vz) represent, respectively, the simulated and the ideal transformation functions.

The complete circuit dissipates about 750pW for at 1.5V.

This circuit was also electrically simulated by directly ap- plying two differential Gaussian-noise signals with 216 points generated in MATLAB. Fig. 5 (a) displays the input differential Gaussian noise voltage signal and its histogram and Fig. 5 (b) shows the output differential uniform noise current signal and its histogram.

5.

CONCLUSIONS

A broadband CMOS analogue circuit for Gaussian noise generation as well as a new circuit for transforming Gaus- sian noise into uniform noise designed for a supply voltage of 1.5 V were presented. Electrical simulations proved that high noise amplitudes and reasonable bandwidths can be achieved with relatively low power consumption.

Acknowledgments

The research work that led to this implementation was partially supported by the Portuguese Foundation fur Science and Technol- ogy (FCT/MCT) under ADOPT (POCTIIESEi333I 1/1999), S2A (POCTIIESEI38689/2001), SAMBA (POCTIIESE/4180412001) and SECA (POCTI/ESE/47061/2002) Projects.

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Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation