C a c h e M e m o ri e s O c to b e r 6 , 2 0 0 6 C a c h e M e m o ri e s O c to b e r 6 , 2 0 0 6 T o p ic s T o p ic s G e n e ri c c a c h e m e m o ry o rg a n iz a ti o n D ir e c t m a p p e d c a c h e s S e t a s s o c ia ti v e c a c h e s Im p a c t o f c a c h e s o n p e rf o rm a n c e T h e m e m o ry m o u n ta in class12.ppt
1 5 -2 1 3 “ T h e c o u rs e t h a t g iv e s C M U i ts Z ip !” –2–15-213, F’06
C a c h e M e m o ri e s C a c h e M e m o ri e s C a c h e m e m o ri e s a re s m a ll , fa s t S R A M C a c h e m e m o ri e s a re s m a ll , fa s t S R A M -- b a s e d m e m o ri e s b a s e d m e m o ri e s m a n a g e d a u to m a ti c a ll y i n h a rd w a re . m a n a g e d a u to m a ti c a ll y i n h a rd w a re . Hold frequently accessed blocks of main memory C P U l o o k s f ir s t fo r d a ta i n L 1 , th e n i n L 2 , th e n i n m a in C P U l o o k s f ir s t fo r d a ta i n L 1 , th e n i n L 2 , th e n i n m a in m e m o ry . m e m o ry . T y p ic a l s y s te m s tr u c tu re : T y p ic a l s y s te m s tr u c tu re :
main memoryI/O bridgebus interfaceL2 data
ALU
register fileCPU chip SRAM Portsystem busmemory busL1 cacheL2 tags –3–15-213, F’06
In s e rt in g a n L 1 C a c h e B e tw e e n th e C P U a n d M a in M e m o ry In s e rt in g a n L 1 C a c h e B e tw e e n th e C P U a n d M a in M e m o ry
a b c dblock 10 p q r sblock 21... ...
w x y zblock 30...
The big slowmain memoryhas room for many 4-word blocks.
The small fastL1 cachehas room for two 4-word blocks.
The tiny, very fast CPU register filehas room for four 4-byte words. The transfer unit between the cache andmain memory is a 4-word block (16 bytes).
The transfer unit between the CPU register fileand the cacheis a 4-byte block. line 0 line 1 –4–15-213, F’06
G e n e ra l O rg a n iz a ti o n o f a C a c h e G e n e ra l O rg a n iz a ti o n o f a C a c h e
•••B–110 •••B–110valid valid
tag tagset 0:
B = 2bbytes per cache block E lines per set S = 2ssets
ttag bits per line Cache size: C = B x E x S data bytes
••• •••B–110 •••B–110
valid valid
tag tagset 1:••• •••B–110 •••B–110
valid valid
tag tagset S-1:•••
•••
Cache is an array of sets. Each set contains one or more lines. Each line holds a block of data. 1 valid bit per line
–5–15-213, F’06
A d d re s s in g C a c h e s A d d re s s in g C a c h e s
tbitssbitsbbits <tag><set index><block offset>0m-1
Address A: •••B–110 •••B–110
v v
tag tagset 0:••• •••B–110 •••B–110
v v
tag tagset 1:••• •••B–110 •••B–110
v v
tag tagset S-1:•••
••• The word at address A is in the cache if the tag bits in one of the <valid> lines in set <set index> match <tag>. The word contents begin at offset <block offset> bytes from the beginning of the block. –6–15-213, F’06
A d d re s s in g C a c h e s A d d re s s in g C a c h e s
tbitssbitsbbits <tag><set index><block offset>0m-1
Address A: •••B–110 •••B–110
v v
tag tagset 0:••• •••B–110 •••B–110
v v
tag tagset 1:••• •••B–110 •••B–110
v v
tag tagset S-1:•••
••• 1.Locate the set based on <set index> 2.Locate the line in the set based on <tag> 3.Check that the line is valid 4.Locate the data in the line based on <block offset> –7–15-213, F’06
D ir e c t- M a p p e d C a c h e D ir e c t- M a p p e d C a c h e S im p le s t k in d o f c a c h e , e a s y t o b u il d S im p le s t k in d o f c a c h e , e a s y t o b u il d (o n ly 1 t a g c o m p a re r e q u ir e d p e r a c c e s s ) (o n ly 1 t a g c o m p a re r e q u ir e d p e r a c c e s s ) C h a ra c te ri z e d b y e x a c tl y o n e l in e p e r s e t. C h a ra c te ri z e d b y e x a c tl y o n e l in e p e r s e t. valid valid valid
tag tag tag
•••
set 0: set 1: set S-1:
E=1 lines per setcache block cache block cache block Cache size: C = B x S data bytes –8–15-213, F’06
A c c e s s in g D ir e c t- M a p p e d C a c h e s A c c e s s in g D ir e c t- M a p p e d C a c h e s S e t s e le c ti o n S e t s e le c ti o n Use the set index bits to determine the set of interest. tbitssbits 0 0 0 0 1 0m-1
bbits tagset indexblock offset
se le ct ed s et
valid valid validtag tag tag
•••
set 0: set 1: set S-1:
cache block cache block cache block
–9–15-213, F’06
A c c e s s in g D ir e c t- M a p p e d C a c h e s A c c e s s in g D ir e c t- M a p p e d C a c h e s L in e m a tc h in g a n d w o rd s e le c ti o n L in e m a tc h in g a n d w o rd s e le c ti o n Line matching: Find a valid line in the selected set with a matching tag Word selection: Then extract the word tbitssbits 100i0110 0m-1
bbits tagset indexblock offset
selected set (i):10110w3w0w1w2
30127456=1?(1) The valid bit must be set = ?(2)The tag bits in the cache line must match the tag bits in the address
If (1) and (2), thencache hit –10–15-213, F’06
A c c e s s in g D ir e c t- M a p p e d C a c h e s A c c e s s in g D ir e c t- M a p p e d C a c h e s L in e m a tc h in g a n d w o rd s e le c ti o n L in e m a tc h in g a n d w o rd s e le c ti o n Line matching: Find a valid line in the selected set with a matching tag Word selection: Then extract the word t bitss bits 100i0110 0m-1
b bits tagset indexblock offset
selected set (i):10110w3w0w1w2
30127456 (3)If cache hit, block offset selects starting byte. –11–15-213, F’06
D ir e c t- M a p p e d C a c h e S im u la ti o n D ir e c t- M a p p e d C a c h e S im u la ti o n
M=16 byte addresses, B=2 bytes/block, S=4 sets, E=1 entry/set Address trace (reads):0 [ 0 0 0 0
2] , 1 [ 0 0 0 1
2] , 7 [ 0 1 1 1
2] , 8 [ 1 0 0 0
2] , 0 [ 0 0 0 0
2]
x t= 1 s= 2 b =1 x x x
0??v ta g d at a
miss 10M[0-1]
hit miss 10M[6-7]
miss 11M[8-9]
miss 10M[0-1] –12–15-213, F’06
S e t A s s o c ia ti v e C a c h e s S e t A s s o c ia ti v e C a c h e s C h a ra c te ri z e d b y m o re t h a n o n e l in e p e r s e t C h a ra c te ri z e d b y m o re t h a n o n e l in e p e r s e t E=2 lines per set
validtag set 0: set 1: set S-1:
•••
cache block validtagcache block validtagcache block validtagcache block validtagcache block validtagcache block
E -w ay a ss oc ia ti ve c ac h e
–13–15-213, F’06
A c c e s s in g S e t A s s o c ia ti v e C a c h e s A c c e s s in g S e t A s s o c ia ti v e C a c h e s S e t s e le c ti o n S e t s e le c ti o n identical to direct-mapped cache valid validtag tagset 0: valid validtag tagset 1: valid validtag tagset S-1:
•••
cache block cache block cache block cache block cache block cache block tbitssbits 0 0 0 0 1 0m-1
bbits tagset indexblock offset
se le ct ed s et
–14–15-213, F’06A c c e s s in g S e t A s s o c ia ti v e C a c h e s A c c e s s in g S e t A s s o c ia ti v e C a c h e s L in e m a tc h in g a n d w o rd s e le c ti o n L in e m a tc h in g a n d w o rd s e le c ti o n must compare the tag in each valid line in the selected set. 10110w3w0w1w2
11001 selected set (i):
30127456 tbitssbits 100i0110 0m-1
bbits tagset indexblock offset
=1?(1) The valid bit must be set = ?
(2)The tag bits in one of the cache lines must match the tag bits in the address
If (1) and (2), thencache hit –15–15-213, F’06
A c c e s s in g S e t A s s o c ia ti v e C a c h e s A c c e s s in g S e t A s s o c ia ti v e C a c h e s L in e m a tc h in g a n d w o rd s e le c ti o n L in e m a tc h in g a n d w o rd s e le c ti o n Word selection is the same as in a direct mapped cache 10110w3w0w1w2
11001 selected set (i):
30127456 tbitssbits 100i0110 0m-1
bbits tagset indexblock offset
(3)If cache hit, block offset selects starting byte. –16–15-213, F’06
2 -W a y A s s o c ia ti v e C a c h e S im u la ti o n 2 -W a y A s s o c ia ti v e C a c h e S im u la ti o n
M=16 byte addresses, B=2 bytes/block, S=2 sets, E=2 entry/set Address trace (reads):0 [ 0 0 0 0
2] , 1 [ 0 0 0 1
2] , 7 [ 0 1 1 1
2] , 8 [ 1 0 0 0
2] , 0 [ 0 0 0 0
2]
x x t= 2 s= 1 b =1 x x
0??v ta g d at a
0 0 0miss 100M[0-1]
hit miss 101M[6-7]
miss 110M[8-9]
hit
–17–15-213, F’06
W h y U s e M id d le B it s a s I n d e x ? W h y U s e M id d le B it s a s I n d e x ? H ig h H ig h -- O rd e r B it I n d e x in g O rd e r B it I n d e x in g Adjacent memory lines would map to same cache entry Poor use of spatial locality M id d le M id d le -- O rd e r B it I n d e x in g O rd e r B it I n d e x in g
Consecutive memory lines map to different cache lines Can hold S*B*E-byte region of address space in cache at one time
4-line CacheHigh-Order Bit IndexingMiddle-Order Bit Indexing 00 01 10 11
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 –18–15-213, F’06
M a in ta in in g a S e t- A s s o c ia te C a c h e M a in ta in in g a S e t- A s s o c ia te C a c h e
H o w t o d e c id e w h ic h c a c h e l in e t o u s e i n a s e t? H o w t o d e c id e w h ic h c a c h e l in e t o u s e i n a s e t?
Least Recently Used (LRU), Requires lg2(E!)extra bits Not recently Used (NRU) RandomV ir tu a l v s . P h y s ic a l a d d re s s e s : V ir tu a l v s . P h y s ic a l a d d re s s e s :
The memory system works with physical addresses, but it takes time to translate a virtual to a physical address. So most L1 caches are virtually indexed, but physically tagged. –19–15-213, F’06M u lt i- L e v e l C a c h e s M u lt i- L e v e l C a c h e s O p ti o n s : s e p a ra te O p ti o n s : s e p a ra te d a ta d a ta a n d a n d in s tr u c ti o n c a c h e s in s tr u c ti o n c a c h e s , o r a , o r a u n if ie d c a c h e u n if ie d c a c h e size: speed: $/Mbyte: line size:
200 B 3 ns 8 B
8-64 KB 3 ns 32 B
128 MB DRAM 60 ns $1.50/MB 8 KB 30 GB 8 ms $0.05/MB larger, slower, cheaper
MemoryMemory
Regs Unified L2 Cache
Unified L2 Cache
Processor 1-4MB SRAM 6 ns $100/MB 32 B
diskdisk
L1 d-cache L1 i-cache –20–15-213, F’06
W h a t a b o u t w ri te s ? W h a t a b o u t w ri te s ? M u lt ip le c o p ie s o f d a ta e x is t: M u lt ip le c o p ie s o f d a ta e x is t: L1 L2 Main Memory Disk W h a t to d o w h e n w e w ri te ? W h a t to d o w h e n w e w ri te ?
Write-through Write-back need a dirty bit What to do on a write-miss? W h a t to d o o n a r e p la c e m e n t? W h a t to d o o n a r e p la c e m e n t?
Depends on whether it is write through or write back
–21–15-213, F’06
In te l P e n ti u m I II C a c h e H ie ra rc h y In te l P e n ti u m I II C a c h e H ie ra rc h y
Processor ChipProcessor ChipL1 Data 1 cycle latency 16 KB 4-way assoc Write-through 32B lines L1 Instruction 16 KB, 4-way 32B lines
Regs. L2 Unified 128KB--2 MB 4-way assoc Write-back Write allocate 32B lines L2 Unified 128KB--2 MB 4-way assoc Write-back Write allocate 32B lines
Main Memory Up to 4GB
Main Memory Up to 4GB –22–15-213, F’06
C a c h e P e rf o rm a n c e M e tr ic s C a c h e P e rf o rm a n c e M e tr ic s
Miss RateMiss Rate Fraction of memory references not found in cache (misses / references) Typical numbers: 3-10% for L1 can be quite small (e.g., < 1%) for L2, depending on size, etc. Hit TimeHit Time Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: 1-2 clock cycle for L1 5-20 clock cycles for L2 Miss PenaltyMiss Penalty Additional time required because of a miss Typically 50-200 cycles for main memory (Trend: increasing!)Aside for architects: -Increasing cache size? -Increasing block size? -Increasing associativity? –23–15-213, F’06
W ri ti n g C a c h e F ri e n d ly C o d e W ri ti n g C a c h e F ri e n d ly C o d e •• R e p e a te d r e fe re n c e s t o v a ri a b le s a re g o o d R e p e a te d r e fe re n c e s t o v a ri a b le s a re g o o d (( te m p o ra l lo c a li ty te m p o ra l lo c a li ty )) •• S tr id e S tr id e -- 1 r e fe re n c e p a tt e rn s a re g o o d ( 1 r e fe re n c e p a tt e rn s a re g o o d ( s p a ti a l lo c a li ty s p a ti a l lo c a li ty ))
E x a m p le s : •• E x a m p le s :
cold cache, 4-byte words, 4-word cache blocks intsum_array_rows(inta[M][N]) { inti,j,sum=0; for(i=0;i<M;i++) for(j=0;j<N;j++) sum+=a[i][j]; returnsum; } intsum_array_cols(inta[M][N]) { inti,j,sum=0; for(j=0;j<N;j++) for(i=0;i<M;i++) sum+=a[i][j]; returnsum; } Miss rate =Miss rate =1/4 = 25%100% –24–15-213, F’06T h e M e m o ry M o u n ta in T h e M e m o ry M o u n ta in R e a d t h ro u g h p u t (r e a d b a n d w id th ) R e a d t h ro u g h p u t (r e a d b a n d w id th ) Number of bytes read from memory per second (MB/s) M e m o ry m o u n ta in M e m o ry m o u n ta in
Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance.
–25–15-213, F’06
M e m o ry M o u n ta in T e s t F u n c ti o n M e m o ry M o u n ta in T e s t F u n c ti o n
/*Thetestfunction*/ voidtest(intelems,intstride){ inti,result=0; volatileintsink; for(i=0;i< elems;i+=stride) result+=data[i]; sink=result;/*Socompilerdoesn'toptimizeawaytheloop*/ } /*Runtest(elems,stride)andreturnreadthroughput(MB/s)*/ doublerun(intsize,intstride,doubleMhz) { doublecycles; intelems=size/sizeof(int); test(elems,stride);/*warm up thecache*/ cycles=fcyc2(test,elems,stride,0);/*calltest(elems,stride)*/ return(size/stride)/(cycles/Mhz);/*convertcyclestoMB/s*/ } –26–15-213, F’06M e m o ry M o u n ta in M a in R o u ti n e M e m o ry M o u n ta in M a in R o u ti n e
/*mountain.c-Generatethememorymountain.*/ #defineMINBYTES(1<< 10)/*Workingsetsizerangesfrom 1KB*/ #defineMAXBYTES(1<< 23)/*...up to8MB*/ #defineMAXSTRIDE16/*Stridesrangefrom 1to16*/ #defineMAXELEMSMAXBYTES/sizeof(int) intdata[MAXELEMS];/*Thearraywe'llbetraversing*/ intmain() { intsize;/*Workingsetsize(inbytes)*/ intstride;/*Stride(inarrayelements)*/ doubleMhz;/*Clockfrequency*/ init_data(data,MAXELEMS);/*Initializeeachelementindatato1*/ Mhz=mhz(0);/*Estimatetheclockfrequency*/ for(size=MAXBYTES;size>=MINBYTES;size>>=1){ for(stride=1;stride<=MAXSTRIDE;stride++) printf("%.1f\t",run(size,stride,Mhz)); printf("\n"); } exit(0); } –27–15-213, F’06T h e M e m o ry M o u n ta in T h e M e m o ry M o u n ta in
s1 s3
s5 s7
s9 s1 1
s1 3
s1 5
8m 2m 51 2k 12 8k 32 k 8k 2k
0
200
400
600
800
1000
1200 L1 L2 mem
xe Slopes of Spatial Locality
Pentium III 550 MHz 16 KB on-chip L1 d-cache 16 KB on-chip L1 i-cache 512 KB off-chip unified L2 cache Ridges of Temporal Locality Working set size (bytes)Stride (words)
Th rou gh put (M B/s ec)
–28–15-213, F’06
X 8 6 -6 4 M e m o ry M o u n ta in X 8 6 -6 4 M e m o ry M o u n ta in
s1 s5
s9 s1 3
s1 7
s2 1
s2 5
s2 9
128m
4m
128k
4k 0
1000
2000
3000
4000
5000
6000
Re ad T hro ug hp ut (M B/s )
Stride (words)
Working Set Size (bytes)
Slopes of Spatial Locality
Ridges of Temporal Locality Mem
L2
L1
Pentium Nocona Xeon x86-64 3.2 GHz 12 Kuop on-chip L1 trace cache 16 KB on-chip L1 d-cache 1 MB off-chip unified L2 cache
–29–15-213, F’06
O p te ro n M e m o ry M o u n ta in O p te ro n M e m o ry M o u n ta in
s1 s5
s9 s1 3
s1 7
s2 1
s2 5
s2 9
128m
4m
128k
4k 0
500
1000
1500
2000
2500
3000 Read throughput (MB/s) Stride (words)
Working set (bytes)
AMD Opteron 2 GHZL1 L2 Mem –30–15-213, F’06
R id g e s o f T e m p o ra l L o c a li ty R id g e s o f T e m p o ra l L o c a li ty S li c e t h ro u g h t h e m e m o ry m o u n ta in w it h s tr id e = 1 S li c e t h ro u g h t h e m e m o ry m o u n ta in w it h s tr id e = 1 illuminates read throughputs of different caches and memory 0
200
400
600
800
1000
1200
8m 4m 2m 10 24 k
51 2k
25 6k
12 8k
64 k
32 k
16 k
8k 4k 2k 1k
working set size (bytes)
re ad th ro ug pu t ( MB /s )
L1 cache regionL2 cache regionmain memory region –31–15-213, F’06
A S lo p e o f S p a ti a l L o c a li ty A S lo p e o f S p a ti a l L o c a li ty S li c e t h ro u g h m e m o ry m o u n ta in w it h s iz e = 2 5 6 K B S li c e t h ro u g h m e m o ry m o u n ta in w it h s iz e = 2 5 6 K B shows cache block size. 0
100
200
300
400
500
600
700
800 s1s2s3s4s5s6s7s8s9s10s11s12s13s14s15s16 stride (words)
re ad th ro ug hp ut (M B/s )
one access per cache line –32–15-213, F’06
M a tr ix M u lt ip li c a ti o n E x a m p le M a tr ix M u lt ip li c a ti o n E x a m p le M a jo r C a c h e E ff e c ts t o C o n s id e r M a jo r C a c h e E ff e c ts t o C o n s id e r Total cache size Exploit temporal locality and keep the working set small (e.g., use blocking) Block size Exploit spatial locality D e s c ri p ti o n : D e s c ri p ti o n :
Multiply N x N matrices O(N3) total operations Accesses N reads per source element N values summed per destination »but may be able to hold in register
/*ijk*/ for(i=0;i<n;i++){ for(j=0;j<n;j++){ sum=0.0; for(k=0;k<n;k++) sum+=a[i][k]*b[k][j]; c[i][j]=sum; } }
/*ijk*/ for(i=0;i<n;i++){ for(j=0;j<n;j++){ sum=0.0; for(k=0;k<n;k++) sum+=a[i][k]*b[k][j]; c[i][j]=sum; } } Variable sum held in register
–33–15-213, F’06
M is s R a te A n a ly s is f o r M a tr ix M u lt ip ly M is s R a te A n a ly s is f o r M a tr ix M u lt ip ly A s s u m e : A s s u m e : Line size = 32B (big enough for four 64-bit words) Matrix dimension (N) is very large Approximate 1/N as 0.0 Cache is not even big enough to hold multiple rows A n a ly s is M e th o d : A n a ly s is M e th o d :
Look at access pattern of inner loop CAk
i B
k
j i
j –34–15-213, F’06
L a y o u t o f C A rr a y s i n M e m o ry (r e v ie w ) L a y o u t o f C A rr a y s i n M e m o ry (r e v ie w ) C a rr a y s a ll o c a te d i n r o w C a rr a y s a ll o c a te d i n r o w -- m a jo r o rd e r m a jo r o rd e r each row in contiguous memory locations S te p p in g t h ro u g h c o lu m n s i n o n e r o w : S te p p in g t h ro u g h c o lu m n s i n o n e r o w :
for(i=0;i<N;i++) sum+=a[0][i]; accesses successive elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B S te p p in g t h ro u g h r o w s i n o n e c o lu m n : S te p p in g t h ro u g h r o w s i n o n e c o lu m n :
for(i=0;i<n;i++) sum+=a[i][0]; accesses distant elements no spatial locality! compulsory miss rate = 1 (i.e. 100%) –35–15-213, F’06
M a tr ix M u lt ip li c a ti o n ( ij k ) M a tr ix M u lt ip li c a ti o n ( ij k )
/*ijk*/ for(i=0;i<n;i++){ for(j=0;j<n;j++){ sum=0.0; for(k=0;k<n;k++) sum+=a[i][k]*b[k][j]; c[i][j]=sum; } }/*ijk*/ for(i=0;i<n;i++){ for(j=0;j<n;j++){ sum=0.0; for(k=0;k<n;k++) sum+=a[i][k]*b[k][j]; c[i][j]=sum; } }ABC(i,*)
(*,j) (i,j)
Inner loop: Column- wiseRow-wiseFixed
M is se s p er I n n er L o o p I te ra ti o n : A B C 0 .2 5 1 .0 0 .0
–36–15-213, F’06M a tr ix M u lt ip li c a ti o n ( ji k ) M a tr ix M u lt ip li c a ti o n ( ji k )
/*jik*/ for(j=0;j<n;j++){ for(i=0;i<n;i++){ sum=0.0; for(k=0;k<n;k++) sum+=a[i][k]*b[k][j]; c[i][j]=sum } }/*jik*/ for(j=0;j<n;j++){ for(i=0;i<n;i++){ sum=0.0; for(k=0;k<n;k++) sum+=a[i][k]*b[k][j]; c[i][j]=sum } }ABC(i,*)
(*,j) (i,j)
Inner loop: Row-wiseColumn- wiseFixed
M is se s p er I n n er L o o p I te ra ti o n : A B C 0 .2 5 1 .0 0 .0
–37–15-213, F’06
M a tr ix M u lt ip li c a ti o n ( k ij ) M a tr ix M u lt ip li c a ti o n ( k ij )
/*kij*/ for(k=0;k<n;k++){ for(i=0;i<n;i++){ r=a[i][k]; for(j=0;j<n;j++) c[i][j]+=r*b[k][j]; } }/*kij*/ for(k=0;k<n;k++){ for(i=0;i<n;i++){ r=a[i][k]; for(j=0;j<n;j++) c[i][j]+=r*b[k][j]; } }ABC(i,*)(i,k)(k,*)
Inner loop: Row-wiseRow-wiseFixed
M is se s p er I n n er L o o p I te ra ti o n : A B C 0 .0 0 .2 5 0 .2 5
–38–15-213, F’06M a tr ix M u lt ip li c a ti o n ( ik j) M a tr ix M u lt ip li c a ti o n ( ik j)
/*ikj*/ for(i=0;i<n;i++){ for(k=0;k<n;k++){ r=a[i][k]; for(j=0;j<n;j++) c[i][j]+=r*b[k][j]; } }/*ikj*/ for(i=0;i<n;i++){ for(k=0;k<n;k++){ r=a[i][k]; for(j=0;j<n;j++) c[i][j]+=r*b[k][j]; } }ABC(i,*)(i,k)(k,*)
Inner loop: Row-wiseRow-wiseFixed
M is se s p er I n n er L o o p I te ra ti o n : A B C 0 .0 0 .2 5 0 .2 5
–39–15-213, F’06M a tr ix M u lt ip li c a ti o n ( jk i) M a tr ix M u lt ip li c a ti o n ( jk i)
/*jki*/ for(j=0;j<n;j++){ for(k=0;k<n;k++){ r=b[k][j]; for(i=0;i<n;i++) c[i][j]+=a[i][k]*r; } }/*jki*/ for(j=0;j<n;j++){ for(k=0;k<n;k++){ r=b[k][j]; for(i=0;i<n;i++) c[i][j]+=a[i][k]*r; } }ABC
(*,j) (k,j)
Inner loop: (*,k) Column - wiseColumn- wiseFixed
M is se s p er I n n er L o o p I te ra ti o n : A B C 1 .0 0 .0 1 .0
–40–15-213, F’06M a tr ix M u lt ip li c a ti o n ( k ji ) M a tr ix M u lt ip li c a ti o n ( k ji )
/*kji*/ for(k=0;k<n;k++){ for(j=0;j<n;j++){ r=b[k][j]; for(i=0;i<n;i++) c[i][j]+=a[i][k]*r; } }/*kji*/ for(k=0;k<n;k++){ for(j=0;j<n;j++){ r=b[k][j]; for(i=0;i<n;i++) c[i][j]+=a[i][k]*r; } }ABC
(*,j) (k,j)
Inner loop: (*,k) FixedColumn- wiseColumn- wise
M is se s p er I n n er L o o p I te ra ti o n : A B C 1 .0 0 .0 1 .0
–41–15-213, F’06
S u m m a ry o f M a tr ix M u lt ip li c a ti o n S u m m a ry o f M a tr ix M u lt ip li c a ti o n ij k (& j ik ): •2 l oa d s, 0 s to re s • m is se s/ it er = 1 .2 5 ki j (& i kj ):
•2 l oa d s, 1 s to re • m is se s/ it er = 0 .5 jk i (& k ji ):
•2 l oa d s, 1 s to re • m is se s/ it er = 2 .0
for(i=0;i<n;i++){ for(j=0;j<n;j++){ sum=0.0; for(k=0;k<n;k++) sum+=a[i][k]*b[k][j]; c[i][j]=sum; } } for(k=0;k<n;k++){ for(i=0;i<n;i++){ r=a[i][k]; for(j=0;j<n;j++) c[i][j]+=r*b[k][j]; } } for(j=0;j<n;j++){ for(k=0;k<n;k++){ r=b[k][j]; for(i=0;i<n;i++) c[i][j]+=a[i][k]*r; } }–42–15-213, F’06
P e n ti u m M a tr ix M u lt ip ly P e rf o rm a n c e P e n ti u m M a tr ix M u lt ip ly P e rf o rm a n c e M is s r a te s a re h e lp fu l b u t n o t p e rf e c t p re d ic to rs . M is s r a te s a re h e lp fu l b u t n o t p e rf e c t p re d ic to rs . Code scheduling matters, too. 0
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kji jki kij ikj jik ijk
kj i & j ki ki j & i kj ji k & i jk
–43–15-213, F’06Im p ro v in g T e m p o ra l L o c a li ty b y B lo c k in g Im p ro v in g T e m p o ra l L o c a li ty b y B lo c k in g E x a m p le : B lo c k e d m a tr ix m u lt ip li c a ti o n E x a m p le : B lo c k e d m a tr ix m u lt ip li c a ti o n “block”(in this context) does not mean “cache block”. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 C11= A11B11+ A12B21 C12= A11B12+ A12B22 C21= A21B11+ A22B21 C22= A21B12+ A22B22
A11A12 A21A22
B11B12 B21B22X= C11C12 C21C22 Key idea:Sub-blocks (i.e., Axy) can be treated just like scalars. –44–15-213, F’06
B lo c k e d M a tr ix M u lt ip ly ( b ij k ) B lo c k e d M a tr ix M u lt ip ly ( b ij k )
for(jj=0;jj<n;jj+=bsize){ for(i=0;i<n;i++) for(j=jj;j<min(jj+bsize,n);j++) c[i][j]=0.0; for(kk=0;kk<n;kk+=bsize){ for(i=0;i<n;i++){ for(j=jj;j<min(jj+bsize,n);j++){ sum=0.0 for(k=kk;k<min(kk+bsize,n);k++){ sum+=a[i][k]*b[k][j]; } c[i][j]+=sum; } } } }–45–15-213, F’06
B lo c k e d M a tr ix M u lt ip ly A n a ly s is B lo c k e d M a tr ix M u lt ip ly A n a ly s is
Innermost loop pair multiplies a1 X bsizesliver of Aby absize X bsizeblock of Band accumulates into1 X bsizesliver of C Loop over isteps throughnrow slivers of A&C, using sameB ABC block reusedn times in succession row sliver accessed bsizetimesUpdate successive elements of sliveriikk
kkjjjj
for(i=0;i<n;i++){ for(j=jj;j<min(jj+bsize,n);j++){ sum=0.0 for(k=kk;k<min(kk+bsize,n);k++){ sum+=a[i][k]*b[k][j]; } c[i][j]+=sum; }Innermost Loop Pair –46–15-213, F’06
P e n ti u m B lo c k e d M a tr ix M u lt ip ly P e rf o rm a n c e P e n ti u m B lo c k e d M a tr ix M u lt ip ly P e rf o rm a n c e B lo c k in g ( B lo c k in g ( b ij k b ij k a n d a n d b ik j b ik j ) im p ro v e s p e rf o rm a n c e b y a ) im p ro v e s p e rf o rm a n c e b y a fa c to r o f tw o o v e r u n b lo c k e d v e rs io n s ( fa c to r o f tw o o v e r u n b lo c k e d v e rs io n s ( ij k ij k a n d a n d ji k ji k ))
relatively insensitive to array size. 0
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kji jki kij ikj jik ijk bijk (bsize = 25) bikj (bsize = 25) –47–15-213, F’06
C o n c lu d in g O b s e rv a ti o n s C o n c lu d in g O b s e rv a ti o n s P ro g ra m m e r c a n o p ti m iz e f o r c a c h e p e rf o rm a n c e P ro g ra m m e r c a n o p ti m iz e f o r c a c h e p e rf o rm a n c e How data structures are organized How data are accessed Nested loop structure Blocking is a general technique A ll s y s te m s f a v o r A ll s y s te m s f a v o r ““ c a c h e f ri e n d ly c o d e c a c h e f ri e n d ly c o d e ””
Getting absolute optimum performance is very platform specific Cache sizes, line sizes, associativities, etc. Can get most of the advantage with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality)
