TEST BENCH FOR DYNAMIC RANGE TESTING OF ADC

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TEST BENCH FOR DYNAMIC RANGE

TESTING OF ADC

K.HARIHARAN

Electronics and Communication Engineering Dept., Thiagarajar College Of Engineering, Madurai-625015 Madurai, Tamil Nadu, India

khh@tce.edu.

E.BENITTA HUBERT

benitta@tce.edu

K.V.O.DIVYA LAKSHMI

divyalakshmi@tce.edu

K.SHAMALLA

shamalla@tce.edu

Dr.V.ABHAI KUMAR

Abstract:

A built-in self-test (BIST) approach based on a direct digital frequency synthesizer (DDFS) for the dynamic range testing of ADC is proposed. Testing analog components using spectral techniques requires a coherent sinusoidal stimulus. The sinusoidal test stimulus is generated using a direct digital frequency synthesizer, which is based on a new novel approach of using extended Taylor series approximations. The merit of DDFS is that the output frequency can be precisely and rapidly manipulated under digital control. The BIST method aims at full dynamic characterization of an ADC under test (DUT), while maintaining low area overhead. A low complexity DDFS has been proposed in this paper and the design approach for BIST of ADC is discussed.

Keywords: Built-In Self Test (BIST); Direct Digital Frequency Synthesis (DDFS); dynamic range.

1. INTRODUCTION

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and distortion ratio (SINAD).Dynamic characterization of the ADC is important in the field of communication and embedded systems. These dynamic parameters can be computed from the harmonic values and the noise value. Harmonic and noise values of a given converter can be evaluated from its spectral analysis wherein a single tone sine wave is applied to the converter input and FFT of the output signal is computed.

A complete Built-In Self Test procedure that utilizes the SoC inbuilt resources is a good alternative to reduce test costs when compared to external mixed-signal testers. Section 2 deals with the proposed BIST technique. Test pattern is generated using Direct Digital Frequency Synthesizer using extended Taylor Series approximation and is discussed in Section 3. The condition for coherent sampling is briefed in Section 4. Section 5 deals with the pseudo code for the BIST controller. ADC testing methodology is dealt in section 6.

2. PROPOSED BIST TECHNIQUE

A back-to back testing methodology is proposed, in which the output of the DAC is fed to the ADC (Device under Test) [Dai et al, (2006)] [Yang et al, (2005)]. The proposed BIST architecture is shown in Fig.1.The architecture consists of a DDFS based test pattern generator (TPG). Input clock (CLK) and the frequency control word (FCW) are controlled by the BIST controller. The test vectors can either be fed into a register manually or it can be generated through the DDFS. The digitized test pattern from DDFS or the DAC register is fed to a DAC through the digital multiplexer. The input to the ADC (DUT) is either the output response from the DAC or the user input (analog input) which is controlled by the analog multiplexer. The ADC is triggered by the Start Conversion signal from the BIST controller. The digital response from the ADC is stored in the memory, whose address pointer is controlled by the BIST controller.

3. TEST PATTERN GENERATION USING EXTENDED TAYLOR SERIES APPROXIMATED DDFS

Sine waves are commonly used in ADC testing. Sine wave sources are readily available and it is relatively easier to establish the quality of the sine wave (e.g., with a spectrum analyzer). Sine waves are generated using direct digital frequency synthesizers. In this paper, a new novel method towards the generation of sine waves using DDFS is presented. Taylor series expansion with an approximation algorithm is used to generate the sine waves. The proposed DDFS design provides two improvements over the traditional DDFS while maintaining the performance. First, minimizing the size of the ROM lookup table by using an approximation algorithm, and second, reducing the complexity of the system. The primary objective for using such an approach is that precision can be achieved with relatively less hardware overhead, as compared to other techniques. The spectral purity achieved by this method is 72 dBc.

Fig. 1. Proposed BIST architecture

User output User input

FCW

S1

DAC Digital Mux

Sine Wave Generator

DAC Register

S2

Analog Mux

Memory

Memory Pointer ADC

Start conversion

CLK

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Sine function can be implemented based on the following Taylor series approximations, Sin (θ) = Sin (γ) + (θ - γ) * Cos (γ) + . . . (1)

Cos (θ) = Cos (γ) - (θ - γ) * Sin (γ) + . . . (2) Another form of Taylor series expansion for sine and cosine function is,

Sin (γ) = γ – ( γ 3 / 3! ) + ( γ 5 / 5! ) – ( γ 7 / 7!) + . . . (3)

Cos (γ) = 1 – ( γ 2 / 2! ) + ( γ 4 /4! ) – ( γ 6 / 6! ) + . . . (4)

Prior algorithms are based on Eq. (1), Eq. (2) which utilize the sample magnitude of Sin (θ) stored in a ROM and its slope Cos (θ) [Hai et al, (2005)]. Typically, the sine function generation is realized by using a look up table (LUT) provided by a ROM [Vankka, (1997)]. The phase and amplitude quantization errors are determined by the number of words and the number of bits in each word in the ROM respectively. Thus it is desirable to increase the resolution of the ROM for a high spectral purity sine output. This leads to larger ROM size, which means higher power consumption and chip area, low reliability, lower speed and increased costs.

The proposed algorithm is aimed to develop DDFS for low power, reduced ROM size and high speed operation using limited hardware. The higher order terms in Eq. (1) and Eq. (2) are neglected thus,

Sin (θ) ~ Sin(γ)+(θ - γ)*Cos (γ) (5) Cos (θ) ~ Cos(γ)-(θ - γ)*Sin (γ) (6)

For N bits precision, the terms after (1–(γ2/2!)) in cos γ expansion and γ in sin γ expansion can be ignored (because they are less than 2-(N+1)). The approximations for sine and cosine functions can be simplified as follows:

From Eq. (3) and Eq. (4), it can be inferred [Chih et al, (2001)] that,

Sin (γ) ~ γ (7) Cos (γ) ~ 1 – ( γ 2 / 2! ) (8) Using Eq. (7) and Eq. (8) in Eq. (5),

Sin (θ) ~ γ + (θ - γ) *(1 – (γ 2 / 2!)) = θ – ((γ 2 / 2) * θ) + γ 3 / 2 Neglecting higher order terms,

Sin (θ) ~ (1– (γ 2 / 2)) * θ (9) The γ value for sine wave, denoted as

γ

s can be obtained using Eq. (9) as,

γ

s= √ (2 * (1- (sin θ/ θ))) (10)

Where θ holds good from 1º to 45º.

Similarly, using Eq. (7) and Eq. (8) in Eq. (6),

Cos (θ) ~ (1 + (γ * γ / 2)) - (θ * γ) (11) The γ value for cosine wave denoted as γc can be obtained using Eq. (11) as,

γc 2 -2 (θ* γc ) – 2 (cos θ – 1) = 0 (12)

where θ holds good for 1º to 45º. The minimum of the two roots from Eq. (12) is used for the computation.

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is the same as the sine from zero to Π /4. Thus, it is sufficient to compute the sine and cosine values from zero to Π/4 using Eq. (9) and Eq. (11). The entire sine wave is generated from the translations given in Table. 1.

Fig.2. shows the proposed architecture of DDFS based on the algorithm described in section 2. The N-bit frequency control word to the accumulator from the system controller determines the phase step and the frequency resolution. Generally, the linearly increasing output of the phase accumulator is used to access the sine amplitude values stored in the look-up table [Essenwanger and Reinhardt, (1998)]. In the proposed architecture, the phase accumulator output is the actual phase value itself. After the phase value reaches 360º, the accumulator content is reset to 0º. The proposed method consists of a simple computational hardware which generates sine wave from 0-45º. The 45º modulo counter detects the number of 45º increments of the phase word. The full cycle is generated by using the symmetry of sine wave [Lin-hui et al, (2008)]. The number of 45º roll over in the counter, a three bit value, is used to map one eighth of the sine wave to full wave i.e., 360º. The three bits decide the quadrant of the given phase value and the data required for mapping (90, 180, 270 or 360) to 45º is obtained from ROM. The mapping with the three bits is done according to Table.1. The LSB of the counter value is used to complement (2’s complement) the phase value, that is, if LSB is 1, the phase angle is complemented (-θ). The sine and cosine amplitude values are computed using the proposed algorithm. The second and third bits are XOR'ed to select sine or cosine function, through MUX. The generation of positive half or negative half of the sine wave is controlled by first bit of the counter value, and it is done using the sign magnitude DAC.

Fig. 2. Proposed test pattern generation architecture

2 3

3

Sign Magnitude

DAC

Sin θ output 1st MSB

0º 90º -90º 180º -180º 270º -270º 360º

3rd MSB

Mux

+

1 – γ2_/2

X

1 + γ2_/2

X

γ

θ FCW

N bits

Phase Accumulator

45º modulo Counter

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Table 1. Translation of phase values.

Counter value (bits) Phase word (θ) degrees

Phase

word

mapped to

(0-45º) 1 2 3

0 0 0 0≤θ≤45 θ

0 0 1 45<θ≤90 90 - θ

0 1 0 90<θ≤135 θ - 90 0 1 1 135<θ≤180 180 - θ 1 0 0 180<θ≤225 θ - 180 1 0 1 225<θ≤270 270 - θ 1 1 0 270<θ≤315 θ - 270 1 1 1 315<θ≤360 360 - θ

3.1.Determination of γ (γs , γc) values

γ

s values determined from Eq. (10) ranges from 1.4018 to 1.4030 which increases in a fine step per degree

increment of the angle θ. As Eq. (9) is a linear equation, sin θ value increases linearly as

γ

s increases, and so the

above equation holds good only for 1º to 45º. The sine amplitude for 0º is obtained by default, since the initial phase accumulator output is 0.

γ

c values determined from Eq. (12) ranges from 0.0015 to 0.0063 which increases in a fine step per degree

increment of the angle θ, similar to the sine wave. As Eq. (11) is a quadratic equation, cos θ value increases linearly as

γ

s increases, and so the above equation holds good only for 1º to 45º. The cosine amplitude for 0º is obtained by

default, as in sine.

The hardware overhead increases when the

γ

s values ranging from 1.4018 to 1.4030 and

γ

c values ranging from

0.0015 to 0.0063 are stored in a separate ROM. For optimization, a constant

γ

s and

γ

c is to be chosen. The

performance of the proposed DDFS (SFDR value) is indirectly dependant on the constant values

γ

s ,

γ

c.From Fig. 3

and Fig.4, it can be inferred that SFDR is maximum for particular values of

γ

sand

γ

c. Thus the constant values are

fixed as

γ

s = 1.4020 and

γ

c= 0.0048 to achieve maximum possible spectral purity. The given architecture in Fig.2. is

provided with the fixed values for both sine and cosine function. The performance (SFDR) of the proposed DDFS is about 72 dBc.

The simulations were performed with the proposed test pattern generation algorithm using MATLAB. Instead of using look up table based phase to sine amplitude conversion [Yi et al, (2006)], the proposed architecture employs combinational circuits for computation thereby reducing the computational time. The hardware overhead and performance of the proposed architecture has been compared with [Lin-hui et al, (2008)] and [Yi et al, (2006)] as shown in Table.2. The proposed test vector generation method uses only 40% lookup table size than [Lin-hui et al, (2008)] and [Yi et al, (2006)] to achieve a spectral purity of about 72 dBc. High SFDR is still achievable while using very small ROM lookup table. The spectrum obtained for the proposed architecture is shown in Fig.5.

4. CONDITION FOR COHERENT SAMPLING

The frequency of the sine wave generated from the proposed N bit DDFS can be varied using FCW. However, FCW has to satisfy the following condition for obtaining coherent sine wave samples:

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Fig. 3. Determination of γs

Fig. 4. Determination of

γc

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Table 2. Performance summary of the new DDFS.

Parameters Ref .[6] Ref .[7] Proposed

method

Bit resolution 10 17 11

SFDR (dBc) 63.58 80 72

ROM table size (bits) 328 384 132

Adder (Computation block)

(bits) One 10+10

Two 16+16 One 16+1

Two 11+11

Multiplier (Computation block) (bits)

One 10*5 (realized using shift register)

One 16*16 Two 16*12

Two 11*5

5. PSEUDO CODE FOR BIST CONTROLLER

The BIST controller computes the number of free running clocks required for a complete sinusoidal wave cycle. It enables the DONE signal once the single wave of the sinusoid is generated. The start conversion signal is a function of the free running clock and the complement of the DONE signal. Thus, the ADC is enabled using the start conversion signal. Fig.7. shows the BIST controller architecture. The pseudo code for the BIST controller is shown in Fig.6. If the start conversion signal is enabled (DONE = 0), the test signal is converted into digital form by the ADC and the responses are stored in the memory. The memory pointer is also incremented in accordance with the free running clock.

Fig. 6. Pseudo code for BIST controller

Fig.7. BIST controller architecture

If (number of clocks < (360/FCW))

DONE = 0

Else DONE = 1

If DONE = 0

Start Conversion = (Free running clock (DONE)’)*

Memory Pointer = Memory Pointer ++

Else

Start Conversion = 0

Counter (compare mode)

360/FCW

Start Conversion Free running clock

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6. TESTING METHODOLOGY

The test signal generated from the above DDFS is fed to the DAC. Then, the DAC output (sine wave) is fed to the ADC. Using a Fourier series expansion, the output signal can be expressed by Eq. (13). [Kerzerho et al ,(2007)]

s (n) = x (n) +



0

k

Hkconverter cos (k (θn + θ0) + θk) (13)

In this equation we distinguish the sampled sine-wave x (n) that would be obtained if the ADC is ideal and the sum of all the harmonic values introduced by static and dynamic non-linearity of the converter. n is the sample index, θ0 the initial phase shift, θk the phase shift induced by dynamic non-linearity, the amplitude of the kth

harmonic, and θn is the nominal sampling phase given by Eq. (14).

θn = 2π

(

M

P

)

n (14)

where P is the number of cycles and M the number of samples in the test record.

The output responses of the ADC are stored in the memory and then fed to the output response analyzer (spectrum analyzer). The spectrum of the output signal is computed in the ORA and values of the harmonics Hk

can be extracted.

The measured spectrum includes the harmonic contributions of the ADC as well as the harmonic contributions of the DAC.

Hkmeasure = HkADC + HkDAC (15)

DAC is a SoC resource and hence it is calibrated and has a high resolution. Therefore, in Eq. (15), we assume that amplitudes of harmonics created by the DAC are negligible with respect to the fundamental amplitude of the signal. In this way, we can consider that the ADC is driven by a single tone signal.

The ORA contains ADC Analyzer software that computes various dynamic parameters like SNR, SINAD, SFDR and THD from the output spectrum [Kester and Sheingold]. Thus, dynamic characterization of ADC is done.

7. CONCLUSION

This paper deals with the dynamic range testing of an ADC using the SoC resources. A novel method to generate the test signal which is used to characterize the ADC has been proposed. The BIST controller ensures coherent sampling by synchronizing the clock and the frequency control word thereby effective dynamic characterization of the ADC is ensured.

An n-bit ADC under test requires a DAC with a resolution of at least n+2 bits [Kerzerho et al, (2008)]. As the resolution of the proposed DDFS and the DAC is 11 bits, the dynamic parameters of an 8-bit ADC can be characterized with the proposed design.

Our future work is to extract the harmonics introduced by the DAC

(Hk

DAC) from the measured output spectrum (

Hk

measure

).

References

[1] Chih Jen-Chuan, Chou Jun-Yei and Chen Sau-Gee (2001) “An Efficient Direct Digital Frequency Synthesizer based on Two-level Table Lookup”. IEEE International Frequency Control Symposium and PDA Exhibition.

[2] Dai Foster Fa, Stroud Foster Fa, and Yang Dayu (2006)“Automatic Linearity and Frequency Response Tests with Built-in Pattern Generator and Analyzer”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 14, NO. 6.

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[4] Essenwanger Kenneth .A., Reinhardt Victor.S. (1998) “Sine Output DDSs A Survey Of The State Of The Art”, IEEE International Frequency Control Symposium.

[5] Hai Usman, Nadir Khan Muhammad, Saad Imran Muhammad, Rehan Muhammad (2005), Electronics Dept , NED UEET “Compressed ROM High Speed Direct Digital Frequency Synthesizer Architecture”.

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[8] Kester WaltandSheingold Dan, “Testing Data Converters”.

[9] Lin-hui Lai, Xiao-jin Li, Zong – sheng Lai (2008) , East China Normal University, Shanghai 200062, P. R. China “A Low-Complexity Direct Digital Frequency Synthesizer”.

[10] Vankka.J. (1997), “Methods of mapping from phase to sine amplitude in direct digital frequency synthesis,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 44, no. 2, pp. 526–534.

[11] Vankka.J. and Halonen.K. (2001) “Direct Digital Synthesizers: Theory, Design and Applications”. Norwell, MA: Kluwer. [12] Yang Dayu, Foster Dai and Charles Stroud (2005) “Built-In Self-Test for Automatic Analog Frequency Response Measurement”. [13] Yi Shu-Chung, Lee Kun-Tse, Chen Jin-Jia, Lin Chien-Hung (2006) , NCUE, Changhua, Taiwan 500,ROC, “A low-power efficient direct

TEST BENCH FOR DYNAMIC RANGE TESTING OF ADC