Comparison of Modulation Techniques for
Multilevel Inverter fed Permanent Magnet
Synchronous Motor
V. NAGA BHASKAR REDDY Dept. of EEE, RGMCET, Nandyal, Andhra Pradesh, India; +91-518501
CH.SAI BABU
Dept. of EEE, JNTUA, Anantapur, Andhra Pradesh, India; +91-533001
S.NAGARAJA RAO Dept. of EEE, RGMCET, Nandyal, Andhra Pradesh, India; +91-518501
Abstract — Multilevel inversion is a power conversion strategy in which the output voltage is obtained in steps thus bringing the output closer to a sine wave and reduces the Total Harmonic Distortion. Multilevel inverter structures have been developed to overcome shortcomings in solid-state switching device ratings so that they can be applied to higher voltage systems. In recent years, the multilevel inverters have drawn tremendous interest in the area of high-power medium-voltage energy control. Three different topologies have been proposed for multilevel inverters like Diode-Clamped Inverter, Capacitor Clamped Inverter and Cascaded Multi cell Inverter. In addition, several modulation and control strategies have been developed or adopted for multilevel inverters including the following multilevel Sinusoidal Pulse Width Modulation (SPWM), and Space Vector Modulation. In this paper, simulation of various modulating techniques i.e., Pulse Width Modulate techniques such as Sinusoidal PWM, Trapezoidal PWM, Stepped PWM, Stair case PWM, third harmonic injected PWM, Modified SVPWM are applied for both Diode Clamped Three-Level Inverter and Diode Clamped Five-Level Inverter, and Space Vector PWM technique are analyzed for DC3LI. The best modulation technique are extended to Permanent Magnet Synchronous Motor.
Keywords : Diode-Clamped Multilevel inverters, Modified Space Vector Modulation, Multilevel carrier signals, Multilevel concept, Permanent Magnet Synchronous Motor. Pulse width modulation, Space Vector Modulation, Total Harmonic Distortion.
I. Introduction
Inversion is the conversion of DC power to AC power at a desired output voltage or current and frequency. A static semiconductor inverter circuit performs this electrical energy inverting transformation. The terms voltage-fed and current-fed are used in connection with the output from inverter circuits. A Voltage Source Inverter (VSI) is one in which the DC input voltage is essentially constant and independent of the load current drawn. The inverter specifies the load voltage while the drawn current shape is dictated by the load.The DC power input to the inverter is obtained from an existing power supply network (or) from a rotating alternator through a rectifier (or) a battery, fuel cell, photo voltage array (or) Magneto Hydro Dynamic (MHD) generator.
Inverters are mainly classified as Voltage Source Inverters (VSI), and Current Source Inverters (CSI). A VSI is one in which the DC source has small or negligible impedance. In other words, a VSI has stiff DC voltage source at its terminals. Because of low internal impedance, the terminal voltage of a VSI remains substantially constant with variations in load. It is therefore equally suitable to single motor and multi-motor drives. Any short circuit across its terminals causes current to rise very fast, due to the low time constant of its internal impedance. The fault current cannot be regulated by current control and must be cleared by fast acting fused links.
2. Diode Clamped Multilevel Inverters
The most commonly used multilevel topology is the DCMLI [1], in which the diode is used as the clamping device to clamp the DC bus voltage so as to achieve steps in the output voltages.
2.1 Diode Clamped Three-Level Inverter (DC3LI):
Table 1. Switching Sequence for Diode Clamped Three- Level Inverter
Fig. 1 Configuration of DC3LI for a single leg
2.2 Diode Clamped Five-Level Inverter (DC5LI):
A DC5LI is shown in Fig. 2. In this circuit the DC bus consists of four capacitors, C1, C2, C3, and C4. For DC
bus voltage, the voltage across each capacitor is Vdc and each device voltage series will be limited to one
capacitor voltage level through clamping diodes. To explain how the staircase voltage is synthesized, the neutral point n is considered as the output phase voltage reference point.
Fig. 2 Configuration of Diode Clamped Five-Level Inverter for a single leg
Table 2 Switching Sequence for Diode Clamped Five-Level Inverter 2.2.1 Advantages of DC MLI:
Output voltage
Switching sequence S1 S2 S1' S2'
0 0 0 0 0
Vdc/2 1 1 0 0
- Vdc/2 0 0 1 1
Output voltage
Switching sequence
S1 S2 S3 S4 S1' S2' S3' S4'
0 0 0 1 1 1 1 0 0
Vdc/4 0 1 1 1 1 0 0 0
Vdc/2 1 1 1 1 0 0 0 0
- Vdc/4 0 0 0 1 1 1 1 0
Inverter efficiency is high because all devices are switched at the fundamental frequency The control method is relatively simple.
3. Modulation Techniques
In general for a PWM techniques two signals are needed i.e., one is reference signal and other is carrier signal. For this chapter the reference signal is going to modify, where as carrier is going to be as triangular wave. Some of the different modified reference signals are as follows.
SinusoidalPulse width modulation Trapezoidal PWM.
Stepped PWM Stair case PWM. Harmonic injected PWM Space vector PWM
Modified Space vector PWM
3.1 Sinusoidal Pulse Width Modulation (SPWM):
In sinusoidalPWM instead of maintaining the width of all pulses the same as in the case of multiple PWM, the width of each is varied in proportion to the amplitude of a sine wave evaluated at the same pulse. The distortion is reduced significantly compared to multiple PWM.
Fig 3 Sinusoidal pulse width modulation
3.2 Trapezoidal Pulse Width Modulation:
In this technique the gate signals are generated by comparing a triangular carrier wave with a modulating Trapezoidal wave as shown in fig 4.
3.3 Staircase Pulse width Modulation :
Fig 5 Staircase modulation
This is an optimized PWM and is not recommended for fewer than 15 pulses in one cycle. It has been shown that for high fundamental output voltage and low distortion factor. The optimum number of pulses in one cycle is 15 for two levels, 21 for three levels and 27 for four levels. This type of control provides a high quality output voltage with a fundamental value of up to 0.94 Vs.
3.4 Stepped modulation :
The modulating signal is a stepped wave as shown in fig 3.4. The stepped wave is not a sampled approximation to the sine wave. It is divided into specified intervals, say 20°, with each interval controlled individually to control the magnitude of the fundamental component and to eliminate specific harmonics. This type of control gives low distortion, but higher fundamental amplitude compared with of normal PWM control.
Fig 6. Stepped modulation
3.5 Third harmonic injected PWM :
It is implemented in the same manner, as sinusoidal PWM. The difference is that the reference ac waveform is not sinusoidal but consists of both fundamental component and a third-harmonic component. As a result, the peak –to-peak amplitude of the resulting function does not exceed the dc supply voltage Vs, but the fundamental
component is higher than the available supply voltage Vs.
4. .Space Vector PWM For Three Level Inverter
SVPWM is a digital modulating technique where the objective is to generate, PWM load line voltages that are in average equal to a given reference load line voltages. With PWMs, the inverter can be thought of as three separate push pull driver stages, which create each phase waveform independently.
Fig. 8 . Space Vector hexagon displaying switching states
There are altogether 27 switching states in a DC3LI. They correspond to 19 voltage vectors whose positions are fixed. These space voltage vectors can be classified into four groups. Where we notice the first group corresponds to 03 zero vectors or null vectors (V0, V7, V14), the second group consists of large voltage vectors (V15-V20), the third group consists of medium voltage vectors (V8-V13) and finally the fourth group consist of small voltage vectors (V1-V6). The last three groups can be distinguished into three hexagons which are shown in below Fig. 8.
5. Modified Space Vector PWM
In the SPWM scheme for two-level inverters, each reference phase voltage is compared with the triangular carrier and the individual pole voltages are generated, independent of each other [6]. To obtain the maximum possible peak amplitude of the fundamental phase voltage, in linear modulation, a common mode voltage, Voffset1, is added to the reference phase voltages [9, 1], where the magnitude of Voffset1 is given by
2
)
(
max min1
V
V
V
offset
--- (1)
In (1), Vmax is the maximum magnitude of the three sampled reference phase voltages, while Vmin is the minimum magnitude of the three sampled reference phase voltages, in a sampling interval. The addition of the common mode voltage, Voffset1, results in the active inverter switching vectors being centred in a sampling interval, making the SPWM technique equivalent to the modified reference PWM technique [9].
Fig.10. modified reference with triangular carriers for 3-level inverters
The proposed modified reference PWM technique presents a simple way to determine the time instants at which the three reference phases cross the triangular carriers. These time instants are sorted to find the offset voltage to be added to the reference phase voltages for modified reference PWM generation for multilevel inverters for the entire linear modulation range, so that the middle inverter switching vectors are centred (during a sampling interval), as in the case of the conventional two-level modified reference PWM scheme.
It has been shown that for an n-level inverter, n-1 level-shifted carrier waves are required for comparison with the sinusoidal references [8]. Because of the level-shifted multicarrier as shown in fig (9 & 10), the first crossing (termed the first-cross) of the reference phase voltage cannot always be the min-phase. Similarly, the last crossing (termed the third-cross) of the reference phase voltage cannot always be the max-phase. Thus the offset voltage computation, based on equation(1) is not sufficient to centre the middle inverter switching vectors, in a multilevel PWM scheme during a sampling period Ts.
6. Mathematical Modeling of PMSM
Detailed modeling of interior PMSM drive system is required for proper simulation of the system. The d-q axis model has been developed on rotor reference frame as shown in Fig. 11. At any time t, the rotating rotor d-axis, makes an angle θr with the fixed stator phase axis and rotating stator miff makes an angle α with the rotor d-axis.
Stator mmf rotates at the same speed as that of the rotor [8].
Fig. 11. Motor Axis
The following assumptions are made in the modeling of PMSM 1. Magnetic saturation and frictional coefficient is neglected. 2. The induced emf is sinusoidal.
3. For modeling purposes, the permanent magnets can be considered as fictitious constant current sources. 4. Eddy current and hysteresis losses are neglected.
There is no field or damper winding on the rotor. d q
r d s
d
R
i
p
V
---(2)d d
r q s
q
R
i
p
f d d
d
L
i
---(5) Substituting Eqn. (4) and (5) into (2) and (3)
d d f
q q r d s
d
R
i
L
i
p
L
i
V
---(6)
d d f
q q rq s
q
R
i
L
i
pL
i
V
---(7)Arranging Eqns. (6) and (7) in matrix form
0
p
Ψ
i
i
pL
R
i
L
ω
L
ω
pL
R
V
V
f q d q s d d r q r d s q dThe developed electromagnetic torque in motor is given by
d q q d
e
i
i
2
P
2
3
T
---(8) The mechanical torque equation isdt
d
J
T
T
m L e
---(9)Solving for the rotor mechanical speed from above Eqn.
dt
J
T
T
e Lm
P
2
r m7. Simulation results for 3-level & 5-level DCMLI
7.1 Harmonic Injected Pulse Width Modulation
Fig. 12. Line Voltage of DC5LI with Third Fig. 13. THD spectrum of DC5LI with Third Harmonic Injected PWM Harmonic Injected PWM
In this modulation technique Fig. 12 shows the Line Voltage of DC5LI with Third Harmonic Injected PWM and Fig. 13 shows the THD spectrum of DC5LI with Third Harmonic Injected PWM, in this modulation technique the fundamental voltage is 339.7 V and THD is 10.18%.
Fig. 14. Line Voltage of DC5LI with Modified Fig 15. THD spectrum of DC5LI with Modified space vector PWM Space Vector PWM
In this modulation technique Fig. 14 shows the Line Voltage of DC5LI with MSVPWMand Fig. 15 shows the THD spectrum of DC5LI with MSVPWM, in this modulation technique the fundamental voltage is 345.1 V and THD is 10.15%.
Modified Space Vector PWM Technique for a Three-Phase DC5LI fed with PMSM
Fig. 16 Speed waveform of PMSM with DC5LI with step loadTL=4 N-m
Fig.17 Torque waveform of PMSM with DC5LI with step loadTL=4
Comparison of THD and fundamental component for DC3LI and DC5LI :
Input voltage for 3-level inverter = 400V Input voltage for 5-level inverter = 400V Switching frequency = 5000 Hz
MODULATI ON TECHNIQUE
S
DC3LI DC5LI
THD
Fundam ental Compon
ent
THD
Funda mental Compo nent Sinusoidal
PWM 29.89% 233.3 V 13.20% 332.3 V
Trapezoidal
PWM 27.66% 246.9 V 12.75% 334.7 V
Stepped
PWM 27.01% 253.0 V 11.61% 336.4 V
Stair case
PWM 26.07% 277.3 V 10.37% 338.6 V
Harmonic
injected PWM 24.52% 300.5 V 10.18% 339.7 V
SVPWM 23.20% 312.7 V ---- ----
Modified
SVPWM 23.14% 311.8 V 10.15% 345.1 V
Table 3 Comparison of THD and fundamental componentfor DC3LI and DC5LI
8. Conclusion
Diode Clamped Multi-Level Inverter topologies developed for 3-level and 5-level and by comparison. It is concluded that the performance of DC5LI is good. Hence it is chosen to use in the further work.
Various modulation techniques i.e., Sinusoidal PWM, Trapezoidal PWM, Stepped PWM, Stair case PWM, third harmonic injected PWM, Space Vector PWM, and Offset voltage injected Sinusoidal reference PWM are implemented for DC3LI and DC5LI topology. By comparison it is concluded that DC5LI with MSVPWM has given the good performance of 10.15 as %THD and fundamental component as 345.1 V.
Finally PMSM is chosen to feed from the proposed DC5LI with MSVPWM. A model for PMSM is developed by using MATLAB/SIMULINK. The results for a load of 4 N-m obtained and THD in stator current obtained as 3.87% and fundamental component as 15.98 A.
9. References
[1] J. S. Lai and F. Z. Peng, “Multilevel converters–A new breed of power converters”, IEEE Trans. Ind. Applicat., vol. 32, pp. 509–517, May/June 1996
[2] Leon M.Tolbert and Thomas G.Habetler “Novel Multilevel Inverter Carrier- Based PWM Method” IEEE Trans. Ind. Applicat., vol. 35, pp. 1098–1107, Sep/Oct 1999.
[3] Brendan Peter McGrath, Donland Grahame Holmes and Thomas Lipo “Optimized Space Vector Switching Sequence for Multilevel Inverters” IEEE Trans. Power Elecrtonics., vol. 14, No. 6 pp. 1293–1301, Nov 2003.
[4] Holtz J “Pulse width modulation- A survey”, IEEE Trans. Ind. Electron., 1992. Vol 30 No. 5 pp 410-420.
[5] S.R Bowes and G.S.Singh, “ Novel space-vector based harmonic elimination inverter control” IEEE Trans. Ind. Applicat., vol. 36 No. 2 , pp. 142–150, Mar/Apr 1988.
[6] Ahmad Radan and Zahra Daneshi Far “Optimization Opportunities in carrier-based Multilevel PWM using Degrees of freedom of modulation”.
[7] K. Taniguchi and H. Irie, “Trapezoidal modulating signal for three-phase PWM inverter”, IEEE Trans. on Industrial Electronics, Vol.IE3, No2, 1986, pp. 193-200.
[8] John C. Salmon, Oisen and Nelson Durdle “A Three-Phase PWM Strategy using Stepped Reference waveform” IEEE Trans. Ind. Applicat., vol. 27 No. 5 , pp. 914–920, Sep/Oct 1991.
[9] Baiju, M.R., Gopakumar, K., Somasekhar, V.T., Mohapatra, K.K., and Umanand, L.: ‘A space vector based PWMmethod using only the instantaneous amplitudes of reference phase voltages inverters’, IEEE, Trans. Ind. Appl 2005, pp. 297–309.
[10] K. Thorborg and A. Nystorm, “Staircase PWM: an uncomplicated and efficient modulation technique for ac motor drives”, IEEE Trans. on Power Electronics, Vol. PE3, No.4, 1988, pp. 391-398.
