ADVANCED CMOS DEVICES AND RELIABILITY

ADVANCED CMOS DEVICES AND RELIABILITY

BEN KACZER

UFRGS 2013 Tutorial

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

BTI

time

strain USJ

silicide

>130 90-65-45 ^Strain, USJ (F,C co-implant, …)

Performance

22-15

FinFET

Multi-gate 45-32/28

High-k, Metal Gate

FUSI

Gate-first

Gate-last

??

Ge/IIIV

III-V, CNT, VFET

TFET, NW, graphene…

nanowires

Tunnel FET

<15

VFET

SCALING ROADMAP : VARIETY OF

ARCHITECTURES ON THE HORIZON

EXPLOSION OF MATERIAL AND DEVICE TECHNOLOGY OPTIONS

Ge/III-V Strain

Metal gates FinFET

High k

HP -Logi c LP -Logi c Fl ash -FG

DRAM RRAM Fl ash -CT

POWER SUPPLY VOLTAGE EVOLUTION

0.00 1.00 2.00 3.00 4.00 5.00 6.00

0.01 0.10

1.00 10.00

Su pp ly v ol ta ge ( V)

Gate length ( µ m)

Power supply voltage is saturating at about 1V due to non-scaling of subthreshold slope

Constant voltage

Constant voltage

ELECTRIC FIELDS IN OXIDE AND IN SILICON INCREASE

Third scaling period: renewed constant voltage scaling due to non- scaling subthreshold slope has new implications on reliability !

1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08

0.01 0.10

1.00 10.00

E lec tr ic field ( V /c m )

Gate length (um)

Eox Esi

70-80’s 90’s 00’s

POWER DENSITY INCREASES DUE TO NON-SCALING SUBTHRESHOLD SLOPE

Power density will soon be dominated by static power !

leak dd

stat

eff swing

dd dyn

I V P

: Static

f C

V V

P : Dynamic

⋅

=

⋅

⋅

⋅

⋅ α

=

Almost all reliability problems are accelerated by Temperature !

D. Cox, IRPS Tutorial 2004

NO TWO IDENTICALLY FABRICATED TRANSISTORS ARE ALIKE ANYMORE

These time-zero variations require adaptations in circuit design to account for statistical spread in device parameters

The established simulation

paradigm

Physical gate length 22nm

Physical gate length 9nm = 30x30x30

atoms

100

Asenov et al., IEDM 2008 σV_T ~ 1/(WL)^1/2

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

BTI

Reliability is an essential aspect of all products and technologies

IS RELIABILITY IMPORTANT ?

WHY RELIABILITY TESTING

As fabricated

Record performance!

Insufficient reliability: field returns, loss of profit, credibility, market share...

Devices cannot be tested for years (corresponding to field use)

 accelerated testing needed!

V

_D

I

D

E.g., a month later

Performance degraded!

V

_D

I

D

ACCELERATED TESTING (IN FEOL)

TYPICALLY DONE WITH V AND/OR T

Operating conditions Accelerated conditions

Log t im e- to -fa ilur e 10 years

Correct projection to operating conditions only possible if

 same mechanism at accelerated and operating conditions

 acceleration laws understood!

STOCHASTIC NATURE OF RELIABILITY MECHANISMS:

A FRACTION OF DEVICES WILL FAIL!

Operating conditions Accelerated conditions

Log t im e- to -fa ilur e

10 years

Again, the distribution can be correctly described only if underlying mechanism understood!

As dimensions get smaller,

distributions become wider

(courtesy of T. Grasser)

RELIABILITY MUST BE PART OF EVERY (TECHNOLOGY) SPECIFICATION!

Example:

1 out of 10,000 chips (100ppm) allowed to fail in

10 years at operating conditions.

“CLASSICAL” APPROACH TO RELIABILITY ASSESSMENT

failure data statistics

develop predictive reliability models accelerated

testing/model

reliability test structures failure

mechanisms

Reliability engineer Designer

 Novel approaches needed to design reliable circuits with

unreliable components: Reliability Aware Design (RAD)

RELIABILITY AND RECENT CMOS FEOL TRENDS

• New (3D) device architectures

• New “exotic” materials (high-k gate dielectrics, metal gates, high-mobility substrates)

• Downscaling of devices toward atomic dimensions (variability)

• Supply voltages are not correspondingly reduced

 Reexamination of known “old” degradation mechanisms in new materials and architectures required

 Revision of existing and need for novel characterization techniques

 New reliability lifetime assessment methodologies

 Reliability cannot be guaranteed at technology level:

Reliability-Aware Design

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

BTI

TIME-DEPENDENT DIELECTRIC BREAKDOWN (TDDB)

Electrical stress = Additional gate oxide leakage paths (TDDB) + FET intrinsic parameters change (“BTI”)

G

S D

W

G

S D

W

G

S D

W

G

S D

W

G

S D

W

1 2

3 5

1 2 3 4 5

wear-out

4

10 ^-14 10 ^-12 10 ^-10 10 ^-8 10 ^-6 10 ^-4

5 4

3 2

1 0

Gate Voltage (V)

Fresh SILC

SBD HBD

CHANNEL HOT CARRIER (CHC) DEGRADATION

h

e

hole current

Electrons and/or holes in the channel of a MOSFET gain high energy under influence of large electrical fields in the Si at the drain. They are injected into the oxide causing interface traps to be created and charges to be trapped in the oxide

Bravaix et al., IRPS 2009

POSITIVE / NEGATIVE BIAS TEMPERATURE INSTABILITY (BTI)

0 5 10 15 20 25

0 500 1000 1500 2000

time (s) - ∆ V

th

( m V)

T = 125

^o

C V

_G,stress

= -2 V V

_G,relax

= 0 V

stress relaxation 0V

0V V

_G

0V

Example: PFET at Negative gate Bias (and typically at elevated T emperature) pFET V

_th

starts shifting (shows Instability)  NBTI Charging of interface and oxide defects  ∆V

_th

and ∆ μ

0.0 0.2 0.4 0.6 0.8 1.0

6 8 10 12 14 16 18

|V G-V th| [V]

T_{inv (≈EOT+4Å)} [Å]

EOT = 1nm

SiGe

Franco et al., IEDM 2010

ITRS

Critical issue in sub 1 nm oxides

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

• Overview / Phases of BD

• SILC

• SBD & impact of position

• Wear-out and HBD

BTI

V

Gate

Si substrate

(GIST OF) GATE OXIDE BREAKDOWN

I

t t

BD

D. R. Wolters, Ph.D. Thesis, 1985

40 nm SiO

₂

Gate oxide breakdown =

catastrophic failure

PHASES OF GATE DIELECTRIC BREAKDOWN

Electrical stress = Additional gate oxide leakage paths (TDDB) + FET intrinsic parameters change (“BTI”)

G

S D

W

G

S D

W

G

S D

W

G

S D

W

G

S D

W

1 2

3 5

1 2 3 4 5

wear-out

4

10 ^-14 10 ^-12 10 ^-10 10 ^-8 10 ^-6 10 ^-4

5 4

3 2

1 0

Gate Voltage (V)

Fresh SILC

SBD HBD

Crupiet al., TED 1998

SINGLE TRAP CONDUCTION PATH

Additional leakage path = Trap-assisted tunneling with energy loss

(Takagi et al., TED 46(2), 1999).

This is Stress-Induced Leakage Current = SILC.

e

^-

V

_G

n

⁺

-type gate

p-type substrate

dielectric

1 0^{- 1 1}

2 4

1 0^{- 1 0}

2 4

1 0^{- 9}

2 4

1 0^{- 8}

1 0^{1 5} 1 0^{1 6} 1 0^{1 7} 1 0^{1 8} 1 0^{1 9}

p . D_{o t} [ c m^{- 3}]

Ielmini et al., TED 49 (11), 2002

• Steady-state SILC increase is

proportional to neutral oxide trap density

• Trap near the middle between interfaces

= highest conductivity

De Blauwe et al., TED 45(8), 1998

TWO COMPENSATING TRENDS IN ULTRA-THIN OXIDE SILC

Trend 1: trap generation rate drastically drops (figure)

▸ Less conductive paths through the oxide

Trend 2: conductivity per trap increases drastically

▸ Tunnel distance decreases and current rises exponentially

▸ Each trap contributes more to the total SILC

Stathiset al., IEDM 1998

T rap gener at ion ra te

THE CHANGING APPEARANCE OF SILC

SILC

time

many small contributions

oxide gate

substrate e^-

SILC

time

few large contributions

oxide gate substrate e^-

Capacitor top view

SILC and individual

trap components

Capacitor cross section

SILC

time

many small contributions

SILC

time

many small contributions

oxide gate

substrate e^-

oxide gate

substrate e^-

SILC

time

few large contributions

SILC

time

few large contributions

oxide gate substrate e^-

oxide gate substrate e^-

Capacitor top view

SILC and individual

trap components

Capacitor cross section

Thick / large device Thin / small device

Abrupt current increase of about 250nA

= creation of single trap conduction path

= ‘discrete’ SILC event

This is NOT a breakdown

TWO-TRAP CONDUCTION PATH

Percolation path with trap-assisted tunneling

▸ this is Anomalous Stress-Induced Leakage Current = a-SILC (non- volatile memories) (Okada et al., IEDM 2001, Degraeve et al., IEDM 2001) In thick oxide: moving bits in flash memory

▸ this is Micro-Breakdown (Cellere et al., TED 49(8), 2002) or pre- Breakdown (Degraeve et al., IEDM 2001)

2-trap path

capacitor top view e

^-

V

_G

n

⁺

-type gate

p-type substrate

dielectric

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

• Overview / Phases of BD

• SILC

• SBD & impact of position

• Wear-out and HBD

BTI

CONDUCTION PATH = SOFT BREAKDOWN

= SMALL GATE CURRENT INCREASE

• 1

^st

SBD observation (in 2 nm SiO

₂

):

Farmer et al., APL 52, p. 1749 (1988)

• Localized current flow through lowered barrier

• Model: ‘quantum point contact’

Suñé, IEDM 2000

• This is a soft breakdown, aka quasi-BD (

Lee, IEDM 1994

), partial BD, B-mode

SILC (

Okada, VLSI 1997

).

e

^-

V

_G

n

⁺

-type gate

p-type substrate

dielectric

<1 %-step detection mandatory in automatic tester or, use smaller areas

or, use a noise-based detection (

Roussel et al., TDMR 1(2), 2001

)

11.4x10^-6 11.2 11.0 10.8 10.6 10.4 10.2 10.0

gate current (A)

30 25

20 15

10 5

0

time (s) 2 percent

5 percent

soft breakdown

nmos transistor L x W = 1 x 100 µm² V_g = 4.4 V

t_ox =2.4 nm

0 40 80 120

0 0.5 1.0 1.5

V

_D

(V) I

D

( µ A)

G

S D

W

W

_eff

= 120 nm

V

_G

= 0, 0.15 .. 1.5 V

NO SIGNIFICANT EFFECT ON FET

CHARACTERISTICS AT THE MOMENT OF SBD

Kaczer et al., IRPS, p. 79 (2004)

Already in

Weir et al., IEDM, p. 73 (1997)

Circuits will generally work after SBD!

Gerrer et al., ESSCIRC 2009

TIME-TO-SOFT BREAKDOWN =

STATISTICALLY DISTRIBUTED PARAMETER

Time-to-breakdown is Weibull distributed

Monomodal Weibull distribution is described as:

( )

^⇒

(

⁻

(

⁻

) )

^{= β}

( )

^−β

( )

^η















 





− η

−

=

β

ln t

ln F

1 ln t ln

exp 1

t F

-4 -3 -2 -1 0 1

ln(-ln(1-F))

10

2 3 4 5 6 7

100

2 3 4 5 6 7

1000 t_BD (s)

V_G=4.4V

A=1.5e-08cm² T=298C

EOT=2.4nm

η=63%-value β=slope

-5 -4 -3 -2 -1 0 1

ln(-ln(1-F))

0.01

2 4 6 8

0.1

2 4 6 8

1 normalized Q _BD

4.6 11

t_ox= 2.4 nm 7.5

3.4

-5 -4 -3 -2 -1 0 1

ln(-ln(1-F))

0.01

2 4 6 8

0.1

2 4 6 8

1 normalized Q _BD

4.6 11

t_ox= 2.4 nm 7.5

3.4

-5 -4 -3 -2 -1 0 1

ln(-ln(1-F))

-5 -4 -3 -2 -1 0 1

ln(-ln(1-F))

0.01

2 4 6 8

0.1

2 4 6 8

1 normalized Q _BD

4.6

4.6 1111 7.5 t_ox= 2.4 nm 7.5

t_ox= 2.4 nm

3.4 3.4

dt t J Q_BD ⁼

∫

0^tBD _G( )

TDDB STATISTICAL DISTRIBUTION IS LINKED TO NUMBER OF TRAPS IN PERCOLATION PATH

Weibull slope increases with oxide thickness  can be used to identify the breaking layer in a multilayer (high-k) stack

Not very precise or decisive for thin layers Very indirect monitor

14 12 10 8 6 4 2 0

Weibull slope

12 10

8 6

4 2

0

Physical layer thickness (nm) SiO₂

CVS with V_G > 0 V

Thick oxide

Thin oxide

DETERMINATION OF THE MAXIMUM APPLICABLE GATE VOLTAGE

Combined effect of temperature acceleration and statistical scaling (depends on β!) This extrapolation is only valid for soft breakdown

Voltage power-law more accurate than exponential also in high-k

Wu & Suñe, TED 2009

Soft BD

Degraeveet al., VLSI 1999

Temperature 0.6 V percentile

~0.3 V area

~0.25 V 10 years

G

S D

W

G

S D

W G

S D

W

0 L x

s is a monotonically increasing function of x.

R. Degraeve, IRPS (2001)

0 < s < 1

s ≅ 0 s ≅ 1

IMPACT OF BREAKDOWN POSITION ON FET

— PRINCIPLE OF POSITION DETERMINATION

D S

D

I I

s I

≡ +

Evaluate after BD in accumulation

Wu et al., IEDM, p. 187 (1998) Pompl et al., IRPS, p.82 (1999) Yang et al., IEDM, p.453 (1999)

EQUIVALENT ELECTRICAL CIRCUIT FOR FET AFTER BD

S D

W G

F_S

R_path

B_S

F_D B_D

F

F

_S

, F

_D

gate lengths, B

_S

, B

_D

base lengths a function of BD position

R

_path

independent of BD position G

S D

W

Explains varying FET behavior following BD

Kaczer et al., TED 49, p. 507 (2002)

OTHER USES OF BD POSITION DETERMINATION

FinFETs:

Crupi et al., TED 53, p. 2351 (2006)

Non-uniform oxide stress:

Crupi et al., EDL 24, p. 278 (2003)

Processing issues:

Kauerauf et al., SISC (2004)

Uniformity of GOX stress in accumulation and inversion:

Crupi et al., TDMR 3, p. 8 (2003)

Impact of BD position on BD wear-out:

Pey et al., IRPS, p. 221 (2007)

Also

B. Linder et al., IRPS, p. 403 (2003)

Correlation of successive BD’s and 1 and 2D:

Alam et al., p. 151, IEDM 2002; p. 415, IEDM2005;

TED 55, p. 3150 (2008)

These 2 cases are equivalent in 1D

x x

east south

west north

gate bulk

1 μm

Kaczeret al., IPFA 2007

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

• Overview / Phases of BD

• SILC

• SBD & impact of position

• Wear-out and HBD

BTI

CONDUCTION PATH + THERMAL DAMAGE

= HARD BREAKDOWN

Mass transport and Si regrowth in the breakdown spot

Lei Jun Tang et al., TDMR 4(1), 2004

Localized current flow through resistor (+diode)

Kaczer et al., TED 49(3) 2002

V

_G

n

⁺

-type gate

p-type substrate

dielectric

capacitor top view

hard breakdown

PHASES OF DEGRADATION AND WEAR OUT IN THIN OXIDES

1. SBD: Weibull ( β

_SBD

, η

_SBD

)

2. Wearout: assume Weibull ( β

_wo

, η

_wo

)

3. Runaway

HBD

R

_S

-limited

DETAILED STRUCTURE OF THE WEAR OUT PHASE

In some cases the wear out phase is clearly observable by the increased ‘digital’ noise (Digital Breakdown)

J.S. Suehle et al., IRPS 2004

Kaczer et al., IEDM 2004

0 500 1000

10⁰ 10¹ 10² 10³ 10⁴

t

_rs

(s)

gate current (A)

• Analog breakdown rate increases with lower R

_s

(e.g. in Metal gates)

• Can be “arrested” by limited current supply (e.g. from previous stage)

ln(10)

( ) log( ) ^g ... log( )_rs ( _g)

s s

I t t V C t D V

a R R

= + + ≡ +

Alam et al., IEDM 2000; Linder et al., VLSI 2001; Monsieur et al., IRPS 2003;

Kaczer et al., IRPS 2004

HARDNESS OF BREAKDOWN

DEPENDS ON GATE ELECTRODE

Post-BD current through BD path depends on gate material Gate current run-away is positive feed back process

controlled by electron ‘supply’ in the gate

metal gate  hard BD

poly-Si gate  soft BD

Duschl et al., IRPS, p. 632 (2005).

-3 -2 -1 0 1

ln (-l n (1 -F ))

1

2 4 6

10

2 4 6

100

2 4 6

1000 time-to-breakdown (s)

V

_G

=2.2V

0.9 nm EOT SiO

₂

/HfO

₂

A=1.25e-09cm

²

HBD β

_HBD

=~1.2 SBD β

_SBD

=~0.7

HBD IS NOT WEIBULL DISTRIBUTED!

If HBD is fitted with Weibull, β will be too high  erroneous conclusions can be drawn

TDDB data meaningful if BD detection criterion given

t With limited data, hard breakdown resembles I

Weibull distribution

Degraeve et al., IRPS 2006 Kerber et al., IRPS 2007

virgin device 1^st SBD

COMPETING FOR HBD: A TRIATHLON …

 In statistics described by series rule of reliability

2^nd SBD 3^rd SBD

1^st HBD

 faster swimmer can be overtaken by even faster biker!

time

SBD HBD

ST AR T

_Winner

competitor 1

competitor 2

P. J. Roussel et al., Microelectron. Eng. 84, 1925 (2007)

ALL-IN-ONE RELIABILITY PREDICTION

Region 1 = breakdown-free

Region 2 = multiple soft breakdown

▸ Contours = relative leakage current increase DI/I

₀

after 10 years

▸ NOTE: current increase for individual small transistor can be substantial!

Region 3 = Hard breakdown (taking multiple SBD into account)

▸ Contours = lifetime for 0.01% failures

0.001

2 4 6

0.01

2 4 6

0.1

Area (cm2 )

1.4 1.3

1.2 1.1

1.0

Voltage (V) 10

8.4 77

s =1 0 y

ear s

10 s 8

10 s 7

10 s 6

10 s5

10 s 4

Region 3 Region 1

Region 2

3x10-6 10-43x10-5

10-5

0.001

2 4 6

0.01

2 4 6

0.1

Area (cm2 )

1.4 1.3

1.2 1.1

1.0

Voltage (V) 10

8.4 77

s =1 0 y

ear s

10 s 8

10 s 7

10 s 6

10 s5

10 s 4

Region 3 Region 1

Region 2

3x10-6 10-43x10-5

10-5

SiO

₂

/HfO

₂

EOT=0.9 nm

Sahhaf et al., IEDM 2007

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

BTI

• Overview / BTI components

• Technological remedies

• NBTI recoverable component and AC stress

• BTI in deeply scaled devices

• Observing properties of individual defects

• Impact of individual defects on FET characteristics

• Constructing and projecting ∆V_th distributions

• Combining time-dependent and time-0 variabilities

• Defect-centric circuit simulation framework

BIAS AND TEMPERATURE STRESS:

TYPICAL DURING FET OPERATION

V

_DD

0V V

_DD

0 5 10 15 20 25

0 500 1000 1500 2000

time (s) - ∆ V

th

( mV )

T = 125

^o

C V

_G,stress

= -2 V

0V

0V negative V

_G

0V

Example: PFET V

_th

at Negative gate Bias (and typically at elevated T emperature) starts shifting (shows Instability)  NBTI

Charging of interface and oxide defects  ∆V

_th

and ∆ μ

NBTI (pFET) PBTI (nFET)

Positive oxide charge (negative V

_th

shift)

Negative oxide charge (positive V

_th

shift) Interface states

(mobility, transconductance, subthreshold-slope degradation)

Mahapatra, IEDM 2003 Mitani et al., ECS 2005 Garros et al., ICICDT 2010

X

(but observed in sub 1nm EOT)

Generally at substrate interface Generally trapping in high-k

BTI: CHARGED OXIDE BULK AND INTERFACE STATES

Zafar et al., VLSI 2006 Mahapatra, TDMR 2007

Kerber et al., TED 55, 3175 (2008) Aoulaiche et al., IRPS 2009

EXAMPLE OF BTI LIFETIME EXTRAPOLATION

▸ Failure Criterion: ∆ V

_th

= 30mV at T = 125

^◦

C

▸ Minimized relaxation: t

sense_delay

= 2ms

▸ Stress experiment at different voltages (V

_Gstress

> V

_DD

)  Estimate lifetime  Power Law extrapolation at 10 Years

V_Gstress-V_th0=-1.25V

BTI IS A SERIOUS RELIABILITY PROBLEM

Ultra-Thin EOT high-k gate stacks with overdrive below the required 0.7V for 10 years

nMOS - PBTI pMOS - NBTI

1.4 1.2 1.0 0.8 0.6 0.4 0.2 PBTI Vg overdrive at 10years (V) 0.0

1.6 1.2

0.8 0.4

0.0

EOT (nm) Hf-based

GdHfO Zr-based

target: 0.7V

1.4 1.2 1.0 0.8 0.6 0.4 0.2 NBTI Vg overdrive at 10years (V) 0.0

1.6 1.2

0.8 0.4

0.0

EOT (nm) target: 0.7V

Si substrate

Courtesy of Cho and Franco, imec

“MINOR” COMPLICATION: THRESHOLD VOLTAGE SHIFT STARTS RELAXING IMMEDIATELY AFTER STRESS REMOVED

0 5 10 15 20 25

0 500 1000 1500 2000

time (s)

∆ V

th

( m V)

T = 125

^o

C V

_G,stress

= -2 V V

_G,relax

= 0 V stress relaxation

Crucial issue for all BTI measurements and interpretation!

Observed in p/nFETs, P/NBTI, DC and AC stress...

Alam, IEDM 2003; Kerber et al., TED 2008; Kaczer et al., IRPS 2008

BTI DEGRADATION RELAXES “DISPERSIVELY” OVER MANY TIME SCALES: µSECONDS OR LESS TO DAYS

10

^-3

10

^-1

10

¹

10

³

10

⁵

relaxation time t

_relax

(s)

“DC” MSM Fast MSM

Ultra-Fast MSM On-the-fly

Extended MSM

 Different measurement techniques to attack the problem

MSM = Measure- Stress- Measure

10

^-5

degr adat ion ∆ V

th

RELAXATION INCOMPLETE:

PERMANENT DEGRADATION

0 10 20 30 40 50

10

^-3

10

^-1

10

¹

10

³

10

⁵

relaxation time t

_relax

(s)

∆ V

th

( m V)

“Permanent”

R(t

_stress

, t

_relax

) R (

t stress,

t

relax

= 0)

1.4 nm SiON pFET t

_stress

= 100 s T = 125

^o

C

Most common interpretation:

Relaxation component – discharging of oxide defects Permanent component – generated interface states

se e

Ranganet al., IRPS 2003

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

BTI

• Overview / BTI components

• Technological remedies

• NBTI recoverable component and AC stress

• BTI in deeply scaled devices

• Observing properties of individual defects

• Impact of individual defects on FET characteristics

• Constructing and projecting ∆V_th distributions

• Combining time-dependent and time-0 variabilities

• Defect-centric circuit simulation framework

PBTI CONTROLLED BY CHARGE TRAPPING IN HIGH-K

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

1

E

_ox

(MV cm

^-1

) Δ V

th

( V)

2 5 10

ref La

ref La

T = 125 ^oC t_relax = 10^-3 s lines: t_stress = 10 years symbols: t_stress = 6x10³ s

• Group III elements compensate unpaired electrons around oxygen vacancy in HfO

₂

• Similar effect caused by N (

Xiong & Robertson, JAP 2006; Sahhaf et al., EDL 2010

)

Kaczeret al., INFOS 2009

Reference

With La

Liu and Robertson, APL 2009

Significant reduction of PBTI is observed in nFETs with Lanthanum V

_Th0

-adjusting layer

SIGE PFETS WITH BURIED CHANNEL PROMISE SUPERIOR PERFORMANCE OVER SI

∆E_V

Si SiGe Si SiO HfO MG

To reduce NBTI:

• Increase Ge fraction

• Increase QW thickness

• Reduce Si cap thickness

^Franc

o et al., IRPS 2010, IEDM 2010Mitardet al., IEDM 2010

64

0 0.2 0.4 0.6 0.8 1 1.2 1.4

6 8 10 12 14 16 18

Max.

|V

G

-V

th

|

for 10Y

[V]

T

_inv

[Å]

Ultra-Thin EOT

0 1 2 3 4 5 6 7 8 9

6 8 10 12 14 16 18

Max.

E

oxfor 10Y

[M V/ c m ]

T

_inv

[Å]

THIN Si CAP IMPROVES NBTI LIFETIME WHILE SCALING T

_INV

▸ Enables T

_inv

scaling while improving NBTI reliability

▸ Same trend consistently observed on SiGe, Ultra-Thin EOT SiGe, and pure Ge channels

Si cap thinner

thicker

0.65nm 1nm

1.3nm

2nm

Si cap thinner

thicker

0.65nm

1.3nm 2nm

SiGe

1nm

Si

0.6nm 1nm

1.7nm 0.6nm

1nm

1.7nm

J. Franco et al. IEDM 2010

64

Thin Si cap: channel carriers (E

_F

) ‘miss’ part of the oxide defects

SiGe  LOWER ∆N

_OT

MODEL: REDUCED INTERACTION WITH OXIDE DEFECTS

SiGe Si SiO₂ HfO₂ Si

E

_F

E

_VS

MG

▸ Less defects, located on the gate side, are energetically favorable for holes

▸ Stronger field acceleration due to ‘unaccessible’ traps becoming ‘accessible’

R ↓

J. Franco et al. IEDM 2011

Thick Si cap: channel carriers (E

_F

) ‘see’ all the oxide defects

E

_F

E

_VS

SiGe Si SiO₂ HfO₂

Si MG

SiGe  LOWER ∆N

_OT

MODEL: REDUCED INTERACTION WITH OXIDE DEFECTS

▸ Less defects, located on the gate side, are energetically favorable for holes

▸ Stronger field acceleration due to ‘unaccessible’ traps becoming ‘accessible’

R ↓

J. Franco et al. IEDM 2011

UNIFIED PICTURE: THE ENERGY ALIGNMENT BETWEEN CARRIER AND OXIDE DEFECTS

CONTROLS BTI MECHANISMS

▸ nMOSFET PBTI: improved reliability shifting up the defect energy level by inserting Gd (Dy, La) in the high-k

▸ pMOSFET NBTI: improved reliability shifting up the

channel Fermi level by using a (Si)Ge channel

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

BTI

• Overview / BTI components

• Technological remedies

• NBTI recoverable component and AC stress

• BTI in deeply scaled devices

• Observing properties of individual defects

• Impact of individual defects on FET characteristics

• Constructing and projecting ∆V_th distributions

• Combining time-dependent and time-0 variabilities

• Defect-centric circuit simulation framework

COMMON PROPERTY OF NBTI RELAXATION (RATE) AND LOW-F (“1/F”) NOISE:

STATES WITH WIDELY DISTRIBUTED TIME SCALES

t

_stress

= 100 s V

_stress

= -2V T = 125

^o

C

0 10 20 30 40 50 60 70

10^-3 10^-1 10¹ 10³ 10⁵

t

_relax

(s) Δ V

th

(m V)

10^-8 10^-6 10^-4 10^-2 10⁰

-d Δ V

th

/ d t (Vs

-1

)

10^-16 10^-15 10^-14 10^-13 10^-12 10^-11 10^-10 10^-9

10⁰ 10¹ 10² 10³ 10⁴ 10⁵

frequency (Hz) S

VG

(V

2

Hz

-1

)

SiON T = 25 ^oC unstressed

V_G = -0.3 V

V_G = -0.6 V

NBTI relaxation & rate low-f noise (same device)

Both 1/f noise and R component higher in nitrided oxides

Kapila et al., IEDM 2008; Kaczer et al., IRPS 2009

… …

LEARNING FROM NOISE: TWO ATTRIBUTES ESSENTIAL FOR CAPTURING BTI RELAXATION BEHAVIOR

C = 10

⁰

... 10

^N

C = 10

⁰

... 10

^N

low-f noise

(1) Many time scales  distributed RC components

NBTI relaxation

(1) + (2) Different charging (capture) and discharging (emission) of each state

Kaczeret al., IRPS 2008, 2009

capture time constant (s)

emission time constant (s) Reisinger et al., IRPS 2010

PFET AC NBTI: (FAST) SEQUENCE OF STRESS AND RELAX PHASES

0 10 20 30 40 50

10

⁰

10

²

10

⁴

10

⁶

10

⁸

10

¹⁰

frequency (Hz) Δ V

th

( m V)

DC

T = 125 C

t

_stress

= 1000 s

V

_S

= V

_D

= V

_B

= V

_cc

= 2 V

AC NBTI:

V

_select

= 2 V DC NBTI:

V

_select

= 0 V V

_G

= 0 V

AC degradation ~ DC degradation / 2.

• AC BTI degradation lower than DC

• appears f-independent up to GHz

|V_G|

t ^{stress relax stress relax}

…

Zhu et al., IRW 2002 Abadeer, IRPS 2003 Alam, IEDM 2003 Chakravarthi et al., IRPS 2004 Fernandez et al., IEDM 2006

0 20 40 60 80 100

0 20 40 60 80 100

Duty Factor

Δ V

th

= R (t

relax

) + P (m V)

_V

stress = -2.0V f_stress = 10 kHz t_stress = 6000 s

t_relax = 10^-3 ( ), 10^-2, … , 10⁴ s T = 125 ^oC

relaxation

DISTINCTIVE SHAPE OF AC NBTI Δ V

_TH

DEPENDENCE ON STRESS DUTY FACTOR

• Shape with “plateau” due to recoverable component

• Correct model must reproduce this shape

DC

DUTY FACTOR DEPENDENCE OF THE RECOVERABLE COMPONENT REPRODUCED BY EQUIVALENT CIRCUIT

Kaczer et al., IRPS 2008

0 1 2 3 4 5 6 7

0 20 40 60 80 100

Duty Factor R(t relax, t stress= 6000) (a.u.)

V_stress = 1 a.u.

t_relax = 10^-3, 10^-2, … , 10⁴a.u.

relaxation

Experiment Equivalent circuit simulation

• Distinctive shape of Duty Factor dependence cannot be explained by the classical Reaction-Diffusion model

• The shape is controlled by the recoverable component

0 20 40 60 80 100

0 20 40 60 80 100

Duty Factor ΔVth= R(trelax) + P (mV)

V_stress= -2.0V f_stress= 10 kHz t_stress= 6000 s

t_relax= 10^-3 ( ), 10^-2, … , 10⁴s T= 125 ^oC

relaxation

DC

OUTLINE

CMOS FEOL trends Why reliability

Examples of FET degradation mechanisms TDDB

BTI

• Overview / BTI components

• Technological remedies

• NBTI recoverable component and AC stress

• BTI in deeply scaled devices

• Observing properties of individual defects

• Impact of individual defects on FET characteristics

• Constructing and projecting ∆V_th distributions

• Combining time-dependent and time-0 variabilities

• Defect-centric circuit simulation framework

DEEPLY-SCALED DEVICE OPERATION IS AFFECTED BY INDIVIDUAL DEFECTS

In deeply-downscaled technologies, only a handful of random defects will be present in each device

N

_ot

= 10

¹²

cm

^-2

 N

_T

~ 10 if device area = 10 x 100 nm

²

Courtesy of M. Bina, TUWien

Number of charged defects will be increasing with operating time

 time-dependent variability in addition to time-0 variability

BEN KACZER, IMEC BEN KACZER, IMEC

INDIVIDUAL DEFECTS RESULT IN TIME-DEPENDENT VARIABILITY

78

• Individual defects behave stochastically

• Individual defects have considerable relative impact on device

• These time-dependent variations require adaptations in circuit design to account for time-dependent statistical distributions of device

parameters

Large devices

Large Transistor 280 x 720 nm²

N

_T

= 800 traps

Lifetime

Grasser et al., IEDM 2010

(c)

lifetime (s)

Occurrence

Lifetime

Small device 35 x 90 nm²

N

_T

= 12 traps

Lifetime

DEEPLY SCALED DEVICES: INDIVIDUAL EMISSION EVENTS VISIBLE IN NBTI RELAXATION TRACES

relaxation time -Δ V

th

( m V)

10^-3 10^-1 10¹ 10³ 10⁵

Large pFET

[Asenov]

0 10 20 30 40 50 60

relaxation time (s) -Δ V

th

( m V)

10^-3 10^-1 10¹

70 × 90 nm

²

pFET

…

τ

_n-1

τ

₁

τ

₂

τ

_n-2

τ

_n

Kaczeret al., IRPS 2009

IN GENERAL, EACH DEFECT CHARACTERIZED BY

• capture time τ

_c

• emission time τ

_e

• impact on device (∆I

_d

or ∆V

_th,

...)

• occupancy (0 or 1) at given time

(covers BTI, RTN, ... easily extensible to other mechanisms)

(size of bubble represents impact)

Example: defects in 3 different devices

τ

e

(V, T) τ

c

( V , T )

τ

e

(V, T) τ

c

( V , T )

τ

e

(V, T) τ

c

( V , T )

EACH DEVICE CHARACTERIZED BY

• number of defects N

_T

with above properties

Depend on

• spatial position

• energy position

• lattice relax. energy

• ...

Kaczer et al., IRPS 2011

EXTENDED MEASURE-STRESS-MEASURE (eMSM):

EFFICIENT WAY OF OBSERVING MOST DEFECTS

~ log stress time degr adat ion (~ to ta l Δ V

th

)

Example: 3 deeply-scaled devices

~ log relaxation time degr adat ion (~ to ta l Δ V

th

)

τ

e

(V

_L

, T) τ

c

( V

H

, T )

τ

e

(V

_L

, T) τ

c

( V

H

, T )

τ

e

(V

_L

, T)

τ

c

( V

H

, T ) t

_stress

t

_relax

NBTI AND RTN: TWO SIDES OF THE SAME COIN

Random Telegraph Noise (steady-state)

NBTI relaxation transient (perturbation/non-steady-state)

S

^{+ + + + + +}

D

+ + +

+

0 10 20 30 40

10^-3 10^-2 10^-1 10⁰

-Δ V

th

(mV )

time (s) t

_stress

= 1900 s

10¹ 10² 10³

+ + + + +

+ + +

S D

-15 -10 -5 0 5 10 15

0 100 200 300 400

time (s) t

_stress

= 0 s

Δ V

th

(mV )

B. Kaczer et al., IRPS 2009 & 2010