32 aula

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Interface Hardware-Software

Aula 3-2

Arithmetic & Logical Instructions

Prof. Dr. Stefan Michael Blawid sblawid@cin.ufpe.br

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Tópicos

1) Arithmetic Instructions 2) Logical Instructions

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Status flags

Six flags in the FLAGS register are used to monitor the outcome of the arithmetic, logical, and related operations:

Zero flag (ZF) indicates a zero result

Carry flag (CF) indicates an result that is out of range assuming unsigned numbers

Overflow flag (OF) indicates an result that is out of range assuming signed numbers

Sign flag (SF) indicates a negative sign of the result

Auxiliary flag (AF) indicates an result that has generated a carry out of or a borrow into the low-order four bits

Parity flag (PF) indicates even parity of the lower eight result bits Conditional branch instructions my alter the program flow

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Tópicos

1) Arithmetic Instructions

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The

ADD/SUB Instructions

Add without carry; Syntax: add dest, src

Integer addition. The result (dest + src) is assigned to dest Subtract; Syntax: sub dest, src

Integer subtraction. The result (dest - src) is assigned to dest The following combinations are possible:

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The

INC/DEC Instructions

Increment by 1; Syntax: inc dest Decrement by 1; Syntax: dec dest The carry flag is not affected

Better than using add/sub because inc/dec are instructions that take up less memory (1 byte = 40H for inc AX instead of 3 bytes = 050100H for add AX 0x0001)

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The

CMP Instruction

Compare two operands; Syntax: cmp dest, src

Compares the two operands specified by performing dest-src Only the flags are updated to reflect the result of the subtract operation

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The

CMPXCHG Instruction

Compare and Exchange; Syntax: cmpxchg dest, src

Compares the value in the AL, AX, or EAX register (depending on the size of the operand) with dest:

If the two values are equal: dest ← src Otherwise: AL, AX or EAX ← src

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More about

CMPXCHG

This instruction was created only starting with the 486 processor Allows atomic comparison and exchange of values by setting the prefix byte accordingly

Example: Consider the following two apparently “identical” code fragments. Is there a difference? Yes, in the first version, an

interrupt might occur between the execution of cmp and mov

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The

MUL Instruction

Unsigned multiplication; Syntax: mul src

src is a general-purpose register or a memory location

The destination operand is an implied operand located in register AL, AX or EAX (depending on the size of the operand)

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The

IMUL Instruction

Signed multiplication; Syntax:

imul src

imul dest, src

imul dest, src, immediate

The one-operand format works similar as the mul instruction (but for signed multiplication)

The two-operand format performs dest ← dest × src. dest is a 16- or 32-bit general purpose register and src is is an immediate value, a general-purpose register, or a memory location.

The three-operand format performs dest ← src × immediate.

dest is a 16- or 32-bit general purpose register and src is is a general-purpose register, or a memory location.

Obs: For the multiple-operands formats the result of the signed multiplication is of the same length as the input operands

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The

DIV/IDIV Instructions

Unsigned divide; Syntax: div src Signed divide; Syntax: idiv src

src is a general-purpose register or a memory location

-2^7 to 2^7 -1 -2^15 to 2^15 -1

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The

NEG Instruction

Negate sign (two’s complement); Syntax: neg dest Replaces the value of dest with its two's complement

dest is a general-purpose register or a memory location Examples:

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The

CBW/CWD/CWDE/CDQ Instructions

Convert Byte to Word; Syntax: cbw Convert Word to Doubleword: cwde

Both instructions have the same opcode. Which one is executed depends on the operand-size attribute

Doubles the size of the operand in register AL (AX) by sign extension and stores the result in registers AX (EAX)

Convert Word to Doubleword: cwd

Convert Doubleword to Quadword: cdq

Both instructions have the same opcode. Which one is executed depends on the operand-size attribute.

Doubles the size of the operand in register AX (EAX) by sign extension and stores the result in registers DX:AX (EDX:EAX) Useful for preparing operands before a mul or div

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Tópicos

1) Arithmetic Instructions

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The

NOT Instruction

Logical bitwise not; Syntax: not dest One’s complement negation

The dest operand can be a register or a memory location Examples:

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The

AND/OR/XOR Instructions

Logical bitwise and; Syntax: and dest, src Logical bitwise or; Syntax: or dest, src

Logical bitwise exclusive-or; Syntax: xor dest, src

Performs the logical operation on the dest (first) and src (second) operands and stores the result in the dest operand location

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The

TEST Instruction

Logical compare; Syntax: test dest, src

Computes the bit-wise logical “dest AND src” and sets the SF, ZF, and PF status flags according to the result. The result is discarded. The following combinations are possible:

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Example

Code that tests whether a number is odd or even (assuming a register DX value of 0x0000 or 0x0001 for the Assembly code):

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The

BSF/BSR Instructions

Bit scan forward; Syntax: bfs dest, src Bit scan reverse; Syntax: bsr dest, src

Scans the bits in src. The ZF flag is set if all bits are 0 and dest is undefined; otherwise, ZF is cleared and the dest register is loaded with the bit index of the first set bit.

bfs starts the scan with the least significant bit and bsr with the

most significant bit.

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The

BT Instructions

Bit test; Syntax: bt scr1, src2

The value of the bit in src1, whose position is indicated by src2, is saved in the carry flag

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The

BTC/BTR/BTS Instructions

Bit test and complement; Syntax: btc src1, scr2 Bit test and reset; Syntax: btr src1, scr2

Bit test and set; Syntax: bts src1, scr2

The value of the bit in src1, whose position is indicated by src2, is saved in the carry flag and then …

… the bit in src1 is complemented (btc)

… the bit in src1 is reset (i.e., cleared) (btr) … the bit in src1 is set (i.e., stores 1) (bts)

src1 is a 16/32 register or memory location; src2 is a 16/32 register or an 8-bit immediate

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The

SETcc Instruction

Set byte on condition; Syntax: setCC dest

Sets dest byte to 1 if the condition CC is met; otherwise, sets to 0

dest must be 8-bit register or memory location

The conditions CC are A, AE, B, BE, C, E, G, GE, L, LE, O, P, S, Z, NA, NAE, NB, NBE, NC, NE, NG, NGE, NL, NLE, NO, NP, NS, NZ, PE, PO

The conditions can specify signed and unsigned comparisons as well as flag values

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