ALL OPTICAL 3-BIT SERIAL INPUT SHIFT REGISTER DESIGN

ALL OPTICAL 3-BIT SERIAL INPUT

SHIFT REGISTER DESIGN

VIKRANT K SRIVASTAVA*

Electronics & Instrumentation Department Indian School of Mines

Dhanbad 826 004 ,INDIA.

DEVENDRA CHACK

Electronics & Instrumentation Department Indian School of Mines

Dhanbad 826 004 ,INDIA.

VISHNU PRIYE

Electronics & Instrumentation Department Indian School of Mines

Dhanbad 826 004, INDIA.

Abstract:

In this Paper, we present all-optical shift Register logic with complete Boolean functionality as a representative circuit for modeling and optimization of monolithically integrated components. Proposed optical logic unit is based on nonlinear effects in semiconductor optical amplifiers (SOA). We show a strategy of optical pulse propagation in SOA based on coupled nonlinear equations describing XGM and FWM effects. These equations are first solved to generate the pump, probe and conjugate pulses in a SOA. The pulse behavior are analyzed and applied to realize behavior of all-optical NAND gate. Next, the logic is used to implement All-Optical Flip-Flop logic, and its function is verified with the help of truth table. Finally with the help of three Flip Flop a 3-bit shift register is proposed. The full design is simple, compact, economical, thermally stable and integration capable.

Key words: Shift Register, Optical Logic Gates, Semiconductor Optical Amplifier, SOA, four wave mixing, cross gain modulation, cross phase modulation

1. Introduction:

One common requirement in digital circuit is storing binary information. A register might be used to accept input data from an alphanumeric keyboard and then present this data at the input of a microprocessor chip. Similarly, registers are often used to momentarily store binary data at the output of a decoder. A binary register also forms the basis for some very important arithmetic operations such as the operation of complementation. Multiplication and division are frequently implemented by means of a register. A shift register can also be connected to form number of different type of counters [1].

The design carried out in this paper is by means of semiconductor optical amplifiers (SOA). As we know SOA is integration capable, compact, and thermally stable [2]. Various nonlinearities in SOAs including cross gain modulation (XGM), four wave mixing (FWM), and cross phase modulation (XPM), have been exploited for implementing optical gates. The gate operation can scale with data rate and they have some more properties like data regeneration, gain, cascadability and implementing more complex operation than possible with a simple switch [3]. A new approach is discussed in the following paper. This approach include utilization of nonlinear properties of SOA in the development of optical logic gates which are further used in building all-optical Flip-Flops and all Optical Register respectively.

2. Simulation Method:

The following Equation has been taken into consideration [7].

(2.1)

Where A0(0, t), input pump pulse amplitude at any end of SOA, A0(L, t), input pump pulse amplitude at length L of

SOA,L= length of SOA, t=time .Rest parameters are defined in TABLE I.

(2.2)

Where A1 (0, t), input probe pulse amplitude at any end of SOA, A1 (L, t), input probe pulse amplitude at length L of

SOA, L= length of SOA, t=time .Rest parameters are defined in TABLE I.

(2.3)

Where A2(0, t), input conjugate pulse amplitude at any end of SOA, A2(L, t), input conjugate pulse amplitude at

length L of SOA, L= length of SOA, t=time .Rest parameters are defined in TABLE I.

The amplification function h and coupling coefficient ij are defined in [6]. All other typical parameters related with

InGaAsP Semiconductors and used for quantitative evaluation are listed in Table I.

Table 1 Parameters used in simulation work

Parameters Symbol Values Units

Length of amplifier L 450



Width of active region W 1.5



Depth of active region d 0.3



Traditional confinement factor



Small signal gain g0 1.54*10^-4 m-1

Saturation power Psat 28.4 mW

Carrier lifetime



Nonlinear gain compression for carrier heating



Nonlinear gain compression for spectral hole burning



Traditional Line width enhancement factor



Temperature Line width enhancement factor



Line width enhancement factor for spectral hole burning



Time for carrier carrier scattering



Time for carrier photon scattering



Carrier depletion coefficient



3. Result and Discussion

Pump, Probe and Conjugate signal pulses obtained with the help of above equations in MATLAB Environment are used to explain the response of Optical NAND Gate. The basic idea to realize all optical NAND Gate has been taken from [7].

In SOA1 Pump ‘A’ saturates the gain of probe ‘clock’, resulting in conjugate of Pump ‘A’. Also in SOA2, Pump ‘B’ saturates the gain of Probe ‘A’, which inverts the signal ‘B’ and on multiplication with ‘A’ result in, product of ‘A’ and inverted ‘B’ signal. The resulting signal (the sum of outputs of SOA1 and SOA2 will result a NAND output, which can be verified with the help of waveforms and truth tables-1.

Fig 1 NAND Gate using SOA’s Truth table 1 NAND Gate

This clearly indicates the NAND Logic.

Waveform 1 Input A of NAND Gate taken as [1 0 1 0]

The above waveform show that according to the truth table when values of input A and B are taken as [1 0 1 0] and [1 0 1 1] respectively, the on applying clock as [1 1 1 1] the final output of waveform is [0 1 0 1], which clearly verifies the truth table of NAND gate. During time interval [0 1] the inputs A and B are (1 ,1) respectively. So output is ‘0’ accordingly. During time interval [1 2] the inputs A and B are (0,0) respectively. So output is ‘1’ accordingly. During time interval [3 4] the inputs A and B are (0 ,1) respectively. So output is ‘1’ accordingly. This clearly verifies NAND Logic.

A general logic of J-K Flip-Flop is developed (Fig-2, Fig-3) using the logic of NAND Gate, discussed above. For NAND1 and NAND3 Gate, Pump and Probe pulse is selected. Output of NAND1 and NAND3 will act as input of NAND2 and NAND4 respectively. By proper selection of pump and probe pulses J-K Flip –Flop can be realized.

Now in our approach in designing a Flip Flop circuit, all three input NAND gate of Fig 2, is firstly converted into a two input NAND gate. The following figure (Fig 4) is the logic circuit of a Flip–Flop with 2-input NAND Gates. NAND1 and NAND2 gates can be used to make 3-input NAND gates. Similarly NAND5 and NAND6 are also used to make 3-input NAND gate.

Fig-4 Design of flip flop using NAND Gates

Again each NAND Gate is created with the help of SOA’s. Output at each end of different SOA can be tested and verified with the help of waveform. The complete design of Flip Flop with SOA’s is represented in Fig-5 shown below.

Fig-5 Design of flip flop using 14 number of SOA’s

In Fig-5 Connection between SOA 1 and SOA 2 explains circuit of NAND 1. SOA 3 explains one input NAND 2. NAND 3 can be represented as combination of SOA 4 and SOA 5. SOA 6 and SOA 7 are used to represent NAND 4. Similarly SOA 13 and SOA 14 in Fig-5 show construction of NAND 5. One input NAND 6 can be made with SOA 12. (SOA 10, SOA 11) and (SOA 8, SOA 9) represents NAND 7 and NAND 8 respectively. Proper labeling is done in Fig-5 to explain the different inputs used for simulation. Results are verified with the help of waveform-8, which results from simulation. In the waveform-8 shown below HOLD represent that in the selection of inputs J and K as active low, the outputs (Q) holds the state as it was in the previous state. Toggle state can be obtained when both J and K are taken as active high. When J is taken as active high and K as active low the output (Q) is active high. And finally when J is active low and K is active high the output (Q) is active low.Waveform-6 shows that when we take input J=[1 0 1 1] and Waveform-4 shows that when we take input  =[1 0 1 0] (As in Fig 4 ,input of NAND 1), The output is Q=[0 1 0 1] (As in Fig-4 ,output of NAND 4,and also in waveform-7).This verifies one output of Flip Flop. The other output can be verified similarly.

Waveform-5 Input clock of flip flop taken as [1 1 1 1]

Waveform-6 input J of flip flop taken as [1 0 1 1]

Waveform-8 Output of a flip flop with different values of input

Waveform-8 shows all the verified result of full flip flop.During set state the output of flip flop is logic ‘1’, During reset state the output of flip flop is logic ‘0’, During hold state the output of flip flop is same as that of applied input and During toggle state the output of flip flop is toggle of the applied input.

Now to make Register logic we need three such Flip Flops. As we have seen that a Flip Flop circuit requires 14 SOA’s. Hence Register logic requires total 42 SOA’s. The outputs of each flip flops are connected as shown in figure below.

Fig-6 Proposed Design of a 3 bit serial input Shift Register using flip flop

At clock time t1 a “data in” of 0 is clocked from J to Q of all three stages. In particular , J of stage A sees a logic 0,

which is clocked to QA where it remains until time t2.

At clock time t2 a “data in” of 1 is clocked from J to QA. At stage B and C, a 0, fed from preceding stages is clocked

to QB and QC.

At clock time t3 a “data in” of 0 is clocked from J to QA. QA goes low and stays low for the remaining clocks due

to”data in” being 0. QB goes high at t3 due to a 1 from the previous stage .

QC finally goes high at clock t4 due to the high fed to D from the previous stage QB. All earlier stages have 0s shifted

into them. And, after the next clock pulse at t5, all logic 1s will have been shifted out, replaced by 0s.

Thus in this way a serial input serial output shift register is verified.

4. Conclusions

In this paper, using analytical solutions of nonlinear effects in InGaAsP semiconductor optical amplifier, we have shown that with high input pump power generated conjugate pulses can be utilized to generate different digital logic. Based on these logic first of all the operation of all optical Universal NAND gate and JK Flip Flop is verified and a 3 bit register is proposed.

References

[1] From Wikipedia, the free encyclopedia

[2] B. Dagens, et al. SOA-based devices for all-optical signal processing. 2003.

[3].Nema Elfaramawy,Amira Awad Electrical Engineering Department, Faculty of Engineering, Alexandria University, Alexandria, Egypt, 0-7803-8623-X/04/$20.00@2004 IEEE.

[4] Martin T. Hill,1 H. de Waardt,1 G. D. Khoe,1 and H. J. S. Dorren, Department of Electrical Engineering Eindhoven University of Technology, 5600 MB Eindhoven, The Netherlands

[5] M.T. Hill, H. de Waardt, G.D. Khoe, and H.J.S. Dorren, All optical flip-flop based on coupled laser diodes, IEEE J Quantum Electron 37Ž2001, 405_413.

[6] S junqlang et al.,”Analytical solution of four wave mixing between picosecond optical pulses in semiconductor optical amplifiers with cross gain modulation and probe depletion”,Microwave and Optical Technology Letters,Vol. 28,No.1,pp78-82,2001.

[7] 2005 Quantum Electronics and Laser Science Conference (QELS), All-optical NAND gate using cross gain modulation in semiconductor optical amplifiers, Sang H. Kim', J. H. Kim 1,2, J. W. Choi, Y. T. Byun', Y. M. Jhon', S. Lee', D. H. Wool, S. H. Kim',