Institute of Informatics – UFRGS
Carla Freitas (Dean)!
Luciano Gaspary (Deputy Dean) !
direcao@inf.ufrgs.br !
• Founded in 1934
(first schools date back to 1895)
• Ranked the best Federal University by the Ministry of Education 1
• Ranked among the 10 top universities in Latin America by the Times Higher Education
• ≈ 2,950 faculty members 2 , 90% PhDs
UFRGS numbers
• 658 CNPq Fellowships 3
(advanced research fellowships)
1 As of November 2017 2 As of July 2018 3 As of March 2018
• Undergraduate studies
– 78 undergraduate programs
– ≈ 28,500 undergraduate students 1
UFRGS numbers
• Graduate studies
– ≈12,100 graduate students 2 – 90 graduate programs (81 PhD
programs 3 )
1 As of September 2017 2 As of December 2017 3 As of March 2018
20 18 25
Graduate programs, as ranked by CAPES (Dec 2017)
– 42% of the graduate programs are level 6 and 7
– 63 % are at levels 5, 6 or 7
• One of the largest CS institutes in Brazil
• 72 faculty members
• 31 staff members
• Excellent infrastructure
– 10 labs (for classes)
– 40 labs (research groups) – Clusters
Institute of Informatics (INF)
Applied Informatics
Dept.
UFRGS
Institute of INF
Informatics
Incubator
Theoretical Informatics
Dept. CEI
Academic
Sectors Projects and
Accounting IT Support
Administrative Management
• 72 faculty members
• Graduated in several highly ranked institutions
– Brazil, France, Germany, United Kingdom, USA, Canada, Belgium,
Switzerland, Portugal, Sweden, Italy
• Post-docs
– USA, France, Germany, United Kingdom, Canada, Netherlands, Belgium, Denmark, Italy
Institute of Informatics (INF)
• Undergraduate courses
– Computer Science – Computer Engineering
– Ranked among the best in Brazil – ≈ 970 students 1
Institute of Informatics (INF)
1 As of May 2018
CS & CE
Undergraduate Courses
UFRGS
Institute of INF
Informatics
• Undergraduate courses
– Computer Science – Computer Engineering
– Ranked among the best in Brazil – ≈ 970 students 1
• Graduate programs !
– PPGC
– PGMICRO
• With Physics, Engineering and Chemistry
– PGIE
• With (and at) Faculty of Education
Institute of Informatics (INF)
1 As of May 2018
CS & CE
Undergraduate Courses
UFRGS
Institute of INF
Informatics
PPGC
Graduate Program in Computer
Science
PGMicro
Graduate Program
in Microeletronics
• Undergraduate courses
– Computer Science – Computer Engineering
– Ranked among the best in Brazil – ≈ 970 students 1
• PPGC:
– Origin in 1973
– Awarded the highest grade by the Ministry of Education – Ranked by CAPES among the
top 7 programs in CS in Brazil – Currently: > 200 students (PhD
and MSc Research)
– Graduated over 320 PhD and 1,570 MSc students *
Institute of Informatics (INF) and PPGC
CS & CE
Undergraduate Courses
UFRGS
Institute of INF
Informatics
PPGC
Graduate Program in Computer
Science
PGMicro
Graduate Program
in Microeletronics
Research areas
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
Research areas
Computer graphics Data visualization Image processing Computer vision Pattern recognition
Human-computer interaction Virtual reality
Augmented reality
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
Research areas
Software engineering Data mining
Data integration Data analysis Data modeling
Business process modeling
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
Research areas
Design of integrated circuits and systems Tools for design automation
Reliability and fault tolerance
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
Research areas
High-performance computing
Non-conventional architectures
Embedded systems
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
Research areas
Algorithms and optimization
Logic and Computation models
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
Research areas
Machine learning
Knowledge representation Planning
Multiagent systems
Robotics
• Visual computing
• Data science and
Software engineering
• Design of electronic and computational systems
• Computing systems
• Theory of computation
• Artificial intelligence
• Computer networks
Research areas
Architecture and protocols
Network management
Services management
Cybersecurity
Scientific contribution: top venues
Spectral Remapping for Image Downscaling EDUARDO S. L. GASTAL,Instituto de Informática – UFRGS MANUEL M. OLIVEIRA,Instituto de Informática – UFRGS
(a)Lanczos (b)Öztireli and Gross 2015
(c)Weber et al. 2016 (d)Our Spectral Remapping Fig. 1. Comparison of various image-downscaling techniques. (le�) Reference image. (right) Downscaling to180⇥144pixels performed with: (a) Lanczos filtering followed by resampling using a cubic B-Spline causes structured high-frequency details from the pants, scarf, books, and most of the table cloth to be removed. (b) The technique by Öztireli and Gross introduces aliasing artifacts in those regions. (c) The technique of Weber et al. removes most of these high-frequency details, but still exhibits aliasing (e.g., see books). (d) By remapping high frequencies to the representable range of the downsampled spectrum, our approach retains the structured details. The green plots under the images are the intensity values of the highlighted pixels. The light-blue envelopes show the horizontally-compressed plot of the reference image. “Barbara” test image a�ributed to Allen Gersho (public domain). Please zoom in to see the details.
We present an image downscaling technique capable of appropriately repre- senting high-frequency structured patterns. Our method breaks conventional wisdom in sampling theory—instead of discarding high-frequency informa- tion to avoid aliasing, it controls aliasing by remapping such information to the representable range of the downsampled spectrum. The resulting images provide more faithful representations of their original counterparts, retain- ing visually-important details that would otherwise be lost. Our technique can be used with any resampling method and works for both natural and synthetic images. We demonstrate its e�ectiveness on a large number of Author’s e-mails: {eslgastal,oliveira}@inf.ufrgs.br.
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©2017 Copyright held by the owner/author(s). Publication rights licensed to Association for Computing Machinery.
0730-0301/2017/7-ART145 $15.00 https://doi.org/10.1145/3072959.3073670
images downscaled in combination with various resampling strategies. By providing an alternative solution for a long-standing problem, our method opens up new possibilities for image processing.
CCS Concepts:•Computing methodologies→Image processing;
Additional Key Words and Phrases: Image downscaling, spectral remapping, frequency remapping, antialiasing, resampling, signal processing.
ACM Reference format:
Eduardo S. L. Gastal and Manuel M. Oliveira. 2017. Spectral Remapping for Image Downscaling.ACM Trans. Graph.36, 4, Article 145 (July 2017), 16 pages.
https://doi.org/10.1145/3072959.3073670 1 INTRODUCTION
Image downscaling is one of the most prevalent image-processing operations. It is present, for instance, when we (pre-)view images on the displays of smartphones and digital cameras, or browse photo collections. Unfortunately, some spatial frequencies found in the ACM Transactions on Graphics, Vol. 36, No. 4, Article 145. Publication date: July 2017.
ACM SIGGRAPH ACM TOG 2017
IEEE TRANSACTIONS ON VISUALIZATION AND COMPUTER GRAPHICS VOL. 23, NO. 1, JANUARY 2017 671
Manuscript received 31 Mar. 2016; accepted 1 Aug. 2016. Date of publication 15 Aug. 2016; date of current version 23 Oct. 2016.
For information on obtaining reprints of this article, please send e-mail to:
reprints@ieee.org, and reference the Digital Object Identifier below.
Digital Object Identifier no. 10.1109/TVCG.2016.2598624
1077-2626 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Hashedcubes: Simple, Low Memory, Real-Time Visual Exploration of Big Data
C´ıcero A. L. Pahins, Sean A. Stephens, Carlos Scheidegger, Jo˜ao L. D. Comba
Overview of USA tweets between Nov 2011 and Jun 2012 NYC Green Taxis pick-up Brightkite in Europe Brightkite temporal series Fig. 1. Hashedcubes accelerates queries used in a wide range of interactive exploratory visualizations, such as heatmaps, time series plots, histograms and binned scatterplots, and supports brushing and linking across spatial, categorical and temporal dimensions. In this figure, we show some example visualizations backed by Hashedcubes. The left image shows 210.6 million tweets from November 2011 to June 2012, highlighting the activity during Superbowl XLVI. The central image shows 24.5 million pick-up locations of NYC green taxis rides from January 2014 to June 2015. On the right, the visualizations show different aspects of 4.5 million Brightkite check-ins, a social network. Hashedcubes balances low memory usage, fast running times, and simple implementation; it allows interactive exploration of datasets that previously either required a prohibitive amount of memory or uncomfortably large latencies.
Abstract—We propose Hashedcubes, a data structure that enables real-time visual exploration of large datasets that improves the state of the art by virtue of its low memory requirements, low query latencies, and implementation simplicity. In some instances, Hashedcubes notably requires two orders of magnitude less space than recent data cube visualization proposals. In this paper, we describe the algorithms to build and query Hashedcubes, and how it can drive well-known interactive visualizations such as binned scatterplots, linked histograms and heatmaps. We report memory usage, build time and query latencies for a variety of synthetic and real-world datasets, and find that although sometimes Hashedcubes offers slightly slower querying times to the state of the art, the typical query is answered fast enough to easily sustain a interaction. In datasets with hundreds of millions of elements, only about 2%
of the queries take longer than 40ms. Finally, we discuss the limitations of data structure, potential spacetime tradeoffs, and future research directions.
IndexTerms—Scalability, data cube, multidimensional data, interactive exploration
1 INTRODUCTION
Designers of interactive visualization systems face serious challenges in the presence of large, multidimensional datasets. On one side, naive implementations of repeated linear scans of the dataset of interest no longer offer acceptable latencies: this makes simple data structures no longer attractive. On the other side, sophisticated implementations of precomputed indices built specifically for visualization have been proposed recently. These offer attractive query times, but their imple- mentations are not trivial to integrate with existing systems, require GPU support, or have another similar downside. This paper provides an affirmative answer to the following question: is there a simple data structure that offers much of the performance of the more sophisti- cated indices, while maintaining a relatively-low memory footprint and implementation simplicity?
Specifically, we presentHashedcubes, a novel data structure that enables fast querying for interactive visualizations of large, multidimen-
´ıcero A. L. Pahins and Jo˜
´ { }
{ }
sional, spatiotemporal datasets. Hashedcubes supports spatial queries, such as counting events in a particular spatial region; categorical queries over subsets of attribute values; and temporal queries over intervals of any granularity. As we report on Section 6, a typical query is returned in under 30 milliseconds in single-threaded execution. As a practical matter, Hashedcubes was designed to target the amount of main mem- ory of a modern desktop or laptop personal computer (on the order of 16 to 32GB of main memory). In summary, this paper contributes:
a simple data structure for real-time exploratory visualization of large multidimensional, spatiotemporal datasets, advancing the state of the art especially with respect to implementation simplicity and memory usage,
an experimental validation of a prototype implementation of Hashedcubes, including a suite of experiments to assess query time, memory usage, and build time of the data structure on synthetic and real-world datasets, and an extended discussion of the trade-offs enabled by Hashedcubes, including limitations and open research questions.
2 RELATEDWORK
In this section we will focus on work directly related to interactive visual analysis of big data. For a more comprehensive list of papers, we refer the reader to the surveys on big data analysis [15], big data
IEEE Visualization IEEE TVCG 2017
Design and Evaluation of a Handheld-based 3D User Interface for Collaborative Object Manipulation
Jerˆonimo Gustavo Grandi1 1, Henrique Galvan Debarba23, Luciana Nedel1and Anderson Maciel1 Federal University of Rio Grande do Sul, Institute of Informatics 2´Ecole Polytechnique F´ed´erale de Lausanne, Immersive Interaction Group3
Artanim Foundation, Geneva, Switzerland {jggrandi,nedel,amaciel}@inf.ufrgs.br, henrique.debarba@artanim.ch ABSTRACT
Object manipulation in 3D virtual environments demands a combined coordination of rotations, translations and scales, as well as the camera control to change the user’s viewpoint.
Then, for many manipulation tasks, it would be advantageous to share the interaction complexity among team members.
In this paper we propose a novel 3D manipulation interface based on a collaborative action coordination approach. Our technique explores a smartphone – the touchscreen and inertial sensors – as input interface, enabling several users to collab- oratively manipulate the same virtual object with their own devices. We first assessed our interface design on a docking and an obstacle crossing tasks with teams of two users. Then, we conducted a study with 60 users to understand the influence of group size in collaborative 3D manipulation. We evaluated teams in combinations of one, two, three and four participants.
Experimental results show that teamwork increases accuracy when compared with a single user. The accuracy increase is correlated with the number of individuals in the team and their work division strategy.
ACM Classification Keywords H.5.2. User Interfaces: Input devices and strategies; H.5.3.
Group and Organization Interfaces: Computer-supported co- operative work
Author Keywords
3D User Interfaces; Collaborative Manipulation; User Studies.
INTRODUCTION
The accomplishment of spatial tasks in 3D virtual environ- ments (VE) involves a complex coordination of virtual manip- ulations, such as translation, rotation and scale [27]. Each of these transformations refers to independent degrees of free- dom (DOFs). While these manipulations are fundamental to any 3D virtual environment, performing them freely demands
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org.
CHI 2017, May 6-11, 2017, Denver, CO, USA.
Copyright © 2017 ACM ISBN 978-1-4503-4655-9/17/05 ...$15.00.
http://dx.doi.org/10.1145/3025453.3025935
Figure 1: Three users simultaneously driving the object through the virtual environment. The colored rectangles indi- cate the position and orientation of each user in the VE. The three windows at the right-side show the three personal views.
a highly cognitive effort to coordinate the possible transforma- tions [25]. 3D user interfaces (3DUI) try to reduce the mental overhead by mapping natural gestures and movements into the corresponding action in the VE. However, create effective interfaces for 3D virtual systems is challenging [24]. Many 3DUI techniques have been proposed to allow natural, precise and fast interaction with virtual environments [5]. Techniques are typically designed for specific purpose applications. Some of them have become relatively common due to the easy access to the market, such as gaming console interfaces. Neverthe- less, as of today, research in the 3D object manipulation field mainly focus on single-user interaction.
One alternative towards 3D manipulations efficiency is to share the work and solve the task in a parallel and collaborative man- ner. Collaborators may wish to split the different aspects of the manipulation among them. Thus, perhaps, accomplishing the assignment faster, more accurately and with less fatigue. Team- work, in turn, involves considerable negotiations [6] and, as team members vary, team strategies and task accomplishment processes change as well. Modeling such human interactions raises novel collaborative concepts compared to those typically grounded in a single-user scenario [19]. An effective design of a collaborative 3DUI for virtual environments has to take into account perceptual, cognitive and social issues. Researchers in the social and cognitive field have demonstrated that a wide Spatial Manipulation and Navigation CHI 2017, May 6–11, 2017, Denver, CO, USA
5881
ACM CHI 2017
Improved Heuristic and Tie-Breaking for Optimally Solving Sokoban Andr´e G. Pereira
Federal University of Rio Grande do Sul, Brazil agpereira@inf.ufrgs.br
Robert HolteandJonathan Schaeffer University of Alberta, Canada {holte,jonathan}@cs.ualberta.ca Luciana S. BuriolandMarcus Ritt Federal University of Rio Grande do Sul, Brazil
{buriol,marcus.ritt}@inf.ufrgs.br Abstract
We present a novel admissible pattern database heuristic (D) and tie-breaking rule (L) for Sokoban, allowing us to increase the number of optimally solved standard Sokoban instances from20to28 and the number of proved optimal solutions from 25to32compared to previous methods. The previ- ously best heuristic for Sokoban (I) used the idea of an intermediate goal state to enable the effec- tive use of pattern database heuristics in transporta- tion domains, where the mapping of movable ob- jects to goal locations is not fixed beforehand. We extend this idea to allow the use of multiple in- termediate goal states and show that heuristicI is no longer effective. We solve this problem and show that our heuristicDis effective in this situa- tion. Sokoban is a well-known single-agent search domain characterized by a large branching factor, long solution lengths, and the presence of unsolv- able states. Given the exponential growth in the complexity of standard Sokoban instances, the in- crease in the number of optimally solved instances represents a major advance in our understanding of how to search in extremely large search spaces.
1 Introduction
A single-agent search problem is given by theinitial state, the set ofgoal states(or goal condition) and the set of actions.
Each action defines how to transform a state into a succes- sor state with given cost. A solution is a path from the initial state to a goal state – anoptimal solutionhas minimum cost.
Single-agent heuristic search algorithms such as A⇤[Hartet al., 1968] and Iterative Deepening A⇤[Korf, 1985] use the functionf(u) =g(u) +h(u)to guide the search, where g(u)is the cost to reach the stateufrom the initial state andh(u)is an estimate of the cost to reach a goal state fromu. If the heuristic functionhis admissible these algo- rithms are guaranteed to find an optimal solution. Culberson and Schaeffer [1996] proposed pattern databases (PDB) as a way to generate high-quality admissible heuristics for many single-agent search domains [Korf, 1997; Edelkamp, 2001;
Korf and Felner, 2002; Felneret al., 2004; Holteet al., 2006;
Felneret al., 2007].
Sokoban is a PSPACE-complete [Culberson, 1999] single- agent search domain that is harder to solve than other com- mon search domains considering the branching factor, so- lution length, domain-dependent characteristics and search space size – estimated at1098[Junghanns and Schaeffer, 2001]. In addition, no domain-independent PDB heuristic can optimally solve the easiest instance in the standard test set. Major progress has been made in solving Sokoban non- optimally [Junghanns and Schaeffer, 2001]. Currently, the best non-optimal method solves86[Takahashi, 2016] of the 90standard test set instances [Myers, 2016].
PDB heuristics are ineffective in transportation domains where the mapping of movable objects to goal locations is not fixed beforehand (this is the case in Sokoban). Pereira et al.[2015] introduced an admissible PDB heuristic (I) that addresses this issue by using an intermediate goal state. The heuristicIwith the proposed tie-breaking rule (F) increases from10to20the number of optimality solved instances.
However, the gap in solving abilities between optimal and non-optimal solvers is still wide.
We extend this idea to allow the use of multiple intermedi- ate goal states. However, the heuristicIis the sum of two es- timates which are computed independently. As we will show, the fact they are solved independently makes the heuristic in- effective when using multiple intermediate goal states. In ad- dition, the tie-breaking ruleFis prone to error and can guide the search to parts of the search space that will not lead to an (optimal) solution.
In this paper, we propose a novel PDB heuristic (D) that is effective when using multiple intermediate goal states. We also propose a tie-breaking rule (L) that solves the main lim- itations ofF. Our method increases the number of optimally solved instances from20to28and the number of proved op- timal solutions from25to32. Our heuristic is general and addresses an important limitation of PDB heuristics in a large class of single-agent search domains (i.e., transportation).
2 Background
An instance of Sokoban haskmovable blocks (stones) and kgoal squares placed on a grid-square maze defined by im- movable blocks (walls) and free squares. There is an addi- tional block called themanwhich is the only block that can be moved directly. The man can traverse free squares and Proceedings of the Twenty-Fifth International Joint Conference on Artificial Intelligence (IJCAI-16)
IJCAI 2016
662Experimental and Analytical Study of Xeon Phi Reliability
Daniel OliveiraInstitute of Informatics, UFRGS Porto Alegre, RS, Brazil
Laércio Pilla Department of Informatics and
Statistics, UFSC Florianópolis, SC, Brazil
Nathan DeBardeleben Los Alamos National Laboratory
Los Alamos, NM, US
Sean Blanchard Los Alamos National Laboratory
Los Alamos, NM, US
Heather Quinn Los Alamos National Laboratory
Los Alamos, NM, US
Israel Koren University of Massachusetts, UMass
Amherst, MA, US Philippe Navaux
Institute of Informatics, UFRGS Porto Alegre, RS, Brazil
Paolo Rech Institute of Informatics, UFRGS
Porto Alegre, RS, Brazil ABSTRACT
We present an in-depth analysis of transient faults effects on HPC applications in Intel Xeon Phi processors based on radiation experi- ments and high-level fault injection. Besides measuring the realistic error rates of Xeon Phi, we quantify Silent Data Corruption (SDCs) by correlating the distribution of corrupted elements in the out- put to the application’s characteristics. We evaluate the benefits of imprecise computing for reducing the programs’ error rate. For example, for HotSpot a 0.5% tolerance in the output value reduces the error rate by 85%.
We inject different fault models to analyze the sensitivity of given applications. We show that portions of applications can be graded by different criticalities. For example, faults occurring in the middle of LUD execution, or in the Sort and Tree portions of CLAMR, are more critical than the remaining portions. Mitigation techniques can then be relaxed or hardened based on the criticality of the particular portions.
CCS CONCEPTS
•Computer systems organization→Parallel architectures;
•Hardware→Fault tolerance;
KEYWORDS
Radiation experiments, Fault Injection, Parallel Architectures, Fault Tolerance, Reliability
ACM Reference Format:
Daniel Oliveira, Laércio Pilla, Nathan DeBardeleben, Sean Blanchard, Heather Quinn, Israel Koren, Philippe Navaux, and Paolo Rech. 2017. Experimental and Analytical Study of Xeon Phi Reliability. InProceedings of SC17 .ACM, New York, NY, USA, 12 pages. https://doi.org/10.1145/3126908.3126960
ACM acknowledges that this contribution was authored or co-authored by an employee, contractor, or affiliate of the United States government. As such, the United States government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for government purposes only.
SC17, November 12–17, 2017, Denver, CO, USA
© 2017 Association for Computing Machinery.
ACM ISBN 978-1-4503-5114-0/17/11. . . $15.00 https://doi.org/10.1145/3126908.3126960
1INTRODUCTION
Accelerators are extensively used to expedite calculations in large HPC centers. Tianhe-2, Cori, Trinity, and Oakforest-PACS use Intel Xeon Phiand many other top supercomputers use other forms of accelerators [17]. The main reasons to use accelerators are their high computational capacity, low cost, reduced per-task energy consumption, andflexible development platforms. Unfortunately, accelerators are also extremely likely to experience transient errors as they are built with cutting-edge technology, have very high operation frequencies, and include large amounts of resources.
Reliability has been identified by the U.S. Department of En- ergy (DOE) as one of the ten major challenges for exascale [42].
Errors that may undermine the reliability of an HPC system can come from a variety of sources including environmental perturba- tions,firmware errors, manufacturing process, temperature, and voltage variations [31, 35, 37]. Such errors may corrupt data val- ues or logic operations and lead to Silent Data Corruption (SDC), Detected Uncorrectable Error (DUE), or be masked and cause no observable error [13, 43, 44]. Radiation-induced soft errors are par- ticularly critical, as they have been found to dominate error rates in commercial devices [4]. The large scale and long application executions in leading scientific HPC centers exacerbate the prob- ability of having a transient error in the system. As a reference, DOE’s Titan, composed of more than 18,000KeplerGPUs, has a radiation-induced Mean Time Between Failures (MTBF) in the order of dozens of hours [21, 46]. As we approach exascale, the re- silience challenge will become even more critical due to an increase in system scale [34, 42, 45]. In this scenario, a lack of understanding of HPC device resilience may lead to lower scientific productivity and significant monetary loss [45].
Our intention is toevaluate,understand, anddevelop mitigation strategiesfor reliability issues in current and future supercomputers.
First, weevaluatethe problem by showing the results of our neutron beam experiments onKnights CornerXeon Phi (3120A) components.
We report the realistic SDC and DUE Failure In Time (FIT) rates of five benchmarks. Each benchmark was tested for more than 100 hours at the Los Alamos Neutron Science Center (LANSCE), provid- ing data that covers more than 57,000 years of natural exposure per board. All the collected errors are available on a public repository to allow third party analysis and to ensure reproducibility [40].
Supercomputing 2017
64 Affinity-Based Thread and Data Mapping in Shared Memory Systems MATTHIAS DIENER and EDUARDO H. M. CRUZ, Informatics Institute,
Federal University of Rio Grande do Sul
MARCO A. Z. ALVES, Department of Informatics, Federal University of Paran´a PHILIPPE O. A. NAVAUX, Informatics Institute, Federal University of Rio Grande do Sul ISRAEL KOREN, Department of Electrical & Computer Engineering, University of Massachusetts at Amherst
Shared memory architectures have recently experienced a large increase in thread-level parallelism, lead- ing to complex memory hierarchies with multiple cache memory levels and memory controllers. These new designs created a Non-Uniform Memory Access (NUMA) behavior, where the performance and energy con- sumption of memory accesses depend on the place where the data is located in the memory hierarchy.
Accesses to local caches or memory controllers are generally more efficient than accesses to remote ones. A common way to improve the locality and balance of memory accesses is to determine the mapping of threads to cores and data to memory controllers based on the affinity between threads and data. Such mapping tech- niques can operate at different hardware and software levels, which impacts their complexity, applicability, and the resulting performance and energy consumption gains. In this article, we introduce a taxonomy to classify different mapping mechanisms and provide a comprehensive overview of existing solutions.
CCS Concepts:
!
Computer systems organization→Multicore architectures;!
Software and its engineering→Main memory;SchedulingAdditional Key Words and Phrases: Survey, shared memory, thread mapping, data mapping, NUMA, cache memories, communication
ACM Reference Format:
Matthias Diener, Eduardo H. M. Cruz, Marco A. Z. Alves, Philippe O. A. Navaux, and Israel Koren. 2016.
Affinity-based thread and data mapping in shared memory systems. ACM Comput. Surv. 49, 4, Article 64 (December 2016), 38 pages.
DOI: http://dx.doi.org/10.1145/3006385 1. INTRODUCTION
Since reaching the practical limits of Instruction-Level Parallelism (ILP) [Brooks et al.
2000], processor manufacturers have been focusing on increasing the Thread-Level Parallelism (TLP) on modern shared memory architectures to continue improving sys- tem performance. Such multi-core, multi-threaded architectures exert a high pressure on the memory subsystem as they have to supply large quantities of data to the many functional units.
This work is supported by CAPES, under grant PVE 117/2013, and MCTI/RNP Brazil under the HPC4E project, grant 689772.
Authors’ addresses: M. Diener and E. H. M. Cruz, P. O. A. Navaux, Informatics Institute, Federal University of Rio Grande do Sul, Av. Bento Gonc¸alves, 9500, 91501-970, Porto Alegre, RS, Brazil; emails: {mdiener, ehmcruz, navaux}@inf.ufrgs.br; M. A. Z. Alves, Department of Informatics, Federal University of Paran´a, Rua Cel. Francisco Her´aclito dos Santos, 100, 81531-990, Curitiba, PR, Brazil; email: mazalves@inf.ufpr.br;
I. Koren, 309E Knowles Engineering Building, Department of Electrical & Computer Engineering, University of Massachusetts, Amherst, MA 01003; email: koren@ecs.umass.edu.
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⃝2016 ACM 0360-0300/2016/12-ART64 $15.00c DOI: http://dx.doi.org/10.1145/3006385
ACM Computing Surveys, Vol. 49, No. 4, Article 64, Publication date: December 2016.
