TECHNICALUSER'SMANUAL Cortex-M3/M4FInstructionSet

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Cortex-M3/M4F Instruction Set

T E C H N I C A L U S E R ' S M A N U A L

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Copyright

Copyright©2010-2011 Texas Instruments Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.

Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris

http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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List of Figures

Figure 1-1. Cortex-M Extensions ... 26

Figure 1-2. ASR #3 ... 29

Figure 1-3. LSR #3 ... 30

Figure 1-4. LSL #3 ... 30

Figure 1-5. ROR #3 ... 31

Figure 1-6. RRX ... 31 Table of Contents

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List of Tables

Table 1-1. Cortex-M3/M4F Instructions ... 19

Table 1-2. Condition Code Suffixes ... 33

Table 2-1. Memory Access Instructions ... 35

Table 2-2. Offset Ranges ... 38

Table 2-3. Offset Ranges ... 45

Table 3-1. General Data Processing Instructions ... 53

Table 4-1. Multiply and Divide Instructions ... 105

Table 5-1. Saturating Instructions ... 131

Table 6-1. Packing and Unpacking Instructions ... 147

Table 7-1. Bitfield Instructions ... 156

Table 8-1. Floating-Point Instructions ... 159

Table 9-1. Branch and Control Instructions ... 199

Table 9-2. Branch Ranges ... 201

Table 10-1. Miscellaneous Instructions ... 208

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List of Examples

Example 1-1. Absolute Value ... 34

Example 1-2. Compare and Update Value ... 34

Example 1-3. Instruction Width Selection ... 34

Example 3-1. 64-Bit Addition ... 57

Example 3-2. 96-Bit Subtraction ... 57 Table of Contents

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1 Introduction

Each of the following chapters describes a functional group of Cortex-M3/M4F instructions. Together they describe all the instructions supported by the Cortex-M3/M4F processor:

■ “Memory Access Instructions” on page 35

■ “General Data Processing Instructions” on page 53

■ “Multiply and Divide Instructions” on page 105

■ “Saturating Instructions” on page 131

■ “Packing and Unpacking Instructions” on page 147

■ “Bitfield Instructions” on page 156

■ “Floating-Point” on page 159

■ “Branch and Control Instructions” on page 199

■ “Miscellaneous Instructions” on page 208

1.1 Instruction Set Summary

The processor implements a version of the Thumb instruction set. Table 1-1 on page 19 lists the supported instructions.

In Table 1-1 on page 19:

■ Angle brackets, <>, enclose alternative forms of the operand.

■ Braces, {}, enclose optional operands.

■ The Operands column is not exhaustive.

■ Op2is a flexible second operand that can be either a register or a constant.

■ Most instructions can use an optional condition code suffix.

For more information on the instructions and operands, see the instruction descriptions. Figure 1-1 on page 26 shows the Cortex-M3/M4F instructions by category.

Table 1-1. Cortex-M3/M4F Instructions

See Page Flags

Brief Description Operands

Mnemonic M4F

M4 M3

55 N,Z,C,V

Add with carry {Rd,} Rn, Op2

ADC, ADCS

✓

55 N,Z,C,V

Add {Rd,} Rn, Op2

ADD, ADDS

✓

55 N,Z,C,V

Add {Rd,} Rn, #imm12

ADD, ADDW

✓

36 -

Load PC-relative address Rd, label

✓ ADR

✓

58 N,Z,C

Logical AND {Rd,} Rn, Op2

AND, ANDS

✓

60 N,Z,C

Arithmetic shift right Rd, Rm, <Rs|#n>

ASR, ASRS

✓

200 -

Branch label

✓ B

✓

157 -

Bit field clear Rd, #lsb, #width

✓ BFC

✓

157 -

Bit field insert Rd, Rn, #lsb, #width

✓ BFI

✓

55 N,Z,C

Bit clear {Rd,} Rn, Op2

BIC, BICS

✓

209 -

Breakpoint

#imm

✓ BKPT

✓

200 -

Branch with link label

✓ BL

✓

200 -

Branch indirect with link Rm

✓ BLX

✓

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Table 1-1. Cortex-M3/M4F Instructions (continued)

M4 M3

200 -

Branch indirect Rm

✓ BX

✓

202 -

Compare and branch if non-zero Rn, label

✓ CBNZ

✓

202 -

Compare and branch if zero Rn, label

✓ CBZ

✓

52 -

Clear exclusive -

CLREX

✓

63 -

Count leading zeros Rd, Rm

✓ CLZ

✓

64 N,Z,C,V

Compare negative Rn, Op2

✓ CMN

✓

64 N,Z,C,V

Compare Rn, Op2

✓ CMP

✓

210 -

Change processor state, disable interrupts

iflags CPSID

✓

210 -

Change processor state, enable interrupts

iflags CPSIE

✓

211 -

Data memory barrier -

✓ DMB

✓

211 -

Data synchronization barrier -

✓ DSB

✓

55 N,Z,C

Exclusive OR {Rd,} Rn, Op2

EOR, EORS

✓

213 -

Instruction synchronization barrier -

✓ ISB

✓

203 -

If-Then condition block -

✓ IT

✓

46 -

Load multiple registers, increment after

Rn{!}, reglist

✓ LDM

✓

46 -

Load multiple registers, decrement before

Rn{!}, reglist LDMDB, LDMEA

✓

46 -

Load multiple registers, increment after

Rn{!}, reglist LDMFD, LDMIA

✓

37 -

Load register with word Rt, [Rn{, #offset}]

✓ LDR

✓

37 -

Load register with byte Rt, [Rn{, #offset}]

LDRB, LDRBT

✓

37 -

Load register with two words Rt, Rt2, [Rn{, #offset}]

✓ LDRD

✓

50 -

Load register exclusive Rt, [Rn, #offset]

LDREX

✓

50 -

Load register exclusive with byte Rt, [Rn]

LDREXB

✓

50 -

Load register exclusive with halfword

Rt, [Rn]

LDREXH

✓

37 -

Load register with halfword Rt, [Rn{, #offset}]

LDRH, LDRHT

✓

37 -

Load register with signed byte Rt, [Rn{, #offset}]

LDRSB, LDRSBT

✓

37 -

Load register with signed halfword Rt, [Rn{, #offset}]

LDRSH, LDRSHT

✓

42 -

Load register with word Rt, [Rn{, #offset}]

✓ LDRT

✓

60 N,Z,C

Logical shift left Rd, Rm, <Rs|#n>

LSL, LSLS

✓

60 N,Z,C

Logical shift right Rd, Rm, <Rs|#n>

LSR, LSRS

✓

106 -

Multiply with accumulate, 32-bit result

Rd, Rn, Rm, Ra

✓ MLA

✓

106 -

Multiply and subtract, 32-bit result Rd, Rn, Rm, Ra

✓ MLS

✓

65 N,Z,C

Move Rd, Op2

MOV, MOVS

✓

65 N,Z,C

Move 16-bit constant Rd, #imm16

MOV, MOVW

✓

67 -

Move top Rd, #imm16

✓ MOVT

✓

214 -

Move from special register to general register

Rd, spec_reg

✓ MRS

✓

Introduction

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M4 M3

215 N,Z,C,V

Move from general register to special register

spec_reg, Rn

✓ MSR

✓

106 N,Z

Multiply, 32-bit result {Rd,} Rn, Rm

MUL, MULS

✓

65 N,Z,C

Move NOT Rd, Op2

MVN, MVNS

✓

216 -

No operation -

✓ NOP

✓

55 N,Z,C

Logical OR NOT {Rd,} Rn, Op2

ORN, ORNS

✓

55 N,Z,C

Logical OR {Rd,} Rn, Op2

ORR, ORRS

✓

148 -

Pack halfword {Rd,} Rn, Rm, Op2

PKHTB, PKHBT

✓

48 -

Pop registers from stack reglist

✓ POP

✓

48 -

Push registers onto stack reglist

✓ PUSH

✓

136 Saturating add Q

{Rd,} Rn, Rm

✓ QADD

✓

136 -

Saturating add 16 {Rd,} Rn, Rm

QADD16

✓

136 -

Saturating add 8 {Rd,} Rn, Rm

QADD8

✓

138 -

Saturating add and subtract with exchange

{Rd,} Rn, Rm

✓ QASX

✓

140 Saturating double and add Q

{Rd,} Rn, Rm QDADD

✓

140 Saturating double and subtract Q

{Rd,} Rn, Rm QDSUB

✓

138 -

Saturating subtract and add with exchange

{Rd,} Rn, Rm

✓ QSAX

✓

136 Saturating subtract Q

{Rd,} Rn, Rm

✓ QSUB

✓

136 -

Saturating subtract 16 {Rd,} Rn, Rm

QSUB16

✓

136 -

Saturating subtract 8 {Rd,} Rn, Rm

QSUB8

✓

68 -

Reverse bits Rd, Rn

✓ RBIT

✓

68 -

Reverse byte order in a word Rd, Rn

✓ REV

✓

68 -

Reverse byte order in each halfword Rd, Rn

REV16

✓

68 -

Reverse byte order in bottom halfword and sign extend Rd, Rn

REVSH

✓

60 N,Z,C

Rotate right Rd, Rm, <Rs|#n>

ROR, RORS

✓

60 N,Z,C

Rotate right with extend Rd, Rm

RRX, RRXS

✓

55 N,Z,C,V

Reverse subtract {Rd,} Rn, Op2

RSB, RSBS

✓

70 Signed add 16 GE

{Rd,} Rn, Rm SADD16

✓

70 Signed add 8 GE

{Rd,} Rn, Rm SADD8

✓

70 Signed add and subtract with GE

exchange {Rd,} Rn, Rm

✓ SASX

✓

55 N,Z,C,V

Subtract with carry {Rd,} Rn, Op2

SBC, SBCS

✓

158 -

Signed bit field extract Rd, Rn, #lsb, #width

✓ SBFX

✓

130 -

Signed divide {Rd,} Rn, Rm

✓ SDIV

✓

98 -

Select bytes {Rd,} Rn, Rm

✓ SEL

✓

217 -

Send event -

✓ SEV

✓

72 -

Signed halving add 16 {Rd,} Rn, Rm

SHADD16

✓

72 -

Signed halving add 8 {Rd,} Rn, Rm

SHADD8

✓

74 -

Signed halving add and subtract with exchange

{Rd,} Rn, Rm SHASX

✓

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M4 M3

74 -

Signed halving add and subtract with exchange

{Rd,} Rn, Rm SHSAX

✓

77 -

Signed halving subtract 16 {Rd,} Rn, Rm

SHSUB16

✓

77 -

Signed halving subtract 8 {Rd,} Rn, Rm

SHSUB8

✓

108 Signed multiply accumulate long Q

(halfwords) Rd, Rn, Rm, Ra

SMLABB, SMLABT, SMLATB, SMLATT

✓

111 Signed multiply accumulate dual Q

Rd, Rn, Rm, Ra SMLAD,

SMLADX

✓

128 -

Signed multiply with accumulate (32x32+64), 64-bit result RdLo, RdHi, Rn, Rm

SMLAL

✓

113 -

Signed multiply accumulate long (halfwords)

RdLo, RdHi, Rn, Rm SMLALBB,

SMLALBT, SMLALTB, SMLALTT

✓

113 -

Signed multiply accumulate long dual

RdLo, RdHi, Rn, Rm SMLALD, SMLALDX

✓

108 Signed multiply accumulate, word Q

by halfword Rd, Rn, Rm, Ra

SMLAWB,SMLAWT

✓

116 Signed multiply subtract dual Q

Rd, Rn, Rm, Ra SMLSD

SMLSDX

✓

116 Signed multiply subtract long dual

RdLo, RdHi, Rn, Rm SMLSLD

SMLSLDX

✓

119 -

Signed most significant word multiply accumulate Rd, Rn, Rm, Ra

SMMLA

✓

119 -

Signed most significant word multiply subtract

Rd, Rn, Rm, Ra SMMLS,

SMMLR

✓

121 -

Signed most significant word multiply

{Rd,} Rn, Rm SMMUL, SMMULR

✓

123 Signed dual multiply add Q

{Rd,} Rn, Rm SMUAD

SMUADX

✓

125 -

Signed multiply halfwords {Rd,} Rn, Rm

SMULBB, SMULBT, SMULTB, SMULTT

✓

128 -

Signed multiply (32x32), 64-bit result

RdLo, RdHi, Rn, Rm SMULL

✓

125 -

Signed multiply by halfword {Rd,} Rn, Rm

SMULWB, SMULWT

✓

123 -

Signed dual multiply subtract {Rd,} Rn, Rm

SMUSD, SMUSDX

✓

132 Q

Signed saturate Rd, #n, Rm {,shift #s}

✓ SSAT

✓

134 Signed saturate 16 Q

Rd, #n, Rm SSAT16

✓

✓ Introduction

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M4 M3

81 Saturating subtract and add with GE

✓ SSAX

✓

79 -

Signed subtract 16 {Rd,} Rn, Rm

SSUB16

✓

79 -

Signed subtract 8 {Rd,} Rn, Rm

SSUB8

✓

46 -

Store multiple registers, increment after

Rn{!}, reglist

✓ STM

✓

46 -

Store multiple registers, decrement before

Rn{!}, reglist STMDB, STMEA

✓

46 -

Store multiple registers, increment after

Rn{!}, reglist STMFD, STMIA

✓

37 -

Store register word Rt, [Rn{, #offset}]

✓ STR

✓

37 -

Store register byte Rt, [Rn{, #offset}]

STRB, STRBT

✓

37 -

Store register two words Rt, Rt2, [Rn{, #offset}]

✓ STRD

✓

50 -

Store register exclusive Rd, Rt, [Rn, #offset]

STREX

✓

50 -

Store register exclusive byte Rd, Rt, [Rn]

STREXB

✓

50 -

Store register exclusive halfword Rd, Rt, [Rn]

STREXH

✓

37 -

Store register halfword Rt, [Rn{, #offset}]

STRH, STRHT

✓

37 -

Store register signed byte Rt, [Rn{, #offset}]

STRSB, STRSBT

✓

37 -

Store register signed halfword Rt, [Rn{, #offset}]

STRSH, STRSHT

✓

42 -

Store register word Rt, [Rn{, #offset}]

✓ STRT

✓

55 N,Z,C,V

Subtract {Rd,} Rn, Op2

SUB, SUBS

✓

55 N,Z,C,V

Subtract 12-bit constant {Rd,} Rn, #imm12

SUB, SUBW

✓

218 -

Supervisor call

#imm

✓ SVC

✓

154 -

Extend 8 bits to 32 and add {Rd,} Rn, Rm, {,ROR #}

SXTAB

✓

154 -

Dual extend 8 bits to 16 and add {Rd,} Rn, Rm,{,ROR #}

SXTAB16

✓

154 -

Extend 16 bits to 32 and add {Rd,} Rn, Rm,{,ROR #}

SXTAH

✓

150 -

Signed extend byte 16 {Rd,} Rm {,ROR #n}

SXTB16

✓

150 -

Sign extend a byte {Rd,} Rm {,ROR #n}

✓ SXTB

✓

150 -

Sign extend a halfword {Rd,} Rm {,ROR #n}

✓ SXTH

✓

206 -

Table branch byte [Rn, Rm]

✓ TBB

✓

206 -

Table branch halfword [Rn, Rm, LSL #1]

✓ TBH

✓

84 N,Z,C

Test equivalence Rn, Op2

✓ TEQ

✓

84 N,Z,C

Test Rn, Op2

✓ TST

✓

86 Unsigned add 16 GE

{Rd,} Rn, Rm UADD16

✓

86 Unsigned add 8 GE

{Rd,} Rn, Rm UADD8

✓

88 Unsigned add and subtract with GE

✓ UASX

✓

91 -

Unsigned halving add 16 {Rd,} Rn, Rm

UHADD16

✓

91 -

Unsigned halving add 8 {Rd,} Rn, Rm

UHADD8

✓

93 -

Unsigned halving add and subtract with exchange

{Rd,} Rn, Rm UHASX

✓

93 -

Unsigned halving subtract and add with exchange

{Rd,} Rn, Rm UHSAX

✓

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M4 M3

96 -

Unsigned halving subtract 16 {Rd,} Rn, Rm

UHSUB16

✓

96 -

Unsigned halving subtract 8 {Rd,} Rn, Rm

UHSUB8

✓

158 -

Unsigned bit field extract Rd, Rn, #lsb, #width

✓ UBFX

✓

130 -

Unsigned divide {Rd,} Rn, Rm

✓ UDIV

✓

128 -

Unsigned multiply accumulate accumulate long (32x32+64), 64-bit result

RdLo, RdHi, Rn, Rm UMAAL

✓

128 -

Unsigned multiply with accumulate (32x32+64), 64-bit result

RdLo, RdHi, Rn, Rm UMLAL

✓

128 -

Unsigned multiply (32x32), 64-bit result

RdLo, RdHi, Rn, Rm UMULL

✓

144 -

Unsigned saturating add 16 {Rd,} Rn, Rm

UQADD16

✓

144 -

Unsigned saturating add 8 {Rd,} Rn, Rm

UQADD8

✓

142 -

Unsigned saturating add and subtract with exchange {Rd,} Rn, Rm

UQASX

✓

142 -

Unsigned saturating subtract and add with exchange

{Rd,} Rn, Rm UQSAX

✓

144 -

Unsigned saturating subtract 16 {Rd,} Rn, Rm

UQSUB16

✓

144 -

Unsigned saturating subtract 8 {Rd,} Rn, Rm

UQSUB8

✓

99 -

Unsigned sum of absolute differences

{Rd,} Rn, Rm USAD8

✓

101 -

Unsigned sum of absolute differences and accumulate {Rd,} Rn, Rm, Ra

USADA8

✓

132 Q

Unsigned saturate Rd, #n, Rm {,shift #s}

✓ USAT

✓

134 Unsigned saturate 16 Q

Rd, #n, Rm USAT16

✓

93 Unsigned subtract and add with GE

✓ USAX

✓

96 Unsigned subtract 16 GE

{Rd,} Rn, Rm USUB16

✓

96 Unsigned subtract 8 GE

{Rd,} Rn, Rm USUB8

✓

154 -

Rotate, extend 8 bits to 32 and add {Rd,} Rn, Rm, {,ROR #}

UXTAB

✓

154 -

Rotate, dual extend 8 bits to 16 and add

{Rd,} Rn, Rm, {,ROR #}

UXTAB16

✓

154 -

Rotate, unsigned extend and add halfword

{Rd,} Rn, Rm, {,ROR #}

UXTAH

✓

150 -

Zero extend a byte {Rd,} Rm {,ROR #n}

✓ UXTB

✓

150 -

Unsigned extend byte 16 {Rd,} Rm, {,ROR #n}

UXTB16

✓

150 -

Zero extend a halfword {Rd,} Rm {,ROR #n}

✓ UXTH

✓

161 -

Floating-point absolute Sd, Sm

VABS.F32

✓

162 -

Floating-point add {Sd,} Sn, Sm

VADD.F32

✓

163 FPSCR

Compare two floating-point registers, or one floating-point register and zero

Sd, <Sm | #0.0>

VCMP.F32

✓

163 FPSCR

Compare two floating-point registers, or one floating-point register and zero with extend byte check

Sd, <Sm | #0.0>

VCMPE.F32

✓ Introduction

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M4 M3

167 -

Convert between floating-point and integer

Sd, Sm VCVT.S32.F32

✓

167 -

Convert between floating-point and fixed point

Sd, Sd, #fbits VCVT.S16.F32

✓

167 -

Convert between floating-point and integer with rounding

Sd, Sm VCVTR.S32.F32

✓

169 -

Converts half-precision value to single-precision

Sd, Sm VCVT<B|H>.F32.F16

✓

169 -

Converts single-precision register to half-precision

Sd, Sm VCVTT<B|T>.F32.F16

✓

171 -

Floating-point divide {Sd,} Sn, Sm

VDIV.F32

✓

172 -

Floating-point fused multiply accumulate

{Sd,} Sn, Sm VFMA.F32

✓

173 -

Floating-point fused negate multiply accumulate

{Sd,} Sn, Sm VFNMA.F32

✓

172 -

Floating-point fused multiply subtract

{Sd,} Sn, Sm VFMS.F32

✓

173 -

Floating-point fused negate multiply subtract

{Sd,} Sn, Sm VFNMS.F32

✓

174 -

Load multiple extension registers Rn{!}, list

VLDM.F<32|64>

✓

176 -

Load an extension register from memory

<Dd|Sd>, [Rn]

VLDR.F<32|64>

✓

178 -

Floating-point multiply accumulate {Sd,} Sn, Sm

VLMA.F32

✓

178 -

Floating-point multiply subtract {Sd,} Sn, Sm

VLMS.F32

✓

179 -

Floating-point move immediate Sd, #imm

VMOV.F32

✓

180 -

Floating-point move register Sd, Sm

✓ VMOV

182 -

Copy ARM core register to single precision

Sn, Rt

✓ VMOV

183 -

Copy 2 ARM core registers to 2 single precision

Sm, Sm1, Rt, Rt2

✓ VMOV

184 -

Copy ARM core register to scalar Dd[x], Rt

✓ VMOV

181 -

Copy scalar to ARM core register Rt, Dn[x]

✓ VMOV

185 N,Z,C,V

Move FPSCR to ARM core register or APSR

Rt, FPSCR

✓ VMRS

186 FPSCR

Move to FPSCR from ARM core register

FPSCR, Rt

✓ VMSR

187 -

Floating-point multiply {Sd,} Sn, Sm

VMUL.F32

✓

188 -

Floating-point negate Sd, Sm

VNEG.F32

✓

189 -

Floating-point multiply and add {Sd,} Sn, Sm

VNMLA.F32

✓

189 -

Floating-point multiply and subtract {Sd,} Sn, Sm

VNMLS.F32

✓

189 -

Floating-point multiply {Sd,} Sn, Sm

VNMUL

✓

191 -

Pop extension registers list

✓ VPOP

192 -

Push extension registers list

VPUSH

✓

193 -

Calculates floating-point square root Sd, Sm

VSQRT.F32

✓

194 -

Floating-point register store multiple Rn{!}, list

✓ VSTM

(26)

M4 M3

194 -

Stores an extension register to memory

Sd, [Rn]

VSTR.F3<32|64>

✓

196 -

Floating-point subtract {Sd,} Sn, Sm

VSUB.F<32|64>

✓

219 -

Wait for event -

✓ WFE

✓

220 -

Wait for interrupt -

✓ WFI

✓

Figure 1-1. Cortex-M Extensions

1.2 About the Instruction Descriptions

The following sections give more information about using the instructions:

■ “Operands” on page 27

■ “Restrictions When Using the PC or SP” on page 27

■ “Flexible Second Operand” on page 27

■ “Shift Operations” on page 28

■ “Address Alignment” on page 31

■ “PC-Relative Expressions” on page 32

■ “Conditional Execution” on page 32

■ “Instruction Width Selection” on page 34 Introduction

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1.2.1 Operands

An instruction operand can be an ARM Cortex-M3/M4F register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands.

Operands in some instructions are flexible in that they can either be a register or a constant. See

“Flexible Second Operand” on page 27.

See theStellaris® Data Sheetfor more information on the ARM Cortex-M3/M4F registers.

1.2.2 Restrictions When Using the PC or SP

Many instructions have restrictions on whether you can use theProgram Counter (PC)orStack Pointer (SP)for the operands or destination register. See the instruction descriptions for more information.

Important: Bit[0] of any address you write to thePCwith aBX,BLX,LDM,LDR, orPOPinstruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3/M4F processor only supports Thumb instructions.

1.2.3 Flexible Second Operand

Many general data processing instructions have a flexible second operand. This is shown as Operand2in the descriptions of the syntax of each instruction.

Operand2can be a constant or a register with optional shift.

1.2.3.1 Constant

You specify anOperand2constant in the form:

#constant

whereconstantcan be (XandYare hexadecimal digits):

■ Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word.

■ Any constant of the form0x00XY00XY.

■ Any constant of the form0xXY00XY00.

■ Any constant of the form0xXYXYXYXY.

Note: In the constants listed above, X and Y are hexadecimal digits.

In addition, in a small number of instructions,constantcan take a wider range of values. These are described in the individual instruction descriptions.

When anOperand2constant is used with the instructionsMOVS,MVNS,ANDS,ORRS,ORNS,EORS, BICS,TEQorTST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag ifOperand2is any other constant.