Universidade de Aveiro Departamento deElectr´onica, Telecomunica¸c˜oes e Inform´atica, 2018
Filipe
Almeida Costa
T´
ecnicas de Encapsulamento de Circuitos ´
Oticos
Integrados para Redes PON
Packaging of Photonic Integrated Circuits for PON
Networks
Universidade de Aveiro Departamento deElectr´onica, Telecomunica¸c˜oes e Inform´atica, 2018
Filipe
Almeida Costa
T´
ecnicas de Encapsulamento de Circuitos ´
Oticos
Integrados para Redes PON
Packaging of Photonic Integrated Circuits for PON
Networks
Disserta¸c˜ao apresentada `a Universidade de Aveiro para cumprimento dos requisitos necess´arios `a obten¸c˜ao do grau de Mestre em Engenharia Eletr´onica e Telecomunica¸c˜oes, realizada sob a orienta¸c˜ao cient´ıfica do Doutor Ant´onio Teixeira, Professor do Departamento de Eletr´onica Tele-comunica¸c˜oes e Inform´atica da Universidade de Aveiro e do Engenheiro Francisco Rodrigues da PICadvanced S.A.
o j´uri / the jury
presidente / president Professor Doutor Pedro Nicolau Faria da Fonseca
Professor Auxiliar da Universidade de Aveiro
vogais / examiners committee Professor Doutor Ant´onio Luis Jesus Teixeira
Professor Associado com Agrega¸c˜ao da Universidade de Aveiro (orientador)
Professor Doutor Henrique Manuel de Castro Faria Salgado
agradecimentos Este documento marca o final de uma importante etapa da minha vida, quero agradecer a todos os que contribu´ıram para que este cap´ıtulo fosse conclu´ıdo.
Em especial quero agradecer aos meus pais e irm˜ao pois foram os pilares que desde sempre me apoiaram incondicionalmente, n˜ao s´o nos bons momentos como tamb´em nos menos bons. Um agradecimento aos restantes familiares por me ensinarem a ser uma melhor pessoa, tanto profissionalmente assim como pessoalmente. Aos amigos que me tˆem acompanhado neste percurso, ano ap´os ano, um enorme obrigado pelas festas, pelo estudo e pelos conselhos dados.
Um agradecimento tamb´em ao Instituto de Telecomunica¸c˜oes por ter disponibilizado as suas instala¸c˜oes e ao grupo de ´otica por ao longo de este ano estar sempre dispon´ıvel para me ajudar.
Agrade¸co ao Prof. Doutor Ant´onio Teixeira, ao Prof. Doutor M´ario Lima e ao Eng. Francisco Rodrigues pelo conhecimento transmitido e pela disponibilidade.
Obrigado a todos os colaboradores da PICadvanced por desde in´ıcio me acolherem e auxiliarem, em especial ao Eng. Hugo Neto, ao Eng. Ricardo Bastos, `a Eng. Ana Tavares, ao Eng. Jos´e Lima, `a Eng. Carla Rodrigues e ao Eng. Guilherme Cabral pois foram pessoas que trabal-haram diretamente comigo. Obrigado pelo tempo em mim investido. Este trabalho foi financiado pela FCT/MEC atrav´es de fundos nacionais e quando aplic´avel cofinanciado pelo FEDER, no ˆambito do Acordo de Parceria PT2020 no ˆambito do projeto, COMPRESS - PTDC/EEI-TEL/7163/2014.
This work was supported by the European Regional Development Fund (FEDER), through the Regional Operational Program of Centre (CEN-TRO 2020) of the Portugal 2020 framework [Project HeatIT with Nr. 017942 (CENTRO-01-0247-FEDER-017942)].
Palavras chave Encapsulamento el´etrico, encapsulamento t´ermico, circuito ´otico inte-grado (PIC), regras de design t´ermico (TDR)
Resumo Hoje em dia, os sistemas de comunica¸c˜ao ´otica s˜ao capazes de ofer-ecer elevadas velocidades de transmiss˜ao. Com o desenvolvimento destes sistemas ´e necess´ario estudar e melhorar dom´ınios como as suas t´ecnicas de encapsulamento, nomeadamente encapsulamento ´otico, el´etrico, t´ermico, mecˆanico e qu´ımico. Esta disserta¸c˜ao aborda en-capsulamento el´etrico e t´ermico.
Numa fase inicial deste trabalho s˜ao descritas regras de encapsulamento atualmente usadas num circuito integrado ´otico-el´etrico (OEIC) e ´e apresentada a dependˆencia t´ermica de alguns componentes presentes num circuito ´otico integrado (PIC).
De seguida, ´e feito encapsulamento el´etrico que consiste no desen-volvimento de um circuito impresso para teste de um circuito ´otico. A sua conex˜ao com o circuito ´otico, de dimens˜oes microsc´opicas, ´e feito atrav´es da tecnologia de wire-bonding.
Este trabalho termina com um estudo acerca do encapsulamento t´ermico em que ´e criada uma lista de regras de design t´ermicas (TDRs). Estas regras contˆem informa¸c˜ao acerta da distancia m´ınima entre com-ponentes num circuito ´otico para que n˜ao haja interferˆencia t´ermica.
Keywords Electrical packaging, Thermal packaging, photonic integrated cir-cuit(PIC), thermal design rules (TDR)
Abstract Nowadays, optical communication systems are capable of providing high bit rates. With technological evolution of these systems, it is nec-essary to study and improve domains like their packaging techniques, such as optical, electrical, thermal, mechanical and chemical packag-ing.
In an early stage of this work, packaging design rules currently used in opto-electronic integrated circuit (OEIC) are listed. Furthermore, ther-mal dependence of some components placed in a photonic integrated circuit (PIC) is presented.
Later on, the electrical packaging is performed which consists of devel-oping a printed circuit board (PCB) for testing a photonic integrated circuit (PIC). The connection between the microscopic optical circuit and the electric circuit is made through wire-bonding technology. This work is finalized with thermal packaging where it is created a list of thermal design rules TDRs containing information about the minimum distance between active components in an optical integrated circuit for not having thermal interference.
Contents
Contents i
List of Figures iii
List of Tables vii
Acronyms ix
1 Introduction 1
1.1 Overview and Motivation . . . 1
1.2 Objectives . . . 2
1.3 Structure . . . 2
1.4 Contributions . . . 3
2 Packaging of Optoelectronic Integrated Circuits 5 2.1 Packaging Design Rules . . . 5
2.2 Active Adjustment Techniques . . . 7
2.3 Passive Adjustment Techniques . . . 8
2.3.1 Flip-Chip . . . 8
2.3.2 LIGA . . . 10
2.4 Wire Bonding . . . 12
2.4.1 Bonding Technologies . . . 13
2.4.2 Adhesive Bonding . . . 14
2.5 Wire Bonding versus Flip Chip . . . 14
2.6 Thermal Modelling . . . 15 2.7 Thermal Control . . . 18 2.8 Butterfly Packaging . . . 19 2.9 Conclusion . . . 20 3 Electrical Packaging 21 3.1 Electrical Analysis . . . 21
3.1.1 Advanced Design System simulation . . . 21
3.1.2 PCB Design . . . 21
3.1.2.2 PIN BIAS . . . 26
3.1.2.3 Spacing Optimization . . . 27
3.2 Wire Bonding Characterization . . . 28
3.2.1 Bond Wire Model . . . 28
3.2.2 Simulation . . . 29 3.2.3 ADS EBOND . . . 30 3.2.4 Measurement Setup . . . 32 3.2.5 Results . . . 32 3.3 Conclusion . . . 34 4 Thermal Packaging 35 4.1 Thermal Analysis . . . 35 4.1.1 ANSYS Simulation . . . 35
4.1.2 Finite Elements Method . . . 36
4.1.2.1 Procedure of Finite Element Analysis . . . 36
4.1.3 Steady-State Theory . . . 36
4.1.4 DFB laser . . . 37
4.1.4.1 Interference Between Two DFB Lasers . . . 39
4.1.4.2 Safety Distance Between Two DFB lasers . . . 41
4.1.5 Semiconductor Optical Amplifier . . . 41
4.1.5.1 Interference Between Two SOAs . . . 44
4.1.5.2 Safety Distance Between Two SOAs . . . 46
4.1.6 DFB Laser With Semiconductor Optical Amplifier . . . 46
4.1.7 Thermal Design Rules . . . 48
4.2 Integrated Thermal Sensor . . . 50
4.2.1 Pt Ti Sensors . . . 50
4.2.2 Setup . . . 50
4.2.3 Tests and Results . . . 51
4.2.4 Results Analysis . . . 56
4.3 Conclusion . . . 59
5 Conclusion and Future Work 61 5.1 Conclusion . . . 61
5.2 Future Work . . . 62
Appendices 63
A Measured Bond Wire Length 64
List of Figures
2.1 Optical and electrical orientation in a PIC [1]. . . 6
2.2 Electrical connections to the PIC [1] . . . 7
2.3 Six axes Nano-positioning system [2] . . . 8
2.4 Flip-chip integration of an electronic device on a silicon photonic platform [3] 9 2.5 Solder bumps-self adjustment [4] . . . 9
2.6 Generic configuration of Flip-Chip packaging with underfill [5] . . . 9
2.7 a) Tyndall recommendations b)flip-chip integration of an electronic-IC on a Silicon Photonic c)An image of fully packaged photonic system. [6] . . . . 10
2.8 Process steps of the LIGA process [4] . . . 11
2.9 Spring element arrays for fiber-chip coupling [7] . . . 11
2.10 Wire bonding technology [8] . . . 12
2.11 Damage patterns at the end of the pull test, with left: using gold wire and right: using copper wire [9] . . . 12
2.12 Wire bonding processes . . . 13
2.13 Structure of adhesive bonding [10] . . . 14
2.14 (a) Transient wavelength drifts caused by temperature variation after tuning of Ir. (b) Transient wavelength drifts caused by temperature variation after tuning of both If and Ir. [11]. . . 16
2.15 Fiber-to-fiber gain spectra at 70 mA injection current for various mount temperatures [12]. . . 17
2.16 Simulated output spectrum of the outer channel of the AWG design when the temperature undergoes a temperature variation from 280 K to 360 K [13]. 18 2.17 Thermal control using TEC [14]. . . 19
2.18 Butterfly package [15] . . . 19
3.1 Microstrip transmission line [16]. . . 22
3.2 Haar transform- PIC specifications. . . 24
3.3 Building blocks- PIC specifications. . . 24
3.4 PCB designed for characterization of a PIC that performs Haar transform. 25 3.5 PCB designed for testing building blocks of a PIC. . . 26
3.6 PIN bias. . . 27
3.7 PIN bias with current mirror. . . 27
3.9 Parasitic elements for a straight wire . . . 28
3.10 PCB layout for characterization of wire bonding . . . 30
3.11 ADS 3-dimensional model of EBOND . . . 31
3.12 S21 as a function of frequency in simulation . . . 31
3.13 Setup for measuring S21 parameters . . . 32
3.14 S21 parameter measured values. . . 33
3.15 Comparison between S21 measured and simulated values. . . 33
4.1 Thermal distribution of a DFB laser . . . 37
4.2 Cross-section of a DFB laser . . . 37
4.3 Thermal distribution of a DFB laser as a function of the distance along the X axis considering Pd values calculated in table 4.1 . . . 38
4.4 Thermal distribution of a DFB laser as a function of the distance along the Y axis considering Pd values calculated in table 4.1 . . . 38
4.5 Thermal distribution of two DFB lasers. . . 39
4.6 Thermal interference between two DFB lasers separated by 1500µm consid-ering several Pd values in each DFB . . . 39
4.7 Thermal interference between two DFB lasers separated by 750µm consid-ering several Pd values in each DFB . . . 40
4.8 Thermal interference between two DFB lasers separated by 200µm consid-ering several Pd values in each DFB . . . 40
4.9 Safety distance between two DFB lasers. . . 41
4.10 Thermal distribution of a SOA. . . 41
4.11 Cross-section of SOA. . . 42
4.12 Thermal distribution of a SOA as a function of the distance along the X axis considering Pd values calculated in table 4.2 . . . 43
4.13 Thermal distribution of a SOA as a function of the distance along the Y axis considering Pd values calculated in table 4.2 . . . 43
4.14 Thermal distribution of two SOAs. . . 44
4.15 Thermal interference between two SOAs separated by 1200µm considering several Pd values in each SOA . . . 44
4.16 Thermal interference between two SOAs separated by 600µm considering several Pd values in each SOA . . . 45
4.17 Thermal interference between two SOAs separated by 300µm considering several Pd values in each SOA . . . 45
4.18 Safety distance between two SOAs. . . 46
4.19 Thermal distribution of DFB laser + SOA. . . 46
4.20 Cross-section of DFB laser + SOA. . . 47
4.21 Thermal distribution of DFB laser + SOA along the X axis. . . 47
4.22 Thermal distribution of DFB laser + SOA along the Y axis. . . 48
4.23 Block diagram of devices simulated . . . 48
4.24 Silicon chip design . . . 50
4.26 Laboratory Setup for measuring Pt Ti sensors . . . 51 4.27 Experimental values of resistance as a function of the temperature
consid-ering a width of 10µm. . . 52 4.28 Experimental values of sensitivity as a function of the length, considering a
width of 10µm. . . 52 4.29 Experimental values of Resistance mean value as a function of their length,
considering a width of 10µm. . . 53 4.30 Experimental values of resistance as a function of the temperature
consid-ering a width of 7µm. . . 53 4.31 Experimental values of sensitivity as a function of the length, considering a
width of 7µm. . . 54 4.32 Experimental values of Resistance mean value as a function of the length,
considering a width of 7µm. . . 54 4.33 Experimental values of resistance as a function of the temperature
consid-ering a width of 5µm. . . 55 4.34 Experimental values of sensitivity as a function of the length, considering a
width of 5µm. . . 55 4.35 Experimental values of Resistance mean value as a function of the length,
considering a width of 5µm. . . 56 4.36 Presence of humidity in the sensor . . . 59 A.1 Length of wire-bonding . . . 65
List of Tables
2.1 Advantages and disadvantages of wire bonding technology . . . 15
2.2 Advantages and disadvantages of flip chip technology . . . 15
3.1 Measured bond wire length . . . 30
4.1 Power dissipated values for DFB laser . . . 38
4.2 Power dissipated values for SOA . . . 42
4.3 Experimental values of Sensitivity and RMV considering a length of 35 mm 56 4.4 Sensitivity and RMV . . . 57
Acronyms
ADS Advanced Design System
Al Aluminum
Au Gold
AWG Arrayed Wavelength Grating
Cu Copper
DBR Distributed Bragg reflector laser DFB Distributed Feedback Laser EIC Eletronic Integrated Circuit
EPIC European Phonics Industry Consortium
FC Flip-Chip
IBM International Business Machines
IC Integrated Circuit
INESC-MN Instituto de Engenharia de Sistemas e Computadores-Microsistemas e Nanotecnolo-gias
LIGA Lithographie, Galvanoformung, Abformung
LIV Light-Current-Voltage
N-GPON2 Next-Generation Passive Optical Network 2 OEIC Opto Eletronic Integrated Circuit
OLT Optical Line Terminal
PCB Printed Circuit Board PDRs Packaging Design Rules PDRs Product Design Rules PIC Photonic Integrated Circuit PID Proportional Integral Derivative PON Passive Optical Network
Pt Ti Platinum-Titanium
RF Radio frequency
RMV Resistance Mean Value
SOA Semiconductor Optical Amplifier
TCR temperature Coefficient of Electrical Resistiv-ity
TDRs Thermal Design Rules TEC Thermoelectric Cooler TOC Thermo-optic coefficient
TWDM Time and Wavelength Division Multiplexer VNA Virtual Network Analyzer
Chapter 1
Introduction
This chapter presents the extension of this work. Section 1.1 presents the overview and motivation of this dissertation, section 1.2 presents the main objectives, section 1.3 the structure and section 1.4 lists the major contributions of this work.
1.1
Overview and Motivation
Nowadays, there is a demand for higher data-transfer rates across communication net-works, going into optoelectronic technology allow data rates of 40-160 Gbit/s in the telecom core network [4]. Optical fiber access systems based on passive optical networks (PON) are currently been expanded by network operators. N-GPON2 is a 40Gigabit-class PON system that exploits both the time and wavelength domains (TWDM) [17]. TWDM uses four channels, each of 10 Gbit/s for downstream and 2.5 Gbit/s for upstream. Resulting in 40 Gbit/s downstream capacity and 10 Gbit/s upstream [17]. This is possible since ONUs (Optical Network Unit) are equipped with tunable transmitters and receivers. The tunable transmitter is tunable to any of the four upstream wavelengths. The receiver is tunable to any of the four downstream wavelengths [18].
ONUs and Optical Line Terminals (OLTs) are equipped with an OEIC (Optoelectronic integrated circuit) which lies on a photonic integrated circuit (PIC) and an electronic integrated circuit (EIC), as such, OEIC aggregates optical and electrical domains retaining the advantages of each. PIC for high-speed signaling and sensing, and CMOS-electronics for subsequent logical operations and computations [19].
The photonic packaging describes the range of techniques and technical competencies needed to make the optical, electrical, thermal, mechanical (and sometimes chemical) con-nections between a PIC and the outside world [19]. In this work, it is studied the electrical and thermal packaging. Photonic packaging has an important role in the OEIC since there are some variables directly related to circuits performance.
Regarding electrical packaging, it is important to study subjects such as high-speed routing and impedance-matching of transmission-lines from external connectors to the microscopic photonic components on the PIC [19]. Connection between the PIC and the
EIC is performed using wire bonding or flip-chip. Both techniques have impact on OEIC performance.
Photonic integrated circuits need to have a stable temperature within its operational range, because components like a semiconductor optical amplifier (SOA) or a distributed feedback laser (DFB) are temperature sensitive devices dependents. Using thermal sensors to measure PIC temperature and a thermoelectric cooler (TEC) to control it is an approach used. Additionally, the position of active components in an optical circuit is a crucial subject once thermal interference between components affects their performance.
1.2
Objectives
The purpose of this work is to study the packaging of photonic integrated circuits re-garding electrical thermal domains. The following objectives are explored in this document:
• Summary of packaging design rules nowadays used; • Balance between wire bonding and flip-chip techniques;
• Development of a printed circuit board for biasing and testing a photonic integrated circuit;
• Study about thermal interference between active components in a photonic integrated circuit;
• Characterization of Sensitivity and Resistance Mean Value (RMV) for Pt Ti sensors;
1.3
Structure
This document is structured in 5 parts:
• Chapter 1 - Overview and motivation In this chapter, an overview of this document is presented as well as the objectives, structure, and contributions.
• Chapter 2 - Packaging of optoelectronic integrated circuits Information about packaging techniques currently used in optics is given to the reader in this chapter. Goes into detail about wire bonding and flip-chip techniques, followed by thermal phenomena that can occur in optical components.
• Chapter 3 - Electrical packaging This section is divided into two parts. First, is developed two PCBs for testing and biasing two photonic integrated circuit. In the second part, a study on wire bonding performance as a function of the wire length is performed.
• Chapter 4 - Thermal Packaging This section is divided into two parts. First, a study on thermal interference between active components is presented. Resulting in a list of thermal design rules. In the second part, a characterization of an integrated thermal sensor based on Platinum-Titanium is performed.
• Chapter 5 - Conclusion and future work Conclusions are presented along with suggested future work regarding this dissertation.
1.4
Contributions
The main contributions of this work are:
• a study on the effect of wire length in wire bonding technology performance; • Development of thermal design rules (TDRs);
Chapter 2
Packaging of Optoelectronic
Integrated Circuits
An overview about photonic packaging techniques currently used is made in this chap-ter. Furthermore, a comparison between wire bonding and Flip-Chip technologies is per-formed. Lastly, temperature effects on a photonic integrated circuit components are stud-ied.
2.1
Packaging Design Rules
European Photonics Industry Consortium (EPIC) established packaging design rules, PDRs. These PDRs specify the recommended dimensions and locations of the optical and electronic ports to the PIC and covers the packaging of Si-, InP-, and TriPleX- photonic integrated circuits. If these rules are not followed, then packaging may be difficult or even physically impossible [1].
It is recommended to use the North and the South sides of a PIC to electrical connec-tions while the East and West to optical connecconnec-tions. Optical and electrical connecconnec-tions are never permitted on the same side. In some cases of need, optical connections in East side can be replaced with electrical connections. [1] [6].
In figure (2.1) some examples of the orientation in a PIC are presented. PIC#4 is not compatible with standard packaging procedures because the South side is occupied with optical connections instead of electrical. In PIC#5, optical and electrical connections are on the same edge.
Figure 2.1: Optical and electrical orientation in a PIC [1].
Electrical connections between the pick and the outside world (i.e. PCB) are made using Wire-bonding. The location and the pitch of the bond-pads are also recommended by EPIC [1] [6].
1. DC connections:
• Square bond-pads with 100µm of side-length. • Pads should be separated by a pitch of 200µm.
• Pads should be located 100µm from the edge of the PIC. 2. RF connections:
• Square bond-pads with 100µm of side-length. • Pads should be separated by a pitch of 300µm.
• Pads should be located 100µm from the edge of the PIC.
In the case of single-End RF, the pads should be (Ground/Signal/ground) figure (2.2-e). For differential RF, (Ground / Signal(+) / Ground / Signal(-) / Ground ) figure (2.2-f). If a PIC design calls for both DC and RF electrical-connections, EPIC recommends locating all DC bond-pads along the North edge of the PIC, and all RF bond-pads along the South edge [1]. Each pad of a PIC should be connected to a pad of the PCB with a straight wire bond connection figure (2.2-b) instead of staggered bond-pads on the PIC leading to a high risk of shorting [1] [6].
Figure 2.2: Electrical connections to the PIC [1]
2.2
Active Adjustment Techniques
The active techniques use the ability to control the adjustment under real electrical excitation conditions of OEICs [4]. Device alignment is based on the maximization of coupled power and carried out by micro-mechanical actuators, usually performed by hand. After the optimization of the coupled power, the device is fixed permanently [20] [4].
In order to align the fiber optically to another component, is necessary to move the fiber, the component, or both. Using the Cartesian frame of reference, there are six degrees of freedom to describe fully the position and motion of a solid body in space. Three linear (x,y,z) and three angular (θx, θy, θz) [2]. An example of a mechanical actuator system is shown in figure 2.3.
Figure 2.3: Six axes Nano-positioning system [2]
2.3
Passive Adjustment Techniques
Passive adjustment technique means a fiber–chip coupling by pre-alignment grooves that are especially suitable for mass production, once the process of production can be automatized reducing the cost unit cost with the increase of production [20]. Flip-Chip and LIGA (Lithographie, Galvanoformung, Abformung) are two examples of passive adjustment technique [4].
2.3.1
Flip-Chip
Flip-Chip (FC) is an old technique for interconnecting semiconductor devices, it was created by International Business Machines (IBM) in the decade of 1960s [21] and recently an implementation of this technique in the optical domain started to be studied due to high demands of bit-rates. In this technique, a device can be mounted directly onto a sub-strate, board, or carrier in a ‘face-down’ manner, electrical connection is achieved through conductive bumps built on the surface of the chips [21] [4]. Usually, bumps are composed of gold [4] [6] or copper [22].
Solder bumps avoid the use of relatively long wire-bonds which can induce parasitic effects (e.g. increased inductance) and which significantly affect high-speed (>10 GHz) performance [21]. Figure 2.4 illustrates the solder bumps between the electronic IC and the Silicon Photonic Device, to complete the connection between them it needs two active agents, heat and force. Literature report that short bond-distances promise very good RF-features up to 100GHz bandwidth [2].
Figure 2.4: Flip-chip integration of an electronic device on a silicon photonic platform [3] A further advantage of FC-bonding technology is the possibility of self-adjustment, bet-ter than 1µm [2]. It is based on the action of surface tensions of the melted solder, formed during the FC bonding (figure 2.5) [4] [23]. Surface tension is a physical phenomenon that occurs from pressure and cohesion between similar molecules. When the temperature is raised to the melting point of the solder, surface tension forces will tend to bring the structure into alignment as shown in figure 2.5.
Figure 2.5: Solder bumps-self adjustment [4]
To prevent the unit from environmental influence and provide mechanical stability between the chip and substrate it is used underfill technology [4] which consists of a liquid encapsulate, usually epoxy resins heavily filled with SiO2 [5]. Underfill improves the board
level reliability behavior, however, it might influence electrical performance of the product [24].
For FC bonding, Tyndall has some recommendations, presented in figure 2.7:
• The EIC and PIC are then brought into contact, together by solder reflow at 250oC
[6].
• PIC and EIC pads should both be 50µm * 50 µm in size separated by a pitch of 100µm [6].
• Au-thickness on the pads should be at least 500 nm [6].
Figure 2.7: a) Tyndall recommendations b)flip-chip integration of an electronic-IC on a Silicon Photonic c)An image of fully packaged photonic system. [6]
2.3.2
LIGA
LIGA is another method to perform passive fiber to chip alignment. This technology is divided into three steps: lithography, electroplating, and molding technique. The LIGA process is illustrated in figure 2.8: First, a mask is created, then X-ray radiation will generate voids in the substrate and electroplating will fill the voids for preparing the molding tool. After its removal from the mold, the last step consists of using the tool as a master form for the mass production of molded plastic devices [4].
Figure 2.8: Process steps of the LIGA process [4]
Initially, LIGA products have been fabricated either on a solid substrate or as a self-supporting structure but considering that LIGA allows the fabrication of three-dimensional micro-devices in a range of micrometers of precision from plastics, metals and ceramic ma-terial, it was developed some new applications. Spring-element array, illustrated in figure 2.9, is an example of a new application regarding LIGA technique and it is used for the fiber-to-chip coupling [7]. Due to the complexity of fabrication the mold with high preci-sion, the cost of production will naturally be expensive. Up to e50,000 for one imprint. This can be profitable only in mass production because the number of manufactured com-ponents divides the cost per part [4].
2.4
Wire Bonding
Wire bonding, presented in figure 2.10 is one of the oldest techniques to physically connect two devices and still continues to be highly used. It consists in providing electrical connection between the silicon chip and the external leads of the semiconductor device using very fine bonding wires [25] [4]. The wire used is made of gold(Au), aluminum (Al) and recently copper (Cu) started to be used in order to reduce the cost of production [9] [26] [27].
However, copper is substantially stiffer than gold, so there are higher forces to the chip structures and damages likely to occur [9]. Figure 2.11 illustrates the pull test, in the case of gold wire the damage is caused in the wire, on contrary with the copper wire the damage is caused in the silicon.
Figure 2.10: Wire bonding technology [8]
Figure 2.11: Damage patterns at the end of the pull test, with left: using gold wire and right: using copper wire [9]
Ball bonding and Wedge bonding are two different processes of wire bonding. Figure 2.12a illustrates Ball bonding and figure 2.12b, Wedge bonding. Ball bonding requires formation of a gold ball by melting the end of the gold wire, on the other hand, pressure
and ultrasonic energy are applied to the wire to form the Wedge bonding [25] [26]. Ball bonding is a faster solder and more robust, but, wedge bonding requires smaller pad size [28].
(a) Ball bonding (b) Wedge bonding
Figure 2.12: Wire bonding processes
2.4.1
Bonding Technologies
The methods currently used to wire bond include thermocompression, ultrasonic and thermosonic technologies.
Thermocompression-Used in Ball bonding, requires pressure and high temperature (300oC) to deform the wire. The wire material is Au and the pad can be Au or Al [4][27].
Ultrasonic-Used in Wedge bonding is performed at ambient temperature. Bonding is formed as a wedge bond by pressure and vibrational energy. Pad wire material should be either Au or Al [27] [4].
Thermosonic-used in Wedge bonding or Ball bonding, it is done at temperatures around 100oC to 240oC. Bonding is formed when the ultrasonic energy combines with
the capillary technique of thermocompression bonding [27]. Pad needs to be Au or Al and wire material should be Au or Cu [27].
Ultrasonic energy reduces the time of exposure to heat and the pressure necessary to complete the bonding, to the point that Ultrasonic bonding can be produced at room temperatures. Each technology has its own advantages and its drawbacks, if there is a need for a solder using a lower temperature, then Thermosonic and Ultrasonic are suitable possibilities, although ultrasonic energy is expensive, so in some cases Thermocompression could be preferred.
2.4.2
Adhesive Bonding
Adhesive bonding, represented in figure 2.13 is an alternative to wire bonding, instead of having a soldering process, it has an adhesive substance ( commonly a polymer) joining two substrates [10]. All OEICs without thermal load such as photodiodes can be fixed with adhesive. It results in a easier handling but leads to a shorter lifetime due to absorption of humidity [4].
Figure 2.13: Structure of adhesive bonding [10]
It is necessary to carefully choose the adhesive because there are different adhesives with different properties, for instance [4] [29]:
• Electrically conductive (with silver particles). • Electrically non-conductive.
• Thermally conductive for bonding of Peltier elements, heat sinks. • Underfiller/globetop for environmental protection
• Isotropic conductive adhesives (ICA) • Optically transparent
2.5
Wire Bonding versus Flip Chip
The cost of production and the flexibility of design are two main advantages of wire bonding technology, although it is a slow process since the pads are soldered one at time. At average is made 4 to 10 connections per second [8], nevertheless in case of failure, replacing a broken wire is possible. Bonding wires contribute significantly to parasitic inductance, thus limit the operation frequency to a few GHz [30]. Flip chip reduces this parasitic inductances [4] [8] as result of shorter interconnections in length (0.1 mm vs 1-5 mm), achieving bit-rates above 10 GHz/s [3] [31].
Flip chip has higher signal density because the entire surface of the die can be used for interconnections rather than the edge only [31], also, pads are smaller and closer to each other, culminating in higher number of input/output(I/O) pads. Mechanical stress can
occur in Flip-Chip technology due to different thermal expansion coefficients of the silicon and the package substrate [8]
A summary of advantages and disadvantages of both technologies is listed in tables 2.1 and 2.2.
Advantages Disadvantages
Low cost Slow process
Easily replaceable Pads are limited to the chip periphery Design flexibility Parasitic inductance
Table 2.1: Advantages and disadvantages of wire bonding technology
Advantages Disadvantages
Self-adjustment Expensive
Improved density Mechanical stress Reduced inductance
-Faster process
-Table 2.2: Advantages and disadvantages of flip chip technology
2.6
Thermal Modelling
In an active semiconductor optical component, a current is injected in an electrical PN junction to generate or amplify the light by stimulated emission. The efficiency of this process is not perfect and a part of the electrical power injected in device is transferred in heat generating temperature elevation in the vicinity of the active layers, leading to a performance degradation of the components, such as DFB lasers and SOAs [32].Laser optical power and SOA gain decrease when the temperature increases [32] [33].
A temperature change causes a thermal expansion change on the grating period of laser cavity. Furthermore, it causes change of the DFB laser wavelength output. Wavelength drift is reported to be 0.094 nm/oC and it corresponds to grating period expansion of 0.014
nm/oC [33]. Also, temperature transients will have influences on the laser’s performance especially on the lasing spectrum and wavelength drift, since the refractive index of the laser material changes with temperature. In some cases, wavelength drift can cause crosstalk to adjacent WDM channels as well as increase the bit-error rate of the WDM signals [11].
Figure 2.14 illustrates wavelength drift in a DBR laser as a function of time with differ-ent bias currdiffer-ents. Joule effect is more relevant for higher currdiffer-ents, as such, higher currdiffer-ents result in higher wavelength drift. Despite of being illustrated a maximum wavelength drift of 60 pm it is reported that in some cases this value can increase to 0.6nm [32].
Figure 2.14: (a) Transient wavelength drifts caused by temperature variation after tuning of Ir. (b) Transient wavelength drifts caused by temperature variation after tuning of both
If and Ir. [11].
If and Ir denotes the injection currents of the front and rear sections of grating DBR
(SG-DBR) laser [11].
Figure 2.15 exposes the fiber-to-fiber gain curves at 70 mA of injection current in a SOA for various mount temperatures. It is possible to see that the maximum of the gain spectra is decreased and shifted with the raise of temperature [12]. At 20oC the maximum
is at 1540 nm but at 60oC it is situated at 1555 nm, approximately. In this experiment, the
maximum gain shifts by 0.37 nm/K which is lower than typical values of monolithic SOAs ( 0.7 nm/K). This discrepancy is explained by the fact that the grating couplers have a parabolic pass-band, centered around a wavelength of 1550 nm [12];
Figure 2.15: Fiber-to-fiber gain spectra at 70 mA injection current for various mount temperatures [12].
Arrayed wavelength grating(AWG) is a passive device capable of multiplexing several wavelengths in one optical fiber. The performance of this device has thermal dependence, temperature variations affect the refractive index, which, as a function of temperature T can be written as:
η(λ, T ) = η0(λ) + κ(T − T0) (2.1)
Where η0(λ) is the usual refractive index dispersion relation at the reference
temper-ature T0 and κ is the thermo-optic coefficient (TOC) of AWG cladding [13]. Thermal
dependence can be seen in Figure 2.16 where it is presented the first output channel of an AWG at different temperatures. The spectrum is shifted as consequence of the temperature increase [13].
A solution to decrease thermal dependence is to replace the AWG cladding material with a different one sharing negative TOC [13].
Figure 2.16: Simulated output spectrum of the outer channel of the AWG design when the temperature undergoes a temperature variation from 280 K to 360 K [13].
The fact that the behavior of some devices change due to thermal effects can be advan-tageous, temperature dependence can be used for tuning proposes. An example is a DFB laser with resistive heating of a thin silver film [34].
2.7
Thermal Control
A solution for the need of an efficient distribution of high-speed electrical modulation onto the photonic platform is the face-to-face stacking the EIC and PIC, although, there are hundreds of electrical interconnects between EIC and PIC, as such, all of the Joule-heating evolved in the EIC must pass through the PIC, elevating PIC temperature. [35]
Photonic elements, such as integrated semiconductor optical amplifiers (SOAs) and micro-ring resonators, exhibit a strong temperature dependence[36][37] that is many times grater than that of CMOS electronics. A temperature variation of 20 oC is often sufficient for a PIC to drift out of its operational profile, consequently there is a need for thermal stabilization of the PIC in a photonic device using a thermo-electric cooler (TEC). TEC uses a PID controller. [19][14].
Figure 2.17a illustrates higher temperature in the EIC than in the PIC, that is justified due to Joule effect from electrical power evolved in the EIC [35]. Also, is possible to see that initially EIC temperature starts to increase while PIC stays at room temperature for 0.5 seconds, that is justified due thermal transfer from EIC to the PIC. PIC cool down process is presented in figure 2.17b, naturally, when the TEC is turned on the cool down
is accelerated, taking 10 seconds to reach the room temperature. In the case of PIC and TEC reboot, the temperature stabilizes in 3 seconds.
(a) (b)
Figure 2.17: Thermal control using TEC [14].
2.8
Butterfly Packaging
This topic presents an example of a standard package (figure 2.18) available in the market called Butterfly package, it was developed by LINKRA [15].
Figure 2.18: Butterfly package [15] Butterfly package has the following features incorporated: • TEC 4.5 Watt
• NTC Thermistor 10KΩ @ 25oC
• 2 or 4 RF pins (up to 25 GHz)
• Two rows of 26 DC pins (of which 2 for TEC and 2 for Thermistor and max 2x24 for the PIC)
2.9
Conclusion
State of the art related to packaging of photonic integrated circuits was presented in this chapter.
Chapter 3
Electrical Packaging
This chapter approaches electrical packaging of two photonic integrated circuit. It is di-vided in two sections: Electrical Analysis, section 3.1 and Wire Bonding Characterization, section 3.2.
3.1
Electrical Analysis
In this section a study on electrical packaging of a photonic integrated circuit is pre-sented. As it was seen in chapter 2, PIC dimensions (typically 6mm x 4mm) make the task of adding electronic components and RF connectors in the PIC physically impossible. Therefore, a PCB is required for assembling the electrical and optical circuits.
An example of an electrical packaging is presented in this section, it consists in two PCBs developed for two different photonic integrated chips.
3.1.1
Advanced Design System simulation
Advanced Design System (ADS) is an electronic design automation software for RF, microwave, high speed digital, and power electronics applications created by Keysight Technologies. ADS pioneers the most innovative and commercially successful technologies, such as X-parameters and 3D electromagnetic simulators [38]. Advanced Design System was used for designing two PCBs.
3.1.2
PCB Design
In order to design the PCB there are two main steps: define the substrate to use and calculate the physical dimensions of the transmission lines.
Figure 3.1: Microstrip transmission line [16].
In figure 3.1 is presented a microstrip transmission line where d is substrate height, t, the copper thickness, W is the width of the transmission line and r is the relative dielectric
constant. Characteristic impedance can be calculated using the following equations[39] where ef f is the effective dielectric constant.
For Wd ≤ 1 [39], Z0 = 60 √ ef f ln 8d W + W 4d (3.1) ef f = r+ 1 2 + r− 1 2 1 + 12 d W −12 + 0.04 1 −W d 2 (3.2) For Wd ≥ 1 [39], Z0 = 12π√ef f W d + 1.393 + 0.667 + ln W d + 1.444 (3.3) Where [39], ef f = r+ 1 2 + r− 1 2 1 + 12 d W −12 (3.4) At higher frequencies, the effective dielectric constant and characteristic impedance of a microstrip line begins to change with frequency[39]. As such:
ef f(f ) = r− r− ef f 1 + G(f /fp)2 (3.5) Z0(f ) = 377h Wef f(f )pef f(f ) (3.6) Where [39], fp = Z0 8πh (3.7) G = 0.6 + 0.009Z0 (3.8)
The effective width is given by [39]:
Wef f(f ) = W +
Wef f(0) − W
1 + (f /fp)2
(3.9)
Wef f(0) is obtained from 3.6 when f = 0 [39].
Individual RF properties are dependent on the respective dielectric constants, for ex-ample, with increasing dielectric constant, the bandwidth decreases [4]. On the other hand, by analyzing the equations 3.1 and 3.3, higher dielectric constants or thinner substrates en-ables transmission lines with smaller widths which is required in optics due to the number of pads and dimensions of the PIC.
LineCalc is an useful tool provided by ADS to calculate the transmission line phys-ical dimensions. Given the parameters such as Z0, d, t, r, and the frequency, LineCalc
synthesizes the transmission line width [16] using the theoretically equations from 3.1 to 3.4.
3.1.2.1 PCB Layout
It was chosen R04350b substrate which has dielectric constant, r, of 3.48, a substrate
height, d, of 250 µm and a copper thickness, t of 35 µm. Synthesizing the parameters above with LineCalc resulted in microstrip transmission lines with 544 µm of width, W , dimensioned for a bandwidth of 10GHz and a characteristic impedance, Z0, of 50 Ω.
N-GPON2 networks require a bandwidth of 10 GHz for each of the transmitters in an OEIC, that is the reason for adapting the transmission lines to a frequency of 10GHz.
With a substrate height of 250 µm, the PCB would lack mechanical endurance so instead of one layer it was used four layer technology where the three additionally layers are ground planes. With this approach, ground plane is still placed at 250 µm from the copper top layer but PCB thickness has increased.
A specification of the signals in each pad of the PIC was provided by PIC designer1.
Specifications are presented in figures 3.2 and 3.3.
Figure 3.2: Haar transform- PIC specifications.
Figure 3.3: Building blocks- PIC specifications.
The layout of the PCBs designed is presented in figures 3.4 and 3.5 where it is designed the transmission lines for ground (GND), DC and RF signals. Both PCBs have a length of 5.7 cm, a width of 4.5 cm and a thickness of 1 mm. In both images, at the vicinity of the PIC, there are transmission lines (shown in pink) to guide the user to align the fiber to the chip. PIC is glued to the PCB.
The transmission lines designed have the following properties: a width of 200 µm for DC signals, a pitch of 200 µm between DC transmission lines, a width of 544 µm for RF signals and a pitch of 300 µm between RF and DC transmission lines.
Figure 3.5: PCB designed for testing building blocks of a PIC.
3.1.2.2 PIN BIAS
PIN diodes are some of the components used in a PIC. Optical and electric power are related in a PIN diode once current is generated when photons are absorbed. A schematic with the first approach for biasing a PIN diode is presented in figure 3.6 but this solution has a drawback. When optical power increases, diode current increases, drop voltage in the resistor (VR) also increases, therefore the bias voltage of the diode VP IN will decrease.
If this process goes on, VP IN will be lower than threshold voltage, the diode will stop
Figure 3.6: PIN bias.
A proposed solution2 is to use a model based on a current mirror, presented in figure
3.7. The current flowing the resistor will be 5:1 ratio of PIN current and the bias voltage of the PIN will be constant3.
Figure 3.7: PIN bias with current mirror.
3.1.2.3 Spacing Optimization
The minimum pitch between DC lines used in this design was 200 µm although both PCBs have many wire bonds from the PIC to PCB pads so a pitch of 200 µm for all the DC lines is a physical challenge. A first approach was to increase the length of wire (illustrated in figure 3.8a) because for DC connections, length of the wire has no significant effect but longer wires are more likely to break. In addition, wires can touch their neighbor causing a shot circuit.
A solution proposed for optimizing the layout spacing was to short circuit in a single pad of the PCB the vicinity grounds in the PIC -i.e., instead of having a bond wire for each ground signal, connect several in the same pad, as shown in figure 3.8b.
2Suggested by PICadvanced
(a) Longer bond wires. (b) Space optimization.
Figure 3.8: Layout space optimization
3.2
Wire Bonding Characterization
Packaging can result in significant impedance discontinuity due to self-inductance, ap-proximately 1nH/mm, and series-resistance from the bonding wire, apap-proximately 0.1 Ohm/mm. It also cause mutual-inductance [40] but this aspect is not considered in this work. In order to characterize the wire bonding performance as a function of bond wire length it was designed in ADS a PCB with several distances between transmission lines pairs. S21 is the gain through the network [41]. By measuring S21parameter between each
pair of transmission lines it is possible to quantify the attenuation the network suffers at each frequency [41].
3.2.1
Bond Wire Model
Parasitic inductance and capacitance impose limits on the performance of circuits at high frequency or data rate [40]. In order to properly model the bond wires several parasitic elements must be identified, which include: self-inductance, Ls; mutual inductance, Lm;
self-capacitance, Cs; mutual capacitance, Cm; input-output pad capacitance, Cp; and
resis-tance, R [41]. Considering a single bond wire, mutual inductance and mutual capacitance do not exist.
A model for a single straight wire is presented in 3.9, where R represents gold wire resistance, Ls its self-inductance, Cs its self-capacitance and Cp1 and Cp2 are an electrical
representation of the coupling to the substrate [42][43].
Parasitic elements values are calculated using capacitance and inductance equations [41][44]. Ls = lµrµ0 2π ln( 2h r ) (3.10)
Self-inductance of a wire can be calculated using equation 3.10, where l is the length of the wire, µ0 is the permeability in a vacuum (4π x 10-7 H/m), µris the relative permeability,
r is the wire radius and h, the height above the substrate [41]. Cs=
l2πε0εr(ef f )
ln(2hr ) (3.11)
Self-capacitance of a wire can be calculated using equation 3.11, where ε0 is the
per-mittivity of free space (10-9/36π [F/m]) and εr(ef f ) is the relative dielectric constant of the
dielectric material [41].
Cp =
ε0εr(ef f )A
t (3.12)
The capacitance of the pad can be calculated using equation 3.12 where A is the pad area overlapping the ground plane and t is the dielectric thickness [41].
At high frequency, alternating current tends to avoid flow through the center of a solid conductor, the electric current flows mainly at the ”skin” of the conductor. This phenomenon is called skin effect and it causes the effective resistance of the conductor to increase at higher frequencies where the skin depth is smaller.
δ = √ 1 πσµ0f
(3.13) The skin depth of a round conductor if calculated using equation 3.13 where σ is the conductivity of the wire used and f is the frequency of the signal [41].
R ≈ l
2πδσr (3.14)
Resistance of the wire can be calculated using equation 3.14 [44].
For other shapes than a straight bond wire the equations above need to be adapted. The wire must be divided in segments in order to approximate each segment to a straight wire [41]. Higher number of divisions, reduce the approximation error.
3.2.2
Simulation
As mentioned in the section above, a PCB (presented in figure 3.10) with five pairs of transmission lines adapted for 50 Ω, separated by a distance D of 200 µm, 300 µm, 400 µm, 500 µm and 800 µm was designed. Wire bonding machine available in Instituto de Telecomunica¸c˜oes de Aveiro is not an automated process, it needs an active adjustment which does not allow the user to perform a bonding with a precision of micrometers. For
these reason, bond wire length was measured before the simulation, using a microscope and it is expressed as ”D” plus the distance from the bond to each edge of the correspondent transmission line-i.e., distance between the starting and ending points of bond wire. Table 3.1 collects the measured values of bond wire length. Measurements were performed using a microscope with leica software. Check appendix A.1.
The distance from the bond to the transmission line edge should be the smallest possible but 100 µm was the smallest distance achieved in this experiment.
Figure 3.10: PCB layout for characterization of wire bonding
”D” (µm) Bond wire length (µm)
200 401.4
300 704.7
400 815.2
500 897.1
800 1319.2
Table 3.1: Measured bond wire length
3.2.3
ADS EBOND
In order to simulate the behavior of bond wire connections it was used ”ads bondwires” library available in ADS which includes a component with bond wire shape profile editor (”ads bondwires:EBOND Shape”) where the user is enabled to a create bond wire shape. ”ads bondwires” library also includes standard bond wire shapes. ADS uses the model reviewed in section 3.2.1 but adapted to the bond wire shape.
Bond wire shape used and simulated has the following properties: Radius, 8.75 µm; Conductivity, 4.1 ∗ 107 S; ε
Figure 3.11: ADS 3-dimensional model of EBOND
S21 parameter simulated in ADS electromagnetic simulation using Momentum
Mi-crowave field solver is illustrated in figure 3.12. It is possible to confirm that an increase of bond wire length results in a bandwidth decrease. In this simulation it is possible to conclude that until 8GHz S21 has a value above 0.5 dB for distances ”D” up to 300 µm.
0 2 4 6 8 10 12 Frequency (Hz) ×109 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 Magnitude (dB) TL D=200 TL D=300 TL D=400 TL D=500 TL D=800
3.2.4
Measurement Setup
For measuring S21parameter it was used a PNA-X (N5242A) Vector Network Analyzer
(VNA). A calibration process was performed so the connecting cables between VNA to PCB do not interfere with the results.
Figure 3.13: Setup for measuring S21 parameters
The results could be more accurate if during the calibration process it was considered not only the cables but also the RF connectors. To do so, the PCB should have three more pairs of transmission lines (open circuit, short circuit and a load) with connectors only for calibration purposes.
3.2.5
Results
Measured S21 parameters as a function of the frequency considering five distances ”D”
are illustrated in figure 3.14. As in the simulation, bandwidth decreases with an increase of the distance. Until 4 GHz S21 has a value of 0 dB and it is almost constant. For
distances ”D” up to 300 µm, equivalent to bond wire length up to 700 µm, S21 coefficient
has a magnitude value of 1 dB, which means that almost 80% of the power transmitted is received by the load.
It was noticed at the microscope that bond wires for distances ”D” of 200 µm and 300 µm are more curved than the others, which also has impact in the results once the more curved is the wire, the lower the inductance. The reason is the cancellation of the mutual inductance of the wire segments [45].
0 2 4 6 8 10 12 Frequency (Hz) ×109 -8 -7 -6 -5 -4 -3 -2 -1 0 1 Magnitude (dB) TL D=200 TL D=300 TL D=400 TL D=500 TL D=800
Figure 3.14: S21 parameter measured values.
To evaluate the quality of the simulation it is illustrated in figure 3.15 a comparison between the model simulated and experimental results for a distance ”D” of 200 µm. Despite of having resonant frequencies in the experimental results due to parasitic effects between 4.5 - 5 GHz and 9.5 - 10 GHz, S21 behavior is similar.
0 2 4 6 8 10 12 Frequency (Hz) ×109 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 Magnitude (dB) Simulation values Experimental values
3.3
Conclusion
Two PCBs for testing two photonic integrated circuits were developed in this chapter where it was presented two solutions. One for biasing a PIN diode and other for space optimization of the PCB. The chapter is terminated with a characterization of bond wire S21 parameter as a function of the wire length. First, it was performed a simulation in
Chapter 4
Thermal Packaging
An analysis about thermal packaging of photonic integrated circuits is the scope of this chapter. It is divided in two sections: Thermal Analysis, section 4.1, and Integrated Thermal Sensor, section 4.2.
4.1
Thermal Analysis
In this section, it is presented a study on the thermal interference between active com-ponents like distributed feedback lasers (DFB lasers) and semiconductor optical amplifiers (SOAs). Naturally, the thermal interference is highly dependent on the distance between them.
ANSYS was used to simulate the thermal distribution of DFB lasers and SOAs at different working conditions, also to calculate the safety distance between components. First, it was analyzed the thermal distribution of three architectures used in PICadvanced: a DFB laser, a SOA and a block constituted by a DFB laser followed by a SOA. Afterwards, it was calculated the safety distance between two DFB lasers and two SOAs.
This section is finalized with a list of product design rules (PDRs) regarding the safety distance from active components at different working conditions without thermal interfer-ence.
4.1.1
ANSYS Simulation
Founded in 1970, ANSYS is an Engineering simulation 3-D design software. It reaches a wide variety of areas such as computational fluid dynamics, electronics, semiconductors, embedded software and design optimization [46].
In this work, it was used finite element analysis software ANSYS to simulate the steady-state temperature field distribution [47] under different bias conditions of DFB lasers and SOAs. Steady state analysis was chosen since an observation of temperature distribution regarding a stable working status was the focus of this work[48].
4.1.2
Finite Elements Method
Simple problems solving a complex problem is the basic concept of the finite element analysis [49]. Converting a continuous problem into a discrete problem delivers an approx-imate solution. With an increased discretization, the approxapprox-imate solution approaches the exact solution [4].
4.1.2.1 Procedure of Finite Element Analysis
Generally, a finite element solution may be arranged in the following three steps [4]: 1. Pre-processing:
• Define the analysis system (Steady-state thermal, transient thermal, electrical, ...).
• Define the materials to use and their properties. • Create or import the geometry.
• Assign the materials to the geometry. 2. Solution:
• Set the mesh.
• Set boundary conditions (Forces, temperatures, convection, ...). • Solve the equations.
3. Post-processing:
• Displacements, reaction probes, temperature distribution, deflection plots, ... • Show and analyze the simulation results.
4.1.3
Steady-State Theory
For steady-state heat transfer, the differential equation expressing thermal equilibrium is: [50] ∂ ∂x kxx ∂T ∂x ! + ∂ ∂y kyy ∂T ∂y ! + ∂ ∂z kz ∂T ∂z ! +...q = 0 (4.1)
The corresponding finite element equation expressing equilibrium is: [50][51]
[K]{T } = {Q} (4.2)
Where T is the temperature, K is the heat conductivity and Q is the heat transfer rate for each material.
4.1.4
DFB laser
Figure 4.1: Thermal distribution of a DFB laser
Figure 4.2: Cross-section of a DFB laser
Figures 4.1, and 4.2 illustrate the steady state thermal distribution of a DFB laser in a InP substrate at a room temperature of 40oC. Several heat flow values were applied in a
surface with DFB laser dimensions (280 µm * 220 µm * 4 µm) to simulate a DFB laser in working conditions. Heat flow is a boundary condition of ANSYS representing the power dissipated as heat. Power dissipated is correlated to the DFB laser biasing current and biasing current is correlated to DFB laser output wavelength1, as such, different biasing currents causes different working conditions. Considering that a DFB laser has an optical efficiency of 35%2, 65% of the electrical power injected will be dissipated as heat [49].
Pel= Ibias∗ V (4.3)
1Information provided by PICadvanced. 2Courtesy of PICadvanced.
Channel Ibias (mA) V (V) Pel (mW) P d (mW)
CH1 80 1.6 128.0 83.2
CH2 92.5 1.7 157.3 102.2
CH3 105 1.95 204.8 133.1
CH4 125 2.05 256.3 166.6
Table 4.1: Power dissipated values for DFB laser
Power dissipated values of four channels (four different operation conditions) used are presented in table 4.13.
Figure 4.3: Thermal distribution of a DFB laser as a function of the distance along the X axis considering Pd values calculated in table 4.1 .
Figure 4.4: Thermal distribution of a DFB laser as a function of the distance along the Y axis considering Pd values calculated in table 4.1 .
3I
bias and V values were provided by PICadvanced. Light-Current-Voltage (LIV) curves correlate V
Figures 4.3 and 4.4 represent the thermal distribution along the distance in X an Y directions, respectively. (X and Y directions are represented in the coordinate system of figure 4.1).
As expected, temperature decreases with the distance from the DFB laser center, mean-ing, the higher the distance, the lower the thermal interference. Different dissipated power values originate different thermal gradient values (∇T), higher dissipated powers result in higher gradient values -i.e., a dissipated power of 166.6 mW results in a temperature of 44.7oC in the DFB laser centre (∇T =4.7 oC)4 and for 83.2 mW, results in a ∇T =2.4oC. Thermal distribution of X axis (figure 4.3) and Y axis (figure 4.4) are different since the DFB laser surface is not squared, as such, the smaller edge (X axis) will have a faster thermal transition.
4.1.4.1 Interference Between Two DFB Lasers
Figure 4.5: Thermal distribution of two DFB lasers.
Figure 4.6: Thermal interference between two DFB lasers separated by 1500µm considering several Pd values in each DFB .
Figure 4.7: Thermal interference between two DFB lasers separated by 750µm considering several Pd values in each DFB .
Figure 4.8: Thermal interference between two DFB lasers separated by 200µm considering several Pd values in each DFB .
Figure 4.5 shows a thermal distribution of two DFB lasers with different power dis-sipated values (the one on the left with 83.2 mW and the one on the right with 166.6 mW) separated by a distance ”D” from each DFB edge. Figures 4.6, 4.7 and 4.8 illustrate three cases where it was chosen three different distances between DFB, based on thermal distribution presented in the section 4.1.4. It is also illustrated different power dissipated values.
Thermal interference is defined as a naturally occurring process in which temperature differentials can interfere with the operation of the device. In figure 4.6 each laser has no thermal interference on his neighbor considering that the middle point between them is at room temperature (40oC) on the contrary, figure 4.8 has thermal interference. Thermal
of each one, in figure 4.6 there is no interference as result of the long distance but in figure 4.7 the interference depends on the power used, i.e- both lasers dissipating 166.6 mW has a bigger interference than at 83.2 mW.
4.1.4.2 Safety Distance Between Two DFB lasers
Thermal interference between two DFB lasers as a function of their distance is char-acterized in figure 4.9b as result of a study on thermal interference between two DFB lasers working in CH45, see figure 4.9a. The DFB simulated has a wavelength drift limit of
0.16 nm for a bandwidth of 40GHz6, also, wavelength drift occurs due to thermal variations
with a proportion of 0.094 nm/oC [33], consequently it was calculated a maximum gradient of 1.7oC considering a drift of 0.16 nm in the wavelength.
(a) Several distances between DFBs. (b) Safety distance between DFBs.
Figure 4.9: Safety distance between two DFB lasers.
4.1.5
Semiconductor Optical Amplifier
Figure 4.10: Thermal distribution of a SOA.
5Ch4 is the working condition with the highest power dissipation used in PICadvanced. 6Information provided by PICadvanced.
Figure 4.11: Cross-section of SOA.
For simulating the SOA it was used the same method as the DFB but with SOA dimensions (234 µm * 125 µm * 4 µm), however the power dissipated is different. To calculate the power dissipated in the SOA it was used the equation 4.4 adapted from [52], where Pd is the power dissipated as heat, Pel is the electrical power injected to the device
and ∆Prad is the optical power [52]. ∆Prad is the difference between Pout and Pin of the
SOA-i.e., optical gain of the amplifier.
Power dissipated values are presented in table 4.2.7
Pd= Pel− ∆Prad (4.4)
Ibias (mA) V (V) Prad (mW) Pel (mW) Pd (mW)
20 0.20 0.07 4 3.9
40 0.75 0.10 30 29.9
60 1.25 0.09 75 74.9
80 1.65 0.06 132 131.9
100 1.90 0.03 190 190.0
Table 4.2: Power dissipated values for SOA
7 I
bias, V and Prad values were provided by PICadvanced based on SOA operation conditions. LIV
Figure 4.12: Thermal distribution of a SOA as a function of the distance along the X axis considering Pd values calculated in table 4.2 .
Figure 4.13: Thermal distribution of a SOA as a function of the distance along the Y axis considering Pd values calculated in table 4.2
Figures 4.12 and 4.13 illustrate the thermal distribution in X and Y directions in a SOA (X and Y directions are represented in the coordinate system of figure 4.10) for different power dissipated values. The conclusions about SOA are equivalent as the ones reported for DFB laser, the highest the power dissipated, the highest the thermal gradient. Also, thermal interference decreases with the distance from the center of the SOA. X and Y thermal distribution are different due to the physical dimensions, Y edge is smaller so the thermal transition is faster.
4.1.5.1 Interference Between Two SOAs
Figure 4.14: Thermal distribution of two SOAs.
Figure 4.15: Thermal interference between two SOAs separated by 1200µm considering several Pd values in each SOA .
Figure 4.16: Thermal interference between two SOAs separated by 600µm considering several Pd values in each SOA .
Figure 4.17: Thermal interference between two SOAs separated by 300µm considering several Pd values in each SOA .
Figure 4.14 represents a thermal distribution of two SOAs for Pd = 29.9 mW and
Pd = 74.9 mW, respectively. Thermal interference between two SOAs as a function of the
distance between the border of each optical amplifier along X axis is exposed in figures 4.15, 4.16 and 4.17. Once again, thermal interference is proportional to the distance between SOAs and to the power dissipated value.
4.1.5.2 Safety Distance Between Two SOAs
To calculate the safety distance between two SOAs it was simulated several distances between their edges considering a dissipated power of 74.9 mW8, see figure (4.18a). Dis-tance between SOAs as a function of the thermal interference (minimum point between SOAs) is plotted in figure 4.18b.
(a) Several distances between SOAs. (b) Safety distance between SOAs.
Figure 4.18: Safety distance between two SOAs.
4.1.6
DFB Laser With Semiconductor Optical Amplifier
Figure 4.19: Thermal distribution of DFB laser + SOA.
874.9 mW is the highest value of power dissipated in a SOA used in PICadvanced at optimum working
Figure 4.20: Cross-section of DFB laser + SOA.
Figure 4.22: Thermal distribution of DFB laser + SOA along the Y axis.
In this section, a thermal analysis of a DFB followed by a SOA is presented. Figures 4.19 and 4.20 illustrate an ANSYS steady state thermal simulation. Thermal distribution considering several power dissipated values for each device is presented in figures 4.21 and 4.22, where the distance reference of the graphic is the geometric center of the block DFB+SOA. DFB power dissipated is greater than SOA, along X axis (figure 4.21) ∇T at the left side of the graphic will be greater than ∇T at the right side.
4.1.7
Thermal Design Rules
By analyzing the data collected in sections 4.1.4 and 4.1.5 it is possible to establish some thermal design rules (TDRs). The majority of PIC designs only place the devices in the Y axis since in X axis is situated the input and output optical signals, furthermore connected to waveguides. Therefore, only the distance in Y axis has relevance.
(a) DFB. (b) SOA. (c) DFB+SOA.
Figure 4.23: Block diagram of devices simulated
The list below provides information about the safety distance between a passive com-ponent and one of the three active comcom-ponents: DFB, a SOA and DFB+SOA.
1. DFB • CH1
– Safety distance of 460µm, at least.9
• CH2
– Safety distance of 495µm, at least.9
• CH3
– Safety distance of 543µm, at least.9 • CH4
– Safety distance of 577µm, at least.9 2. SOA
• P dSOA = 3.9mW
– Safety distance of 73µm, at least.9 • P dSOA = 29.9mW
– Safety distance of 290µm, at least.9
• P dSOA = 74.9mW
– Safety distance of 436µm, at least.9
3. DFB+SOA
• P dDF B = 102.2mW and P dSOA= 29.9mW
– Safety distance of 525µm, at least.9
• P dDF B = 166.6mW and P dSOA= 29.9mW
– Safety distance of 598µm, at least.9
• P dDF B = 166.6mW and P dSOA= 74.9mW
– Safety distance of 630µm, at least.9
The following list provides information about the safety distance between active com-ponents such as: a DFB and a SOA.
1. Two DFBs
• It is required a safety distance of 310µm, at least.10
2. Two SOAs
• It is required a safety distance of 753µm, at least.9
9Valid for a thermal interference of 0.1oC. This value was suggested by PICadvanced 10Valid for a thermal interference of 1.6oC.
4.2
Integrated Thermal Sensor
As mentioned in the section 2.7, the TEC controls the temperature in a PIC by applying a voltage in the Peltier which leads to a thermal gradient. A thermal sensor is needed to give feedback to the TEC.
To get an accurate measure it is needed to have an integrated thermal sensor with small dimensions in the vicinity of the PIC.
4.2.1
Pt Ti Sensors
It was produced a chip (figure 4.24) including several sensors, squared with 1 mm side. Different designs were used in order to study the best approach. By varying the length and the width, it is possible to obtain different values of resistance and sensitivity. The sensor nomenclature (TSW10L60000) stands for: Thermal sensor with a width of 10µm and a length of 60 000µm. The chip was developed in INESC-MN using a process of lithography and consists in a silicon substrate with Platinum-Titanium (Pt Ti) sensors [53].
Figure 4.24: Silicon chip design
4.2.2
Setup
To characterize the sensors, the setup illustrated in figures 4.25 and 4.26 was assembled. Keithley 2400-C11injects a bias current of 1 mA in the sensor and reads directly the value of the impedance. Considering the dimensions of each sensor, DC probes are used to help the connection between the sensor pad and the Keithley. Controlling the sensor temperature was possible using the TEC.
11Keithley 2400-C is a source meter capable of provide precision voltage and current sourcing as well as
