Universidade de Aveiro Departamento deElectr´onica, Telecomunica¸c˜oes e Inform´atica, 2019
Jo˜
ao
Arantes
Test of Integrated Optical Circuits for PON
Networks
Teste de Circuitos ´
Oticos Integrados para Redes
PON
Universidade de Aveiro Departamento deElectr´onica, Telecomunica¸c˜oes e Inform´atica, 2019
Jo˜
ao
Arantes
Test of Integrated Optical Circuits for PON
Networks
Teste de Circuitos ´
Oticos Integrados para Redes
PON
Disserta¸c˜ao apresentada `a Universidade de Aveiro para cumprimento dos requesitos necess´arios `a obten¸c˜ao do grau de Mestre em Engenharia Electr´onica e Telecomunica¸c˜oes, realizada sob a orienta¸c˜ao cient´ıfica do Professor Doutor M´ario Lima, Professor do Departamento de Electr´onica e Telecomunica¸c˜oes da Universidade de Aveiro e do Engenheiro Francisco Rodrigues da PICadvanced S.A.
o j´uri / the jury
presidente / president Professor Doutor Telmo Reis Cunha
Professor Auxiliar da Universidade de Aveiro (por delega¸c˜ao da Reitora da Univer-sidade de Aveiro)
vogais / examiners committee Doutor Orlando Jos´e dos Reis Fraz˜ao
Professor Auxiliar Convidado da Faculdade de Ciˆencias da Universidade do Porto Professor Doutor M´ario Jos´e Neves de Lima
agradecimentos / acknowledgements
Este trabalho conclui uma fase importante da minha vida, e como tal, gostaria de apresentar uma nota de agradecimento ´as pessoas que me apoiaram no decorrer da mesma. Queria come¸car por agradecer aos meus orientadores, ao Prof. Doutor M´ario Lima e Eng. Eng. Francisco Rodrigues pela disponibilidade e conhecimento transmitido. Um agradecimento ao Eng. Hugo Neto, Eng. Ana Maia, Eng. Carla Rodrigues e Eng. Guilherme Cabral com quem mais trabalhei no decorrer desta disserta¸c˜ao. Um agradec-imento a todos os elementos da PICAdvanced por toda a hospitalidade e disponibiliza¸c˜ao de recursos durante esta minha estadia, n˜ao s´o durante a execu¸c˜ao da disserta¸c˜ao, mas tamb´em pelos dois est´agios que realizei, nos quais aprendi imenso. Por fim, eu grande obrigado `a minha fam´ılia que me apoiou durante todo o meu percurso acad´emico.
Este trabalho financiado pelo Fundo Europeu de Desenvolvimento Re-gional(FEDER), atravs do Programa Operacional Regional do Centro (CEN-TRO2020) do Portugal 2020 [Projeto HeatIT com o n 017942 (CENTRO-01-0247-FEDER-017942)].
Palavras chave Circuito ´otico integrado (PIC), teste de PIC , PON Resumo
No decorrer das ´ultimas duas d´ecadas a Internet tem sofrido uma grande revolu¸c˜ao. A quantidade de servi¸cos e aplica¸c˜oes que surgiram desta revolu¸c˜ao criaram a necessidade de obter mais largura de banda e maiores velocidades. As ´unicas tecnologias capazes de satisfazer estas condi¸c˜oes s˜ao as comunica¸c˜oes ´oticas. A tecnologia que ´e usada atualmente para satisfazer todas estas necessidades ´e chamada de Passive Optical Net-work(PON). Existem algumas evolu¸c˜oes desta tecnologia a serem utilizadas atualmente, nomeadamente a GPON ou EPON. Novas evolu¸c˜oes de PON est˜ao a ser desenvolvidas, nomeadamente a Next Generation Passive Optical Network 2(NG-PON2). Esta tecnologia multiplexa servi¸cos diferentes em diferentes comprimentos de onda, tornando o seu desempenho mais eficaz. Um dispositivo de grande importˆancia neste ramo s˜ao os Photonic Inte-grated Circuit(PIC). A tecnologia integrada tem vindo a substituir a ´otica convencional, uma vez que possiblita a integra¸c˜ao de v´arias funcionalidades ´
oticas num ´unico chip, poupando energia e espa¸co. Com o obectivo de desenvolver sistemas ´oticos de futura gera¸c˜ao, este trabalho pretende testar PICs de maneira que estes possam ser integrados em equipamentos ´oticos, como por exemplo no Optical Line Terminal(OLT) com func¸c˜oes tais como transmissor/receptor situado na esta¸c˜ao da operadora de telecomunica¸c˜oes ou no Optical Network Unit(ONU) que se situa na localiza¸c˜ao do utilizador. Para poss´ıvel integra¸c˜ao dos PICs em redes ´oticas, estes deve ser testados de modo a garantir que todas as fun¸c˜oes se realizem sem anomalias. Para tal, estes componentes encontram-se em teste nos nossos laborat´orios. Estes trabalho, consistiu na realiza¸c˜ao de testes a circuitos integrados ´
oticos, bem como a otimiza¸c˜ao das t´ecnicas e procedimentos adequados para os mesmos. Em primeiro lugar, ´e apresentado um resumo te´orico acerca das redes ´oticas e PIC. De seguida, s˜ao apresentados cuidados de realiza¸c˜ao de testes, bem como procedimento de prepara¸c˜ao dos mesmos. Por fim s˜ao realizados testes aos PIC que representam o maior volume em trabalho deste documento.
keywords Photonic Integrated Circuit (PIC), PIC testing, PON Abstract
For the last two decades, the Internet has been target of a technological revolution. The amount of new services and applications that came up with this revolution demanded the search to obtain more bandwidth and bigger data rates. The only technologies capable of satisfying these conditions are the optical communications. The current technology that is capable to satisfying all these needs is the Passive Optical Network(PON). There are some variations of this technology currently being used such as the GPON and EPON. New evolutions of PON are being developed, such as the Next Generation Passive Optical Network 2(NG-PON2) This technology multi-plexes different services into separated wavelengths, making its performance more effective. One tool of great matter in this business is the Photonics In-tegrated Circuit(PIC). The photonic inIn-tegrated technology has been taking over the conventional optical equipment because it allows the integration of several functionalities into one single chip, saving space and energy. Having in mind the objective of developping next generation optical communica-tion systems, the work presented in this document intends to test PIC in way that they can be used in optical equipment, as for example the Optical Line Terminal(OLT) which has functions of transmitter/receiver situated at the operator’s station, and the Optical Network Unit(ONU) situated at the user’s location. To make it possible for PIC to be integrated in optical networks these must be tested in order to assure that they perform their functions without any anomalies happening. For such reason, these PIC are at our labs, read to be tested. This work, consisted of the execution of tests to PIC as well as the optimization of the techniques and adequate proce-dures. In the first place, it is presented an overview of optical networks and PIC. Then the do’s and dont’s of testing PIC as well as the procedure and preparations of these tests. At last, the tests to the PIC will be performed which represents most of the work shown in this document.
Contents
Contents i
List of Figures iii
List of Tables vii
Acronyms ix
1 Introduction 1
1.1 Overview and Motivation . . . 1
1.2 Objectives . . . 1
1.3 Structure . . . 2
1.4 Contributions . . . 2
2 PON Networks and Optical Components 3 2.1 PON Networks . . . 3
2.1.1 PON Evolution . . . 4
2.2 Photonic Integrated Circuits . . . 6
2.3 Optical Components . . . 8
2.3.1 Lasers . . . 8
2.3.2 Photodetector . . . 11
2.3.3 MMI . . . 13
2.3.4 SOA . . . 14
3 Experimental Procedures and Tests 17 3.1 Equipment and Chip Preparation . . . 17
3.1.1 Fiber cleaving . . . 17
3.1.2 Testing precautions . . . 19
3.1.3 Fiber Alignment . . . 19
3.1.4 TEC - Temperature Controller . . . 21
3.1.5 LDC - Laser Diode Controller . . . 22
3.1.6 PIC testing procedure . . . 23
3.1.7 Rigol Automatization . . . 24
3.2 Experimental Tests . . . 25
3.2.1 Electrical Procedure . . . 25
Design 1 - Architecture 1 . . . 27
Design 1 - Architecture 5 . . . 39
3.2.2 Optical Procedure . . . 43
Design 1 - Architecture 4 . . . 44
Design 2 - Architecture 2 . . . 50
4 Conclusion and Future Work 63 4.1 Conclusions . . . 63
4.2 Future Work . . . 64
Bibliography 65 4.4 Appendices: . . . 69
List of Figures
2.1 Architecture of a TDM-PON in (a) and WDM-PON in (b) . . . 4
2.2 NG-PON2 Architecture . . . 6
2.3 Microscopic view of a PIC . . . 7
2.4 Data capacity per chip trend in commercial optical networks . . . 8
2.5 Cross-sectional structure of a Fabry-Perot Laser . . . 9
2.6 Example of Wavelength variation vs laser temperature . . . 10
2.7 Example of Optical Power variation vs Laser Temperature . . . 10
2.8 Light absortion . . . 11
2.9 Variation of responsivity with wavelength and material . . . 12
2.10 PIN Photodiode Structure . . . 12
2.11 Multimode Interferometer Structure . . . 13
2.12 Structure of a SOA . . . 14
2.13 a) Gain vs Current in SOA b) Gain vs Input Power in SOA . . . 15
2.14 Evolution of the gain as a function of the output power and the SOA current 15 2.15 a) Gain vs Wavelength for different input powers b) Output power vs Wave-length for different input powers . . . 16
3.1 Fiber Cleaving Equipment . . . 18
3.2 ThorLabs 3axis positioner MBT616D at PICAdvanced’s Lab . . . 20
3.3 Fiber Alignment of optical fiber into a PIC . . . 20
3.4 User Interface of TED200C TEC Controller . . . 21
3.5 User Interface of LDC200C TEC Laser Diode Controller . . . 22
3.6 Pin port configuration of LDC . . . 23
3.7 LDC configuration . . . 23
3.8 Rigol Matlab Application - User Interface . . . 24
3.9 Integrated Fast Current Mirror - DS3920 . . . 25
3.10 Electrical Tests Setup . . . 26
3.11 Block diagram of architecture 1 - Design 1 . . . 27
3.12 Block diagram of architecture 1b - Design 1 . . . 28
3.13 DFB1 OP vs DFB1 Current . . . 28
3.14 Block diagram of architecture 1c - Design 1 . . . 29
3.15 DFB2 OP vs DFB2 Current . . . 29
3.16 DFB1+2 OP vs DFB1/2 Current - Measured vs Expected . . . 30
3.17 DFB1 OP vs DFB1 Current for several Temperatures . . . 31
3.18 Slope drop of Optical Power with Temperature . . . 32
3.20 Block diagram of architecture 2a - Design 1 . . . 33
3.21 PIN3/4 OP vs DFB3 current - SOAs OFF . . . 34
3.22 Block diagram of architecture 2 - Design 1 . . . 34
3.23 PIN4 OP vs SOA1 Current at 50◦C, DFB3=75mA . . . 35
3.24 Schematic of architecture 2 - Design 1 . . . 35
3.25 PIN4 OP vs SOA2 Current, DFB3=75mA, T=50◦C . . . 35
3.26 PIN4 OP vs SOA1/2 Current at 50◦C, DFB3=75mA . . . 36
3.27 PIN3/4 OP vs SOA1/2 Current at 25◦C, DFB3=75mA . . . 36
3.28 PIN3/4 OP vs SOA1 Current for several DFB3 currents at 25◦C . . . 37
3.29 PIN3/4 OP vs SOA1 Current (65-95)mA at 20◦C and 25◦C, DFB3=95mA . . 38
3.30 PIN3/4 OP vs DFB3 Current for several SOA1 Currents at 25◦C . . . 38
3.31 Block diagram of architecture 5 - Design 1a . . . 40
3.32 PIN8/10/11 OP vs DFB5 Current for several SOA3 currents at T=15◦C . . . 40
3.33 PIN8/10/11 OP vs DFB5 Current for several SOA4 currents at T=15◦C . . . 41
3.34 PIN8/10/11 OP vs DFB5 Current for several SOA3/4 currents at T=15◦C . 41 3.35 Setup of the optical tests . . . 43
3.36 Block diagram of architecture 4 - Design 1 . . . 44
3.37 OP vs DFB4 Current Sweep for Several Temperatures . . . 44
3.38 Mode Hoping on DFB4 at 25◦C . . . 45
3.39 DFB4 OP vs DFB4 Current Sweep for Several Temperatures with Matching Gel 46 3.40 Mode Hoping on DFB4 at 25◦C and 20◦C with matching gel . . . 46
3.41 DFB4 OP vs DFB4 Current Sweep for Several Temperatures measured on the EAM I/O Port . . . 47
3.42 Wavelength vs Temperature variation with a DFB4 current of 100mA . . . . 48
3.43 Repeatibility test setup . . . 48
3.44 Optical Power per sample for 300 samples . . . 49
3.45 Interval density of optical power measured for 300 samples . . . 49
3.46 Diagram block of Architecture 2 MMI4x4 - Design 2 . . . 50
3.47 OP vs Wavelength for each input/output combination of the MMI4x4 - L band 51 3.48 OP vs Wavelength for each input/output combination of the MMI4x4 - C band 51 3.49 Diagram block of Architecture 2 MMI3x3 - Design 2 . . . 52
3.50 OP vs Wavelength for each input/output combination of the MMI3x3 - L band 53 3.51 OP vs Wavelength for each input/output combination of the MMI3x3 - C band 53 3.52 OP vs Wavelength for each input/output PIN combination of the MMI4x4 - L band . . . 55
3.53 OP vs Wavelength for each input/output PIN combination of the MMI4x4 - C band . . . 55 3.54 OP vs Wavelength for each input/output PIN combination of the MMI3x3 - L
4.5 PIN8/10/11 OP vs DFB5 Current for several SOA4 currents at 35◦C . . . 71 4.6 PIN8/10/11 OP vs DFB5 Current for several SOA3/4 currents at 35◦C . . . 71
List of Tables
3.1 Equipment used for Cleaving of the Optical Fiber . . . 18
3.2 Functions of the User Interface of TED200C TEC Controller . . . 22
3.3 Functions of the User Interface of TED200C TEC Controller . . . 22
3.4 Equipment used for the Electrical Procedure Tests . . . 26
3.5 PIN1 MOP at saturation points . . . 28
3.6 DFB2 MOP at saturation points . . . 30
3.7 PIN1/2 MOP at saturation points - Measured vs Expected . . . 30
3.8 DFB1 MOP at saturation points . . . 31
3.9 PIN1/2 MOP at saturation points for several temperatures . . . 32
3.10 PIN3/4 MOP at saturation points . . . 36
3.11 MOP PIN3/4 vs SOA1 Current for several DFB3 currents at 25◦C . . . 37
3.12 PIN3/4 MOP vs SOA1 Current (65-95)mA, DFB3=95mA, at 20◦C and 25◦C 38 3.13 PIN3/4 MOP for several SOA1 Currents at 25◦C . . . 39
3.14 PIN8/10/11 MOP at saturation points on Figure 3.32, 3.33 and 3.34 . . . 42
3.15 ∆OP between PIN8,10,11 . . . 42
3.16 Equipment used for the Optical Procedure Tests . . . 43
3.17 MOP at saturation points . . . 45
3.18 MOP at saturation points with Matching Gel . . . 46
3.19 MOP at saturation points measured in the EAM I/O Port . . . 47
3.20 Numerical OP analysis on Repeteability’s test results . . . 49
3.21 Maximum OP for each Input/Output SSC - MMI4x4 - C+L Band . . . 52
3.22 Maximum OP for each Input/Output SSC - MMI3x3 - C+L band . . . 54
3.23 Maximum OP for each Input/Output PIN - MMI4x4 - C+L band . . . 56
3.24 OP difference between PINs for each Input/Output PIN - MMI4x4 - C+L band 57 3.25 Maximum OP for each Input/Output PIN - MMI3x3 - C+L band . . . 58
3.26 OP difference between PINs for each Input/Output PIN - MMI3x3 - C+L band 58 3.27 Enumeration of losses from the Input SSC to the output SSC/PIN - MMI3x3 59 3.28 Gap between theoretical estimation and pratical OP for each Input/SSC or PIN - MMI3x3 - C+L band . . . 60
3.29 ∆OP between SSCs and PINs - MMI3x3 . . . 60
3.30 Gap between theoretical estimation and pratical OP for each Input/SSC or PIN - MMI4x4 - C+L band . . . 61
3.31 ∆OP between SSCs and PINs - MMI4x4 . . . 61
4.1 MOP at saturation points for PIN8/10/11 on Figure 3.32, 3.33 and 3.34 . . . 72
Acronyms
Al Aluminium. 7
APON Asynchronous Transfer Mode Passive Optical Network. 4, 5
As Arsenide. 7
ATM Asynchronous Transfer Mode. 4, 5 BPON Broadband Passive Optical Network. 4, 5 CSMA/CD Carrier Sense Multiple Access with Collision
Detection. 5
DFB Distributed FeedBack Laser. 7, 9, 22, 23, 25, 27, 28, 33, 39, 45, 47, 63, 64
DML Directly Modulated Laser. 7
EAM Electro Absortion Modulator. vii, 47, 64 EDFA Erbium Doped Fiber Amplifier. 14 EPON Ethernet Passive Optical Network. 1, 4, 5 FSAN Full Service Access Network. 3
FTTB Fiber-to-the-Building. 3 FTTH Fiber-to-the-Home. 1, 3 FTTx Fiber-to-the-x. 3
Ga Gallium. 7
Gbps Giga-bit-per-second. 1, 5, 7
GPON Gigabit Passive Optical Network. 1, 4, 5 IC Integrated Circuit. 25
IEEE Institute of Electrical and Electronics Engi-neers. 4, 5
InP Indium Phosphide. 7, 8
ITU International Telecommunication Union. 4, 5 Laser Light Amplification by Stimulated Emission
LDC Laser Diode Controller. iii, 23 LED Light Emitting Diode. 22 Mbps Mega-bit-per-second. 5 MMF Multi Mode Fiber. 19
MMI Multimode Interference. 13, 50, 51, 53, 55, 59, 61, 63, 64
MOP Max Optical Power. vii, 28, 30–32, 36–39, 42, 45–47, 72
NG-PON Next Generation Optical Passive Network. 5 NG-PON2 Next Generation Optical Passive Network 2.
1, 5, 6, 8, 56, 63
OLT Optical Line Terminal. 1–3, 5 ONU Optical Network Unit. 1–6
OP Output Power. iii–v, vii, 20, 27–32, 34–42, 44–61, 63, 64, 69–71
OSA Optical Spectrum Analyzer. 17, 20, 43, 45, 47
P Phosphorus. 7
P2MP Point-to-Multipoint. 1, 5
PCB Printed Circuit Board. 19, 23, 25, 27
PIC Photonic Integrated Circuit. iii, 1, 2, 6, 7, 9, 19–23, 27, 47, 58, 59, 64
PID Proportional Integral Derivative Controller. 21, 22
PIN p-i-n Photodiode. iv, vii, 25, 27, 33, 36, 39, 40, 42, 50, 54–61, 63, 64
PON Passive Optical Network. 1–5, 50, 63, 64 POS Passive Optical Splitter. 3
SCPI Standart Commandas for Programmable In-struments. 24
Si Silicon. 7
Si3N4 Silicon Nitride. 7 SiO2 Silicon Dioxide. 7
TEC Temperature Controller. iii, vii, 21, 22, 34– 37, 39, 50, 64
TWDM Time-Wavelength Division Multiplexing. 5 WDM Wavelength Division Multiplexing. 3–5, 7, 13 XG-PON 10 Gigabit Passive Optical Network. 5
Chapter 1
Introduction
1.1
Overview and Motivation
Nowadays, all internet related activities like phone calls, movie downloads, messaging are at some point converted into a light signal that can travel half the world through optical fiber just to reach its destination [1] . These fiber-optic communications systems have been developed since the 1980’s and have become the number one choice of Internet distribution of information and services due to its capabilities. Optical fiber communication systems ensure cost-effective network traffic scaling, opening room for future network peers and ease access. This access is based on the P2MP and FTTH concepts. The Passive Optical Network(PON) is one system based on the FTTH concept that has showed reliable distribution and network flexibility with low-cost components. From there, other PON Networks have appeared as result of the need for more bandwidth, which the amount of services and rising internet applications had demanded. The Next Generation Passive Optical Network(NG-PON2) is the most recent PON Network variation in development and will allow 40Gbps both up and downstream [2].
Integrated Photonics became a topic of great matter as the PON Networks arise. Mono-lithic integration allowed the implementation of several functionalities in one single chip, reducing dimensions and costs. These functionalities include couplers, filters, multiplex-ers/demultiplexers, SOA amplifiers, phase modulators, polarization converters, among oth-ers [3].
Two PIC were due to testing in our lab. This work has in sight to test these PIC and prove they are working as expected. The setup of the equipment used for the experiments is an important factor and will be conducted according to a set of norms.
1.2
Objectives
• Provide a summary on the past, current and future PON Networks as well as the PIC and its components;
• Study conduct and preparation of optical tests and testbenchs associated with it; • Perform tests on 2 PIC;
1.3
Structure
This document is organized in 4 main chapters including the introductory one. The document is organized as follows:
• Chapter 2 - PON Networks and Optical Components presents an overview on PON Networks from the past to the present and its development towards the future. In the second part, there is an theorethical approach on PIC and its components which will serve as fundamentals to support the tests performed in Chapter 4
• Chapter 3 - Experimental Procedures and Tests reunites a group of tasks and equipment handling required to perform tests adequately. Then a set of tests will be performed on 5 architectures belonging to 2 PIC.
• Chapter 4 - Conclusions and Future Work provides a summary on the conclusions achieved throughout the document and on the tests performed. In the future work, it is suggested options of giving continuation to the work performed in this document as well as other paths to explore.
1.4
Contributions
• Execution of tests to experimental PIC for integration in OLT and/or ONU; • Creating of an app for data gathering in PIC testing and facilitate testing.
Chapter 2
PON Networks and Optical
Components
This chapter is separated into 3 parts. It has the objective to approach all the matters that are relevant to the realization of the work that will be performed in chapter 3. This chapter’s information serves as the foundations that will be necessary to theoretically support the work present ahead in this document, as referred chapter 3.
Section 2.1 approaches the history of the PON Networks and its impact in the different regions and what reasons led the technologies to take the course that they took. In Section 2.2 it is described the Photonic Integrated Circuit. It is of great importance to approach this theme, once it is the matter of focus in this all document and constitutes a technology that is in fast development and has a great impact in the communication systems. It will be used for the practical part of this work. In Section 2.3, it is approached some of the optoelectronics components that are implemented in the PIC. Also, it is explained how each of these monolithic integrations are meshed in the PIC.
2.1
PON Networks
PON Networks are passive optical networks whose objective is to allow a network dis-tribution from a telecommunication station to an end-user. PON Networks first started to appear after the FSAN(Full Service Access Network) studied the possibility of network dis-tribution to end-users via optical fiber structures [4]. These structures are often denominated by FTTx structures or Fiber-to-the-x. FTTH refers to Fiber to the Home and FTTB refers to larger buildings or companies. FTTx networks are mostly composed by passive components. The main components are OLT(Optical Line Terminal), located in the operator station, the ONU(Optical Network Unit), located at the destination, either it be a building or a neigh-bourhood. These are the two only non-passive components in the network. The OLT is responsible of controlling the data flow to and from the ONUs. Another important compo-nent in the PON is the POS(Passive Optical Splitter) which is responsible for the distribution of the fiber as well as the power splitting in-between the OLT and the ONU.
Protocol wise, there are several multiplexing techniques that can be implemented in optical fiber PON systems [5]. Due to the need of optimization and signalization of data traffic in the network, WDM and TDM techniques are implemented in PON.
Figure 2.1: Architecture of a TDM-PON in (a) and WDM-PON in (b) [6]
In TDM(Time Division Multiplexing)(Figure 2.1(a)), each node sends the data syn-chronously. This is a positive factor in order to signalize data traffic and avoid data collision. The data is sampled in a time windows with a bit duration less than or equal to 1/N of the original time window, where N is the amount of of existing nodes, or in this matter, number of ONUs. TDM is a very popular technique due to its low cost advantages and flexibility to accommodate present and new costumer demands [7, 8].
In the WDM access(Figure 2.1(b)), the available bandwidth is separated into single wave-lengths. A single wavelength is assigned to each ONU, guaranteeing privacy for every service or end-user. To this advantage, it is also added the high capacity of the network, high bit-rate and the protocol transparency, hence different protocols can opebit-rate in distinguished bands [6, 7, 9, 10].
2.1.1 PON Evolution
Over the past decade several PON-based networks were developed under the supervision of the IEEE and the ITU. These entities had in mind the standardization of norms and protocols for network distribution via optical fiber. The four main PON networks devel-oped in the past years are the APON(Asynchronous Transfer Mode), BPON (Broadband-PON), GPON(Gigabyte-PON) EPON(Ethernet-PON). The first three perform based on Asynchronous Transfer Mode ATM [2].
The APON was one of the first networks. However, as improvements were applied and the network was perfected, it was later ratified as BPON by the ITU, as G.983.1. A APON/BPON provides an upstream bitrate from the ONU to the OLT of 155Mbps, with a wavelength of 1300nm and a downlink bitrate of 622Mbps with a wavelength of 1550nm, from the OLT to the ONU [4, 11].
With the revolution of digital era, internet started to have an important role around the globe and therefore there was a demand for data transfer to reach higher levels. At this point, the EPON came into play, allowing a PON-based network that carries data traffic enclosed in Ethernet frames. It was ratified as IEEE 802.3av standard.
EPON provides an upstream rate of 1Gbps with a wavelength of 1310nm and a down-stream rate of 1Gbps with a wavelength of 1490nm. There are two EPON configurations. One of them integrates CSMA/CD protocol and the other one allows full-duplex traffic by using P2MP(Point-to-Multipoint) connections. These configurations consolidated the efficiency of EPON face to the APON/BPON. EPON is widely deployed in Asia [2, 12].
GPON is a PON protocol that appeared from the need of higher bitrate, that the EPON wouldn’t offer. It allows an upstream bitrate of 1.244Gbps with a wavelength of 1310nm and a downstream of 2.488Gbps with a wavelength of 1490nm. EPON and GPON are the two most common PON architectures in the market in the current days and have similar principles in terms of framework and applications, however EPON still works based on ATM. On the other hand, GPON can support TDM, Ethernet, ATM, shared line, wireless extension, among others. GPON is implemented in North America, Europe, Middle East [2, 13].
In 2010, the ITU standardized XG-PON as G.987.1,2 and 3. It came up as the solution to match the need for more bandwidth, that the 2.5Gbps from the GPON couldn’t satisfy. The XG-PON provides a upstream bitrate of 2.5Gbps with an increased band of [1575-1580]nm and 10Gbps for downstream with a band of [1260-1280]nm [2, 13].
The XG-PON is the bridge towards the NG-PON (Next Generation-PON) that has in sight to provide 10Gbps in both upstream and downlink [2].
The most recent PON network in development is the NG-PON2 and has in sight to perfect the previous PON networks. By using TWDM multiplexing technique, it is possible to increase the system performance, reduce power consumption and cost. [2]. TWDM is capable of keeping the capacity of a network from the TDM and the amount of wavelengths from the WDM. NG-PON2 provides a rate of 40Gbps both up and down-stream, divided by 4 10Gbps channels. As of the spectrum range the upstream is in the [1524-1544]nm region and the downstream at the [1596-1603]nm region [2].
Figure 2.2: NG-PON2 Architecture [2]
Figure 2.2 features an example of the NG-PON2 architecture, in which the ONUs are equipped with tunnable lasers. Filters allow wavelength compliance, and therefore wavelength mobility. Multiplexers combine 4 wavelengths on single fiber [14].
Figure 2.3: Microscopic view of a PIC [17]
By using optical WDM(Wavelength Division Multiplexing) technology it is possible to access the enormous optical bandwidth of a fiber which overcomes electrical bandwidth limi-tations of transmitter and receiver. This increases the data throughout point-to-point systems without need of very expensive high-speed electronics [18].
PIC are a promising approach to handle the quicky growing data traffic in the near future where pure copper based electronic will fail to satisfy the requirements of bandwidth and distance [19]. PIC could drastically reduce packaging cost, enhance power budget by suppressing loss optical couplings, and lower critical power consumption by sharing Peltier coolers among several functionalities [15]. The integration of several functionalities on the same opto-electronic chip is given the name of monolithic integration [15].
As of fabrication materials of PIC, the most common choices are Si(Si), Indium Phos-pide(InP), Silicon Nitrite(Si3N4), Silicon Dioxide(SiO2), since they have the highest potential for mass-market applications [20, 21].
Components of PIC are composed of elements that belong to the III and IV column of the Mendeleev’s table, such as the Gallium(Ga) , Arsenide(As), Prosphorus(P) and Alu-minium(Al) [15]. The materials offer light amplification and detection, in addition to passive light manipulation as filtering, splitting or interfering [21].
There is a variety of PIC in the market. It is an industry that has had the tendency to increase, given the rise of photonics in the current days. Photonics devices range from small-scale chips with laser-modulator and tunnable lasers to large-scale chips with new mod-ulation formats Tx/Rx, multi-channel Tx/Rx, or even complete sub-systems [15]. The first commercial PIC integrated in optical communications had two functions on a single chip: a DFB laser and DML. By 1996, these chips had been integrated in long distance terrestrial networks at bit-rate of 2.5Gbps and at 10Gbps by 1998 [22].
Figure 2.4: Data capacity per chip trend in commercial optical networks [22]
As observed in Figure 2.4, the trend for higher bitrates over the years had been kept. These characteristics are favourable for TDWM systems and favour the development of next generation optical network communications systems such as the NG-PON2 mention in Section 2.1.1.
2.3
Optical Components
2.3.1 Lasers
The Light Amplification by Stimulated Emission of Radiation, also known as Laser, is a device whose function is to create an optical or light signal. Prior to the laser invention light sources were mainly created from thermal processes like the tungsten filament lamp, or spontaneous emission from atoms and molecules, as in a gas discharge. This processes would always be related with temperature of the emitter and limited by that same parameter.
The investigation of the laser field that first came up with a successful laser was led by Theodore Maiman, in 1960, at the Hughes Research Laboratories. For over half century long, lasers have been target of various developments and nowadays they have applications on the areas of scientific research, consumer products, telecommunications, engineering, medicine, materials working and several others [23]. They can be found in every day’s life, from reading barcodes to playing CD recordings, CD ROM, gyroscopes, surgery, printers among others [24,
When put into comparison with other optical sources, lasers have higher bandwidth and higher spectral purity, this is, they function as bright coherent sources.These aspects of lasers allow the emission of light to be tightly focused, with minimum divergence [25]. As mentioned before, bandwidth is a very important detail, specially in optical communication systems. The standart laser outputs light at one specific wavelength. This can be accomplished by varying the thickness of the layers of the substrate. For example, a GaAs laser with a grating spacing of 120nm will grant a wavelength of about 850nm [27]. On the other hand, there are also lasers on the market that can vary wavelength and are dominated as tunnable lasers. Tunnable lasers vary the wavelength of the output signal according to current applied to the heater, that is usually placed near the laser body(substrate). This heater is no more that a resistor, that when applied current to, heats and therefore changes the refraction index of the material. Light will then travel throught the laser cavity at a different angle according to that same refraction index.
There are a wide variety of lasers: Gas laser, Ruby laser, Ion Lasers, quantum cascade laser, Distributed Feedback Laser, Distributed Bragg Reflector and others [27].
One of the laser types that the PIC can support is the DFB Laser.
The DFB Laser is the most common semiconductor laser found in PIC. By applying a electric signal it is possible to obtain a light signal. This phenomenon is illustrated in Figure 2.5.
Figure 2.5: Cross-sectional structure of a Fabry-Perot Laser - based on [28]
The DFB Laser operates with base on the Fabry-Perot principle, which lies on the usage of mirrored facets at the extremities of the laser cavity. This mirrored facets cause the photons to be reflected throughout the entire laser cavity, using a grating which consists of a periodic variation of the refractive index. This factor is decisive for the settling of the wavelength of the signal [29].
The temperature is an important factor when dealing with lasers. The wavelength shift of the laser is affected by the temperature at which the laser cavity is at. The increase in temperature, influences the refractive index of the cavity, causing the wavelength of the beam
to shift, as illustrated in the graph from Figure 2.6 [30].
Figure 2.6: Example of Wavelength variation vs laser temperature [30]
In addiction to the wavelength variation with the temperature, the optical power output of the laser decreases with the increment of temperature, as illustrated in the example from Figure 2.7. These two relations, turn temperature into a major factor for laser tunnability in photonics [30].
2.3.2 Photodetector
In chapter 2.3.1, it is shown how to create a light signal by applying a electric signal to accelerate the release of photons when holes and electrons come across each other on a InP medium. However in photonics, it is often necessary to work the other way around and obtain electric signal from light signals. Photodetectors are the elements responsible for the conversion of optical signals to electric signals. They operate based on the principle of light absorption , in which an incident photon creates a free pair, by removing an electron from a given atom [31]. The flux of electrons forms an electrical current.
Figure 2.8: Light Absortion Illustration [32]
When in the presence of an electric field caused by a voltage that is flowing throught a semiconductor, the holes and electrons are swept across that medium, which ultimately ends up in an electric current, that is proportional to the incident power [31].
Ip = R × P in (2.1)
Where R is the responsivity and can be expressed in terms of the quantum efficiency, η
The quantum efficiency is defined as the fraction of incident photons which are absorbed by the photodetector and generate electrons and is given by [33]:
η = h · v
q · R (2.2)
where h is the Planck constant and q is the electron’s electric charge. The responsivity is a characteristic of the photodiodes that dictates the relation between the amount of input optical power and output current. This relation depends on several factor such as wavelength of the incident light, the applied bias voltage to the photodetector and temperature [34].
Figure 2.9: Variation of responsivity by wavelength and material [33]
There is a wide variety of photodetectors that can be used for different purposes. In fiber optics, one of the most relevant type of photodetector is the PIN diode [34].
2.3.3 MMI
As mentioned in chapter 2.1.1, WDM based networks have been erupting in popularity in the past years. The urge to support these mechanisms has increased the interest in developing MMI(Multimode Interference) devices [35]. MMI is one of the results of the development in the area of optical waveguides and optical interconnection devices such as splitters, cross couplers, splitter-combiner, wavelength multiplexers and demultiplexers [36]. It works with base on the principle of self-imaging which is stated as: ”Self-imaging is a property of multimode waveguides by which an input field profile is reproduced in single or multiple images at periodic intervals along the propagation direction of the guide” [35]. By other words, this is a property of multi-mode waveguide, in which an input field profile is reproduced at regular intervals along the propagation direction. These reproductions can also be named guided modes [37]. Face to the prior statement, MMI devices are commonly denominated as NxM MMI, where N represents the number of input waveguides and the M represents the output number of waveguides.
Figure 2.11: Multimode Interferometer Structure [38]
According to Figure 2.11 the access waveguides are responsible for the input and output signal flow and the central section waveguide is where the wave propagates the signal coming from the previous section into several modes [38].
At the output of a MMI the exiting wave presents an Insertion Loss, caused by accumulated small deviations from phases at the imaging distances and tend to blur the reconstructed image field [35].
2.3.4 SOA
When travelling through the fiber, optical signals are subject to losses due to several factors. For this reason, it is necessary to compensate these losses in order to guarantee that the signal can reach the maximum distance possible and deliver a strong signal in terms of optical power. In dense wavelength division multiplexed(DWDM) optical networks, there are many frequency channels in a single optical fiber. Optical amplifiers are capable of amplifying these signal’s optical power without interfering with the signal in terms of modulation. The popular answer for the matter of fiber attenuation has become the optical amplifier due to the capability of allowing to keep the the power of the signal at a high value and as a consequence of that keep the SNR(signal-to-noise) degradation down.
There are different types of optical amplifiers such as Raman amplifiers, EDFA, SOA, among others. EDFA amplifiers are bulky, power hungry and more expensive devices when compared with SOA. All these factors added to the large bandwith of the SOA and it’s potential to be integrated electronic and optical devices make it the favorable choice to achieve gain in integrated photonics [39, 40]. SOA amplifiers operate on the bandwidth region of 1300 to 1600nm. The SOA amplifier working principle is similar to the Fabry-Perot Laser. However, the side mirrors have reduced reflectivity. The current injection serves to increase carrier density in the active region. When the current flows from the p-cladding to the n-cladding through the active region (Figure 2.12) , a carrier from the conduction band will combine with a hole from the valence band, creating a photon(as illustrated in Figure 2.8). If the current injected is enough, the density of carriers near the conduction band will be bigger and as a result, gain is obtained. However, one undesirable phenomenon might happen, which is given the name of spontaneous emission. In this process, a carrier and a hole will combine, resulting in a photon with different frequency and phase from the original one. This event is unwanted as it manifests as noise [41].
as the output signal hits a threshold(2.13b)).
Figure 2.13: a) Gain vs Current in SOA b) Gain vs Input Power in SOA [43]
Figure 2.14 shows the saturation of the gain versus the output power. The highest satura-tion power is obtained when a higher injected current is used, which has to do with a bigger carrier density in the active region. An higher injected current also causes a higher gain with a higher saturation power [44].
Gain is a characteristic that is influenced by the wavelength of the signal, therefore the SOA works better in the region of 1300 to 1600nm.
From Figure 2.15a) it can be gathered that as the wavelength increases, the gain decreases. For smaller input powers, the gain is higher, once the amplifier is capable of providing a big enough carrier density face to the incoming flow of photons into the active region. On the other hand, as the input power increases, won’t be dense enough in carriers, which causes the gain to decrease. At this point the output power is saturated (Figure 2.15) [44]
Figure 2.15: a) Gain vs Wavelength for different input powers b) Output power vs Wavelength for different input powers [44]
Chapter 3
Experimental Procedures and Tests
This chapter is divided in 2 parts. Firstly, the setup of the test bench will be explained. It figures aspects from the physical positioning of the equipment to the security measures applied in order to guarantee the safety of the same ones. By this statement it is meant to prevent the test bench from being susceptible to oscillations, static discharges and other factors that can disrupt the conduct of the tests.
3.1
Equipment and Chip Preparation
3.1.1 Fiber cleaving
For the optical tests it will necessary to prepare the fiber so that it can be used in the I/O optical ports of the chip. The fiber will allow the OSA(Optical Spectrum Analyzer) to recover the spectral image of the optical signal that will be gathered from the chip. For this process, it will be needed the material from Figure 3.1, which is also listed on Table 3.1. These are the fiber cleaver, alchool, Kimtech tissues, optical fiber, optical fiber splitters and pliers.
Figure 3.1: Fiber Cleaving Equipment Item Category 1 Fiber Splicer 2 Alchool 3 Kimtech Tissues 4 Optical Fiber 5 Fiber Stripper 6 Fiber Stripper (2)
Table 3.1: Equipment used for Cleaving of the Optical Fiber
• Still with the item Number 5 but using the smallest cutting width ring, remove the internal cladding of the fiber. This will expose the fiber. When executing this step, it is required awareness not to press or bend the fiber because it will be necessary some strength when pulling the internal cladding out.
• After pouring some alchool(Number 2) in a Kimtech tissue(Number 3), involve the fiber in the tissue and without bending the fiber, remove the remaining traces of the yellow internal cladding.
• As a final step in this process of cleaving fiber, use item Number 1 to cut the fiber. The cut has to be made in a 90◦ degree with the fiber or, in other words, completely transversely to the fiber.
After these steps, the optical fiber is ready for fiber alignment which will be better ex-plained in Section 3.1.3 and Figure 3.3.
3.1.2 Testing precautions
Optical components and equipment can be very delicate objects. As components can be of just a few microns in size, any oscillation or electrical discharge can cause damage to the structure of it and disrupt behaviours, causing anomalies and unexpected results during testing. Before the testing, the test operator must verify if all equipment is properly connected, before turning it on. It is also necessary to use the anti-static bracelet and stay at a safe distance from the bench. After the testing the PIC and PCB must be covered by a box to avoid exposure to dust and light.
3.1.3 Fiber Alignment
Single Mode Optical Fiber (SMF) is a type of fiber usually used for longer distances in optical communication networks. They have a core diameter of [5-10]1.55µm and 1251.55 µm of cladding which makes it very easy to bend. Multi Mode Fiber(MMF) have a much larger core diameter with [50-62.5]1.55µm. These are used for shorted broadcast for distances of [200-500]meters [45]. As a solution for the fiber fragility issue, it is going to be used a 3axis Thorlabs positioner shown in Figure 3.2. The Thorlabs 3axis positioner - MBT616D - allows micrometer movement in 3 different dimensions which is optimal to delicately maneuver the fiber into the SSC(Spot Size Converter) of the I/O ports of the chip.
Figure 3.2: ThorLabs 3axis positioner MBT616D at PICAdvanced’s Lab [46]
The fiber alignment is imperative to perform the optical tests. It allows the connection of the waveguides of the PIC with the optical fiber. The optical fiber is connected to an OSA or powermeter and this way it is possible to gather optical spectra and OP. In the fiber alignment observed in Figure 3.3, the optical fiber(Number 3 in Figure 3.3) is laid over the V-groove(Number 4 in Figure 3.3), to facilitate the sliding of the fiber into the SSC(Number 2 in Figure 3.3). Number 1 in Figure 3.3 is the PIC. The fiber must slide all the way down the SSC until it barely touches the PIC. During this process the fiber is connected to a powermeter in order to find the position with the most optimal OP.
3.1.4 TEC - Temperature Controller
As referred in the Section 2.3.1, one of the characteristics of light waves is that they vary their wavelength according to the temperature at which the laser operates. This is because the temperature influences the refractive index of the medium material causing the light to change angle when travelling through the waveguide, fiber, or photonic component.
To vary the temperature of the PIC a thermistor will be used, along with a TEC Controller to manipulate the temperature.
The TED200C TEC Controller by Thorlabs can provide a current up to 2A to the thermis-tor. However the thermistor available at the PICAdvanced’s lab can support a maximum cur-rent of 0.7A, and for that reason the TEC curcur-rent was set to 0.7A. The TED200C TEC Con-troller has a PID Temperature Control Loop to provide feedback and ease the settling of the temperature.Temperature controllers are used to control the response of thermo-electrically heated/cooled components in experimental setups, independant of external influences. To adapt a controller to different loads and to optimize the controller’s response characteris-tics, the controlling parameters of the system’s feedback loop must be optimized [47]. These parameters are the following:
• The P share (proportional, gain) can be adjusted with potentiometer ”P”;
• The I share (integral, offset control) can be adjusted with potentiometer ”I”;
• The D share (derivative, rate control) can be adjusted with potentiometer ”D”;
The PID parameters can be ajdusted just as shown in the interface of the TEC Controller TED200C from Figure 3.4 along with other setup functions. These functions are listed in Table 3.2
Number Function
1 Set the current limit of the thermistor
2 Choosing the thermistor value to adjust temperature 3 Display temperature
4 Display current that the TEC is providing to the thermistor 5 ON-OFF Switch
6 Choose the thermistor
7 Set the PID Controller parameters
Table 3.2: Functions of the User Interface of TED200C TEC Controller
3.1.5 LDC - Laser Diode Controller
The Thorlabs LDC210C Series Laser Diode Controller is a high accuracy precise injection current controllers for laser diodes and LEDs [48]. In our testbench, it will take the role of current supplier, so that the DFB and other components from our PIC can operate. The interface for the LDC210C is shown in Figure 3.5, along with its setup functions in Table 3.3.
Figure 3.5: User Interface of LDC200C TEC Laser Diode Controller [48]
Number Function
1 Select constant current/power mode 2 Select laser polarity
Figure 3.6: Pin port configuration of LDC
Figure 3.7: LDC configuration
3.1.6 PIC testing procedure
• Visual Inspection - As a first step in a PIC testing plan, the visual inspection to the chip must take place the in order to evaluate if there are any major evident problems visible on the surface. To accomplish this step a high resolution microscope has to be used. In this situation it was used a LEICA microscope from the Institute of Telecom-munication lab. This step can also allow some rough measurements on the components dimensions to anticipate possible fabrication deviations.
• Bonding Inspection - The bonding inspection is also a visual inspection but its intent is not to guarantee the state of the chip surface, but to guarantee that the metal connections from PIC to holder and holder to PCB remain intact and that they are made from the correct pad of the chip to the respective pad of the holder, and the same applies from the holder to the PCB.
• Electrical Verification - Has the point to verify all the expected voltage values from components. As an example, if the component under test is a PIN, the diode voltage should be evaluated. The typical value is around [0.7 - 0.9] volts. If the measured value is out of this range, the PIN is most likely not working properly. The same test should be performed on the DFBs and SOAs. If the component in discussion is a Polarization Splitter or a DFB heater the resistance must be measured.
• Architecture - This last step includes the actual tests that will be performed to each architecture, with all the components being powered and working actively. From these tests will be recovered data that will allow the test team to gather assumptions and conclusions of whether the architecture is behaving as expected or not, and if not, what is causing that to happen and also formulate solutions for such.
3.1.7 Rigol Automatization
PIC testing can be a intensive workflow that englobes work from plan testing, maintenance of the devices and the testing itself. Test benches can be complex platforms, with a lot of equipment and many times demand the test operator to stand up to be able to reach certain equipment that might not be in range of his sit. As a solution for delayed measurements or large sweeps of tests, which evolved around alternating between instruments such as the oscilloscope for set up and the computer for registering the collected data. This app was developed with the tool GUIDE, available in the MATLAB software. It has as objective to allow the test operator to set up the configurations into the oscilloscope and saving the data from the tests without leaving the computer.
Figure 3.8: Rigol Matlab Application - User Interface
The communication between the app and the Rigol is made via VISA protocol which allows the assignment of an object variable in the app to a electronic device. This way, it is possible to write and read commands to and from the device, respectively. These list of commands was developed Rigol and constitutes the firmware responsible for the SCPI communication
3.2
Experimental Tests
3.2.1 Electrical Procedure
This chapter englobes a set of electrical tests, this is, all the tests that are going to be performed to the board will be measured by gathering electrical values such as voltage. The PINs are going to allow the indirect measurement of optical power emitted by the DFB.
To allow this measurement, the PCB contains a current mirror illustrated in Figure 3.9. The name of the component is a DS3920 Fast Current Mirror.
Figure 3.9: Integrated Fast Current Mirror - DS3920
The current that goes through the PIN is the current that travels through diode D1 on the pin 4 of the IC, DS3920. The voltage on pin 4 is of 3.3V and the voltage on pin 3 can go up to 3.3V. Recurring to the resistor R1, it is possible to achieve the current value in R1 and D1, by using the Ohm Law. It was used the value of 2k2Ω for R1.
I = V
R (3.1)
Then, it is possible to obtain the Optical Power in the linear scale, using the following relation: P (W ) = I
0.8, (3.2)
where 0.8 is the value of the responsivity of the PIN.
The value of the Optical Power in the logarithmic scale is given by:
P (dBm) = 10 × log10(1000 × P (W )), (3.3) To measure the voltage, two instruments were used along the tests in the several architectures: The oscilloscope Rigol DS1104 (Number 3 in 3.10) or alternatively the Thorlabs multimeter (Number 4 in 3.10). The equipment shown in Figure 3.10 is also enumerated in Table 3.4.
Design 1 - Architecture 1
The first test that it is going to take place is in the electrical domain. For that, the PIC is assembled in the holder and the holder is assembled on a PCB. The PIC in study contains multiple architectures and the main components in which the study evolves around are DFB lasers and PIN photodetectors.
The architecture 1 is composed by 2 DFB lasers and 2 PIN photodetectors. The compo-nents are distributed according to Figure 3.11. There is a block composed by DFB1 followed by an PIN1, which is then followed by a identical block which contain DFB2 and PIN2. Given the fact that DFB emits light both sides, this test consists in verifying the following events:
• The optical power observed in PIN1 when only DFB1 is ON, plus the optical power in PIN1 when only DFB2 is ON, equals the optical power in PIN1 when both DFB1 and DFB2 are simultaneously ON.
• When DFB2 is ON, the optical power measured in PIN1 and PIN2 are near the same value of each other.
Figure 3.11: Block diagram of architecture 1 - Design 1
The PIC-holder-PCB set was mounted on a platform which could be moved in different axes with the use of a Thorlabs 3axis positioner (Number 5 - left on Figure 3.10).
In a initial part of the test, the lasers will be supplied by the PCB shown in Number 5 -left on Figure 3.10, which connected to a computer app. Later in the test the input of the lasers will be connected to a LDC - Laser Diode Controller(Number 1 in Figure 3.10) that is also going to perform as a current source. These lasers can be fed up to 150mA at the max, but as a precaution measure for not deteriorating the laser, the laser are going to perform at the most of 120mA.
Number 2 in Figure 3.10 represents, the TED200C which is the TEC - Temperature Controller used to adjust the temperature of the PIC to the desired value. The first step in the experiment is to power only DFB1 and collect OP data on PIN1. The experiment was repeated for 3 distinct temperatures [15,20,25]◦C .
Figure 3.12: Block diagram of architecture 1b - Design 1
Figure 3.13: DFB1 OP vs DFB1 Current
As seen in Figure 3.13 the OP on PIN1 varies as function of the DFB1 current. It shows a similar behaviour for all 3 temperatures. From the 30mA of current upwards, the OP increases consistently indicating that this is the the active region of the laser. The lower the temperature is, the earlier this active region will end, with it being 75mA for 25◦C, 90mA for 20◦C and 100mA for 15◦C. Past the referred points the laser starts to saturate until the end of the tests range. The saturation points are shown in Table 3.5. According to it, the higher the temperature, the sooner the laser saturates.
causes them to emit light to both sides, so it is expect that the amount of light exiting each side to be equal.
Figure 3.14: Block diagram of architecture 1c - Design 1
Figure 3.15: DFB2 OP vs DFB2 Current
PIN1 data is represented as a uniform line in Figure 3.15 and PIN2 data is represented as the dot line. As in the previous step of the test, the active region starts in the [20-30]mA region, with the lower temperatures starting earlier and the higher ones, later. At the saturation point for each DFB, the mean optical power for each PIN is shown in table 3.6. It matches the same behaviour from Table 3.5, at which the saturation point happens sooner for higher temperatures. It is also to note that DFB2 is emitting more light to the PIN1 than for the PIN2; 3.4dB at 15◦C, 2.1dB at 20◦C and 2.5dB at 25◦C.
TC MOP (dBm) DFB2 Current (mA) PIN1 15 7.0 115 PIN2 3.6 115 PIN1 20 6.3 100 PIN2 4.2 110 PIN1 25 5.3 80 PIN2 2.8 90
Table 3.6: DFB2 MOP at saturation points
Figure 3.16 shows the measured optical power value on PIN1, when DFB1 and DFB2 are simultaneously ON, in contrast with the expected value obtain from the calculation of the Equation 3.4. The Expected OP consists of the sum of the PIN1 voltage obtained in 3.13 with the PIN1 voltage obtained in 3.15. At the exception of PIN1 values for a temperature 25◦C, the expected PIN1 values match each other.
Expected OP = 10×log10(1000×( P IN 1 OP (DF B1ON )+ P IN 1 OP (DF B2ON ))) (3.4)
To close the tests on this architecture and provide some more information on the matter an external current source was used to feed the lasers. The advantage of this external current source is that it allowed a bigger current excursion, it was more precise and easier to handle in terms of setting values of current. Figure 3.17 and 3.19 shows several current sweeps for different temperatures. Table 3.8 and 3.9 correspond to the respective saturation points.
Figure 3.17: DFB1 OP vs DFB1 Current for several Temperatures
T◦C MOP (dBm) DFB1-2 Current (mA)
PIN1 15 3.7 85 20 2.9 75 25 1.8 65 35 0.2 100 50 -5.0 75
Table 3.8: DFB1 MOP at saturation points
With base on Figure 3.17 it was possible to retrieve the maximums of optical power before saturation of the DFB1. This way it’s possible to trace a slope drop of power with the increase of temperature, just as in Figure 2.7. The slope drop obtained from the pratical results in shown on Figure 3.18.
Figure 3.18: Slope drop of Optical Power with Temperature
Figure 3.19: DFB2 OP vs DFB1/2 Current for several Temperatures
T◦C MOP (dBm) DFB1-2 Current (mA) PIN1 15 7.1 100 PIN2 3.5 100 PIN1 20 6.4 90 PIN2 3.7 95 PIN1 25 5.4 75 PIN2 3.1 115 PIN1 35 1.0 95
when only DFB1 is ON, plus the optical power received in PIN1 when only DFB2 is ON, equals the optical power obtained in PIN1 when both DFBs are ON simultaneously, until it saturates
With base on Figures 3.13 to 3.19, the curves representing the cases at lower temperatures, show higher optical power, which agrees with the statement from Chapter 2.3.1 and Figure 2.7, in which the optical power is higher for lower temperatures and drops as the temperature increases.
Design 1 - Architecture 2
In the following architecture of the same chip - Architecture 2 - there are 3 main com-ponents in cause: DFB lasers, PIN photodetectors and SOA amplifiers. In the architecture there is a DFB laser with one SOA on each side output. Both SOA’s output are connected to two independent Power Splitters 1x3. Each one of the three outputs are connected to one PIN. These are PIN 3, 4 and 5. In a optical communication system, this component would work as a local oscillator for a coherent receiver. The illustration of the architecture can be better interpreted in Figure 3.20. It is to note that the PIN5 diode voltage wasn’t within the expected range from the Electrical Verification from Section 3.1.6, which indicated the photodetector was not working properly or was completely damaged. For that regard, all the PIN data collected will refer only to PIN3 and PIN4.
Figure 3.20: Block diagram of architecture 2a - Design 1
In the first place, we want to verify if with the SOAs OFF, the optical power coming out of the DFB3 gets to the PINs or if the optical power is blocked by the SOAs. From Figure 3.21 it is possible to verify that the PINs still receive optical power, with the average value of -16.7dBm for PIN3 and -15.7 for PIN4. The temperature was set to 25◦C.
Figure 3.21: PIN3/4 OP vs DFB3 current - SOAs OFF
The next step is to verify the behaviour curve of the SOA. For that, a sweep in current was performed to both SOA1 and SOA2. The results are shown in Figure 3.23 and 3.25. These results match the set up illustrated in Figure 3.22 and 3.24, respectvely. The SOA have the role to amplify the OP of the signal exiting the DFB3. The feed to the DFB3 is fixed at 75mA, with SOA1 ON and SOA2 OFF as it is illustrated in Figure 3.22 and 3.24. The reason why the DFB3 was fixed at 75mA was to guarantee that it is on the active region. The test was performed at a temperature of 50◦C, with the temperature being imposed by the TEC Controller TED210C.
Figure 3.23: PIN4 OP vs SOA1 Current at 50◦C, DFB3=75mA
Following the same line of thought from the previous step, the SOA2 is now ON, and SOA1 is OFF. All the other parameters maintain the value from the previous measurement. The DFB3 current was fixed at 75mA and the temperature of the TEC at 50◦C. As shown above both SOA provide a similar curve of optical power on PIN4 as the current provided is increased.
Figure 3.24: Schematic of architecture 2 - Design 1
By overlapping the results from Figure 3.23 and 3.25 as well as assuming both power splitters divide the OP in two perfect halves, it is possible to get to the conclusion that both SOA have a silimar behaviour(Figure 3.26). On the SOA2 sweep, PIN4 shows a ∆OP of 0.5dB in comparison to the SOA1 sweep, from the 40mA onwards.
Figure 3.26: PIN4 OP vs SOA1/2 Current at 50◦C, DFB3=75mA
In the next part, the TEC temperature was changed to 25◦C, and both PIN3 and PIN4 OPs were compared. The objective of this test is to verify if both PIN receive equal OP from the Power Splitter.
SOA1 and 2.0dB in the SOA2 sweep. The first value is negligible, but in the second there is some discrepancy between the PIN3 and PIN4.
By maintaining the TEC temperature at 25◦C, several steps on current were applied to the DFB3 ([25,50,75,95]mA). For each of these steps a SOA1 and SOA2 sweep was performed and the optical power results were registered and exhibited in the graph from Figure 3.28.
Figure 3.28: PIN3/4 OP vs SOA1 Current for several DFB3 currents at 25◦C
MOP PIN3 (dBm) MOP PIN4 (dBm) ∆OP(dB) DFB3 Current (mA)
-24.9 -25.6 0.7 25
-15.1 -15.7 0.6 50
-12.4 -13.0 0.6 75
-12.9 -13.5 0.6 95
Table 3.11: MOP PIN3/4 vs SOA1 Current for several DFB3 currents at 25◦C
For the case at which the DFB3 is at 25mA, the OP on PIN3 and PIN4 considerably lower than on the other cases, staying on the -24.8 and -25.6dBm mark. This is sign that the DFB5 is still not actively emitting photons, therefore the amplified signal barely increases with the SOA1 current sweep. However, for the steps of [50,75,95]mA on the DFB3, the PIN1 OP increases constantly as the SOA1 current increases until it saturates. After reaching its peak of OP, the curve then drops. This might be due to thermal crosstalk. Thermal crosstalk happens when a component’s temperature is influenced by a changing power dissipation profile on a nearby neighbour [49].
Face to the unexpected result from the previous test, a different parameter was changed in order to gather some more conclusions about that same unexpected event. For that so, with the DFB3 current at 95mA, a current sweep was performed on the SOA1. The only variable in this case was the temperature, which was set for 20◦C and 25◦C.
Figure 3.29: PIN3/4 OP vs SOA1 Current (65-95)mA at 20◦C and 25◦C, DFB3=95mA
TC MOP PIN3 (dBm) MOP PIN4 (dBm) ∆OP(dB) DFB3 Current (mA)
25 -12.9 -13.5 0.6 95
20 -11.2 -11.7 0.5 95
Table 3.12: MOP PIN3/4 vs SOA1 Current (65-95)mA, DFB3=95mA, at 20◦C and 25◦C
Figure 3.29, shows that the temperature has a strong role in this matter, once at 20◦C the OP doesn’t suffer such a fall as had happen for the case at which the temperature was set at 25◦C.
For the last part of this architecture’s tests, instead of performing SOA current sweep for different steps of DFB3 current. it was performed a DFB3 current sweep for different steps of SOA1/2 current([17,30,50,65,90]mA). The results are shown in Figure 3.30.
MOP PIN3 (dBm) MOP PIN4 (dBm) ∆OP (dB) SOA1 Current (mA) -16.6 -17.3 0.7 17 -13.5 -14.1 0.6 30 -12.4 -13.0 0.6 50 -12.3 -12.8 0.5 65 -13.9 -14.4 0.5 90
Table 3.13: PIN3/4 MOP for several SOA1 Currents at 25◦C
After concluding the tests on this architecture, some observations can be made:
• With only the DFB3 ON and both SOA OFF, the PINs still receive optical power from the DFB3.
• Better OP results at T=25◦C than 50◦C. The building blocks are optimized for 25◦C. When the temperature is inscreased, the DFB wavelenght can shift which cause the decrease on the OP results seen in Figure 3.28 and 3.30.
• The decreasing of the OP at the PIN after the SOA saturation can be explained by the thermal crosstalks imposed by the SOAs on the DFB.
• By decreasing the TEC temperature for 20◦C in Figure 3.29, the OP is increased after
the SOA’s saturation region. By varying the DFB3 current with the SOA current fixed, the same behaviour is observed, the OP decrease for DFB3 current values above 100mA.
It is possible to assert that the DFB3 signal obtained in Figure 3.21 with both SOAs OFF, can be amplified by providing a current to the SOA(s). That current provided to the SOA1 is shown in Figure 3.30 and the optical power meets his most optimal value for a SOA1 current of 65mA.These results help to consolidate the statement expressed by Figure 2.13 as for higher SOA1 currents, the output optical power is higher.
Design 1 - Architecture 5
Architecture 5 also represents a local oscillator which is very similar to the Architecture 2 from this same chip. It is composed by a DFB with one SOA on each output. These SOA’s outputs both go into two distinct 1x4 Power Splitters whose exits lead to the four PIN - PIN8, 9, 10 and 11. PIN9 had an invalid diode voltage according to the Electric Verification from Section 3.1.6 and it wasn’t possible to read any valid voltage on this PIN.
Figure 3.31: Block diagram of architecture 5 - Design 1a
The tests on this architecture will be based of DFB5 current sweeps. The objective is to observe the behaviour of the optical power received at the PINs as the SOAs amplify the light signal emitted by DFB5. The SOA current steps are of [20,50,80]mA. Another objective is to conclude about the optical power distribution over the PINs. For a reason of keeping this section organized and simple, the results presented in this architecture will be regarding the case at which the test was performed at a temperature of 15◦C, because at this temperature, the test was able to obtain higher OP in the results. The results regarding T=25◦C and T=35◦C can be found in the Appendix.
Figure 3.33: PIN8/10/11 OP vs DFB5 Current for several SOA4 Currents at T=15◦C
This tests shows a group of curves similar to the previous one on Figure 3.32. However the optical power starts to increase later in the DFB5 current sweep. The maximum optical power is also reached earlier in the sweep, at the mark of 70 and 80mA.
On the last set of measurements for this architecture at the temperature of 15◦C, both SOAs are turn ON, still on the steps of [20,50,80]mA.
PIN SOA(mA)
SOA3 SOA4 SOA3+4
MOP DFB5 MOP DFB5 MOP DFB5
(dBm) (mA) (dBm) (mA) (dBm) (mA)
8 20 -12.4 100 -11.6 70 -12.4 90 10 -10.8 90 -10.3 70 -12.4 90 11 -9.4 100 -8.3 70 -9.6 100 8 50 -8.2 100 -11.7 70 -8.7 90 10 -6.7 100 -10.5 70 -7.4 100 11 -4.8 100 -8.3 80 -5.4 100 8 80 -7.5 100 -12.0 80 -8.8 80 10 -6.1 100 -10.6 80 -7.3 80 11 -4.0 100 -8.7 80 -5.4 80
Table 3.14: PIN8/10/11 MOP at saturation points on Figure 3.32, 3.33 and 3.34 Table 4.2 shows the maximum optical powers reached before saturation of the SOA(s). The highest OP values reached happen for the case at which SOA3 in ON. Even when both SOA are ON, the OP isn’t as high as when the SOA3 is ON. When SOA4 is ON, the OP displayed not only is lower than when SOA3 is ON, but it also saturates earlier in the current sweep from DFB5(at the 70-80mA mark). From observing the equivalent Figure for temperatures of 25◦C and 35◦C located at the Appendix, it is possible to conclude that lower temperature provide higher OP.
PIN SOA(mA) SOA3 SOA4 SOA3+4
∆OP (dB) 8-10 20 1.6 1.3 0 8-11 3 3.3 2.8 10-11 1.4 2 2.8 8-10 50 1.5 1.2 1.3 8-11 3.4 3.4 3.3 10-11 2.9 2.2 2 8-10 80 1.4 1.4 1.5 8-11 3.5 3.3 3.4 10-11 2.1 1.9 1.9
Table 3.15: ∆OP between PIN8,10,11
3.2.2 Optical Procedure
This chapter regards to the setup and execution of optical tests. The fact of the chips having I/O optical ports increases the potential of chip testing at our lab.
Figure 3.35: Setup of the optical tests
In the lab, there is available the following equipment, as listed in table 3.16:
Number Category Model Brand
1 Laser Diode Controller LDC210C Thorlabs 2 Temperature Controller TED200C Thorlabs 3 Optical Spectrum Analyzer FTB-400 EXFO
4 Powermeter Thorlabs
5 PCB Platform on 3axis Positioner Thorlabs Table 3.16: Equipment used for the Optical Procedure Tests
In figure 3.35 it is presented the setup used for the optical tests. Number 1 and 2 represent the equipment responsible for the variation of the test parameters, namely the current and temperature. These equipments are the current laser diode, Thorlabs LDC210C and the temperature controller, TED200C. The setup and handling of such referred equipment was already mentioned on chapter 3.1.4 and 3.1.5. In the number 3 and 4, it is the equipment used for data recover: OSA and powermeter, respectively. The OSA can exhibit the optical spectrum of the optical output of the chip and the powermeter can show the the optical power of the output signal. As last, number 5 shows the platform that holds the chip and holder in position. This platform is mounted on a Thorlabs 3axis positioner to allow micrometer positioning adjustment for fiber alignment.
Design 1 - Architecture 4
In this section, it is presented a study on the architecture 4 of the chip. This architecture is different from the architectures previously studied, on the aspect that it has I/O optical ports, something that the previous ones didn’t have. The objective of this experience is to characterize this laser taking into account a small set of parameters. These parameters are the current provided to the laser and the temperature of the environment. The EAM modulator will remain off during the experiment.
Figure 3.36: Block diagram of architecture 4 - Design 1
After aligning the fiber in the respective optical I/O port of the chip, the tests can be begin, starting with a current sweep on DFB4 laser. The fiber alignment was conducted according to the procedure referred in section 3.1.3. The current supply was applied in steps of 10mA to guarantee an homogeneous sample range.
