Design and Performance Analysis of FFT in OFDM applications using VHDL

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Design and Performance Analysis of FFT in

OFDM applications using VHDL

1

Renu yadav

M.Tech Scholar

Dehradun Institute of Technology, Uttrakhand Technical University, Dehradun India E-mail: renuyadavdbit@yahoo.com

2_{Mukesh Pathela} Head of department,

Department of Electronics & Communication Engineering, Shivalik College of Engineering, Dehradun India E-mail: mukeshpathela@gmail.com

Abstract

For Orthogonal Frequency Division Multiple Access (OFDMA) system module, there is a need for an efficient alterable point FFT block. The research work focuses the design and synthesis of FFT module which is designed to meet the requirements of OFDM & OFDMA system. In the widely used OFDMA systems, the FFT and IFFT pairs are used to modulate and demodulate the data constellation on the subcarriers. The research paper presents a high level implementation of a high performance FFT for OFDM Modulator and Demodulator. Field programmable gate arrays (FPGAs) are extensively used in rapid prototyping and verification of a conceptual design and also used in electronic systems when the mask-production of a custom IC becomes prohibitively expensive due to the small quantity. HDL based VLSI design requires a careful forethought about the entire design process with special attention to transistor sizing, floor planning, layout routing, clock and power distribution with timing analysis. VHDL language is used to present a detail design of FFT block using Xilinx 14.1 software, ModelSim (SE) 10.1b software for the simulation, and verify on the Spartan3E FPGA. Keywords

Fast Fourier Transform (FFT), Inverse Fast Fourier Transform (IFFT), Very Large Scale of Integration (VLSI) 1. Introduction

In modem communication systems Orthogonal Frequency Division Multiple (OFDM) [1] [2] plays an important part, and it will be replaced by Orthogonal Frequency Division Multiple Access (OFDMA) [5] [9] in the next generation wireless communication systems such as WiMAX [1] [2] and 3G-LTE standard. The OFDMA PR [5] is based on OFDMA modulation, which comprises of OFDM modulation as well as subcarrier allocation. Therefore, it is significant to focus more attention on wireless communication technology. IEEE Std 802.16 family [1] is a wireless metropolitan area network standard which is detailed in fixed service in 2004 edition and the 2005 edition for mobile access technology.

Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier transmission technique that divides the available spectrum into multiple carriers in which each one is being modulated by a low rate data stream. OFDM is similar to FDMA [10] in that the multiple user access is achieved by subdividing the available bandwidth into multiple channels band, which is then allocated to users. So, OFDM uses the spectrum much more efficiently by spacing the channels much closer together. It is possible by making all the carriers orthogonal to each another, preventing interference between the closely spaced carriers.

2. OFDM block diagram

The block diagram of OFDM is shown in figure 1.The symmetrical arrangement about the vertical axis is necessary for using the IFFT to manipulate input data. An inverse Fast Fourier transform (IFFT) converts the frequency domain data set into samples of the corresponding time domain representation of this data. Specifically, IFFT is very much useful for OFDM because it generates samples of a waveform with frequency components satisfying orthogonality conditions among its carriers. Then, there is the need of parallel to serial block that creates the OFDM signal by sequentially outputting the time domain samples.

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Figure 1 OFDM block diagram

The time domain samples are passed to the channel simulation allows examination of common wireless channel characteristics such as noise, multipath, and clipping. By adding random data to the transmitted signal, simple noise can be simulated for performance analysis. Multipath simulation involves adding attenuated and delayed copies of the transmitted signal to the original signal. This simulates the problem in wireless communication when the signal propagates on multiple paths. For an example, a receiver may observe a signal via a direct path as well as a path that bounces off a building or mountain. Finally, clipping action is taken to simulate the problem of amplifier saturation. This scheme addresses a practical implementation problem in OFDM where the peak to average power ratio is high. In demodulation section, the receiver performs the inverse of the transmitter. At channeling end first, the OFDM data are split from a serial stream into parallel sets. The Fast Fourier Transform (FFT) converts the time domain samples back into a frequency domain representation. The magnitudes of each frequency components are correspond to the original data. Finally, at receiving end, the parallel to serial block converts this parallel data into a serial stream to recover the original input data.

3. Fast Fourier Transform (FFT)

The fast Fourier Transform (FFT) is an algorithm that efficiently computes the discrete Fourier Transform (DFT). The DFT of sequence x(n) over length N is given by the relation which is a complex valued sequence X(k).

/ _,

The equation can be represented by the relation

/ _,

Here WN represents the complex valued phase factor, which is the Nth root of unity and expressed as

/

Similarly the equation of IDFT is given as

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Figure 2 Flow graph of DIT FFT (N=8) as butterfly structure [15] The value of weight coefficients are

cos sin .7 7 .7 7

cos sin

cos sin .7 7 .7 7

4. Modelsim and Xilinx outputs of 8-point FFT

The Modelsim output of 8 point FFT is shown in figure 3 and 4. In the diagrams X(0)…… X(7) presents the input to FFT module and Y(0)….Y(7) resents the output of FFT module. Similarly Figure 4 shows the discrete data transfer by FFT with complex numbers also. Y(0)……Y(7) presents the output of FFT and output of IFFT. Functional simulation on Modelsim depends on the following step inputs.

Step input1: Force the value of data_in and X(0) to X(7) and run

Step input 2: The output of FFT and input of FFT Y(0)…. Y(7) are in separated in real and imaginary parts because the output of FFT may be a complex number real_Y(0)….. real_Y(7) are the real parts and im_Y(0)…….im_Y(7) are imaginary parts of output.

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Figure 3 Modelsim output of 8-point FFT

Figure 4 Modelsim output of 8-point FFT with complex numbers 5. Device utilization and timing summary

Device utilization report is the report of used device hardware in the implementation of the chip and timing report is the minimum and maximum time to reach the output. Timing parameters are synchronized with the clock signal. Timing details provides the information of net delay, minimum period, minimum input arrival time before clock and maximum output required time after clock

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Optimization Goal : Speed

Optimization Effort : 1

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

DSP48 Utilization Ratio : 100

Slice Utilization Ratio Delta : 5

Macro Statistics # No of Multipliers : 12

33x33-bit multiplier : 12

# No of Adders/Subtractors : 25

No of 32-bit adder : 16

No of 32-bit subtractor : 9

Macro Statistics # Multipliers : 12

33x33-bit multiplier : 12

# Adders/Subtractors : 25

32-bit adder : 16

32-bit subtractor : 9

# GND : 1

# INV : 64

# LUT1 : 2

# LUT2 : 1802

# LUT3 : 58

# LUT5 : 1

# LUT6 : 59

# MUXCY : 1821

# VCC : 1

# XORCY : 1929

# IBUF : 256

# OBUF : 515

# DSPs : 18

# DSP48E : 18

Device utilization summary: Device EP2S90F1020I4 Slice Logic Utilization: Number of Slices : 1986 out of 72768 15%

Number used as Logic : 1986 out of 72768 15%

Slice Logic Distribution: Number of LUT Flip Flop pairs used : 1986

Number with an unused Flip Flop : 1986 out of 1986 100% Number with an unused LUT utilizatio : 0 out of 1986 0%

Number of LUT-FF pairs used : 0 out of 1986 0%

IO Utilization: Number of Ios : 71

Number of bonded IOBs sources : 71 out of 172 41% Specific Feature Utilization: Number of DSP48Es elements : 18 out of 24 75%

Speed Grade : 2

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Maximum combinational path delay : 17.988 ns Total memory usage is : 201920 kilobytes

A flow chart to compare the results in VHDL and MATLAB is shown in the figure 5. The results are corresponding to Minimum time, Maximum time and path delay values obtained from the synthesis summary of Xilinx software. In the MATLAB the delay estimations are in milliseconds and in VHDL nanoseconds. So, VHDL implementation can be a best solution in comparison to MATLAB.

Fig. 5 Comparison of delay (Minimum, Maximum and path delay) in VHDL and MATLAB 6. Conclusion and future work

The hardware chip design and synthesis done for FFT module in VHDL is done on Xilinx 14.2 software. The simulation results are tested on Modelsim 10.1 b student edition successfully. The FFT modules are tested for the different test cases. FFT is used in demodulation schemes and data transfer is checked out with FFT/IFFT transreceiver used in OFDM and ODDMA applications.

The existing work can be used for Wimax and wireless technology in which fast computations are required. FFT implementation can be a good solution for multiple input multiple output (MIMO) system. So, it is possible to implement for MIMO OFDM and MIMO OFDMA systems. The value of time delay is very less in nanoseconds in VHDL realization and in MATLAB it is in milliseconds. The design is applicable to develop ‘N’ point FFT. The feature of pipeline and parallel processing supports to execute the design upto ‘N’ points which are applicable to OFDMA applications.

REFERENCES

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Min Time Max Tme Path delay

VHDL result

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