Dependˆ
encias de Controle
1
or r4, r5, r6
2
sw r15, 0(r16)
3
sub r8, r9, r10
4
beq r1, r2, -4
5
add r12, r13, r13
6
and r14, r15, r16
Se (r1 = r2)
volta atr´as 4 instru¸c˜
oes (or)
sen˜ao
executa add na linha 5
s ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s sssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s
MD
MI
REG
REG
add r2
beq r1,r2
sub r8
sw r15
or r4
beq
s´
o escolhe novo PC no ciclo
DEC
!
O que acontece com a instru¸c˜ao em BUSCA?
Desvios e Saltos
desvios
beq r1,r2,desl
desl em 16 bits, compl-2
PC
←
( r1=r2 ? PC+4+(extSinal(desl)≪ 2) : PC+4 )
saltos
j ender
ender em 26 bits
PC
←
PC(31..28) & (ender≪ 2)
jal ender
ender em 26 bits
r31
←
PC+4 ; PC
←
PC(31..28) & (ender≪ 2)
jr r3
ender em 32 bits
PC
←
r3
UFPR BCC CI212 2016-2— previs˜ao de desvios 2
Revis˜
ao – dependˆ
encias de dados
•
Dependˆencias de dados resolvidas com adiantamento
(quase sempre)
•
Deve garantir que instru¸c˜
oes anteriores escrever˜ao resultado,
destino ´e mesmo que fonte,
e instru¸c˜ao anterior n˜ao tem prioridade
•
Acrescentar circuito de adiantamento onde pode-se adiantar
→
for¸ca bloqueio se precisa esperar por resultado
est´agio EXEC, MEM para store, DECOD para desvio
• loads necessitam parada porque sobrep˜
oem EXEC com MEM
desvios podem necessitar de parada tamb´em
Saltos causam uma bolha
Saltos s˜ao decodificados em DECOD → necessitam um ciclo de stall
felizmente, saltos s˜ao infreq¨
uentes: ≈ 2% nos programas SPECint
qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qq ... ... ... .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
MD
REG
REG
ciclo 2
ciclo 1
ciclo 3
ciclo 4
ciclo 5
ciclo 6
ciclo 7
ciclo 8
c 9
MI
MD
REG
MI
REG
MD
REG
MI
R
j 2000
stall
and r6,r7,r8
sub r4,r1,r5
Circuito com Desvios e Saltos
... .... ... .... . ... .... .... ... ... .... .... ... ... ... ... ... ... ... ... .... . ... .... .... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqq
aluB
regC
opULA
mRd
mWr
rDest
rWr
jump
prxPC
✈ ✈ ✈ ✈ ✈ qqqqqqq qqqqqqqqqqqqqqqqqqqqq ✈ ... . ... ... ... ... ... . ... ... ... ... ... . ... . ... ... ... .... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq q rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr ... . ... ... ... ... rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr ... .... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq q ... .. ... .. rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr r rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr ... .. ... ... ... ... ... . qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq .. ... ... ... ... ... .... ... ... ... ... .... ... .... .... ... ... qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq q qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq ... ...escDados
ULA regs extSinal 32 16 memDadosA
B
ender
leDados
4
endLer
P
C
memInstr 0 1 0 1 0 1instr
c
b
a
C
1 0 sll 2 igual [27-0] [31-28] sll 2 1 0UFPR BCC CI212 2016-2— previs˜ao de desvios 5
Riscos de Controle
•
Ocorrem quando seq¨
uˆencia de endere¸cos n˜ao ´e linear
→
‘linear’ ´e o ‘normal’ no processador segmentado
•
riscos causados por instru¸c˜
oes de controle de fluxo
desvios condicionais
beq, bne
saltos
j, jal, jr
•
Solu¸c˜
oes poss´ıveis:
(a) bloqueia (stall)
(b) mover decis˜ao para segmento pr´oximo de BUSCA
(c) atrasar a decis˜ao (necessita ajuda do compilador)
(d) prever a dire¸c˜ao do desvio
•
riscos de controle s˜ao menos freq¨
uentes que riscos de dados;
mas
n˜ao h´a nada t˜ao efetivo para riscos de controle quanto
adiantamento para riscos de dados
Quest˜
oes com adiantamento – desvios em DECOD
•
Adiantamento de operandos no registrador EM
adianta resultado da pen´
ultima instr para entradas do comparador
if ( Dcntrl.desvio
and ( EM.rd != 0 )
and ( EM.rd == BD.rs ) )
{ fwdC = 1 }
if ( Dcntrl.desvio
and ( EM.rd != 0 )
and ( EM.rd == BD.rt ) )
{ fwdD = 1 }
•
adiantamento de MR ocorre atrav´es do bloco de registradores
•
se instru¸c˜ao imediatamente anterior ao desvio produz um dos
operandos da compara¸c˜ao, ent˜ao um
bloqueio
´e necess´ario
porque opera¸c˜ao de ULA em EXEC ocorre ao mesmo tempo
em que a compara¸c˜ao em DECOD
Decis˜
ao de desvio tomada no 2
o
est´
agio
•
Adicionar circuito para computar endere¸co de destino e
circuito para avaliar condi¸c˜ao de desvio ao est´agio DECOD
⊲
n´
umero de bolhas ´e uma
(como nos saltos)
⊲
endere¸co de destino deve ser computado em paralelo com
acesso ao bloco de registradores
❀ s´
o usa endere¸co em desvios e saltos
⊲
a compara¸c˜ao s´
o pode ocorrer ap´os o acesso aos registradores
para ent˜ao alterar o PC –
piora temporiza¸c˜ao do est´agio
⊲
necessita
adiantamento para o est´agio DECOD
•
em pipelines longos, decis˜ao ´e mais tardia e causa mais bolhas
→
´e necess´ario algo melhor...
UFPR BCC CI212 2016-2— previs˜ao de desvios 8
Desvios causam uma bolha
qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq q ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qq ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... ... ... .... ... .... ... ... ... ... .. ... ... ... ... ... .... .... ... .... .... .... .... ... .... ... ... ... ... ... ... ... ... ... ... . ... ... ... . ... ... ... ... ... .... .... .... .... ... .... .... .... .... ... ... ... ... ... ... ... ... ... ... .. ... ... ... ... ... ... ... ... ... .... ... .... .... .... .... ... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... .... .... ... .... .... .... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... .... .... .... ... .... .... .... ... ... ... ... ... ... ... ... ... ... .... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq qqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qq
MD
REG
ciclo 2
ciclo 1
ciclo 3
ciclo 4
ciclo 5
ciclo 6
ciclo 7
ciclo 8
tempo (ciclos)
MI
beq
ciclo 9
diminui a vaz˜ao
pode resolver o risco
ao esperar (
stall
)
instr 1
instr 2
MD
REG
MI
RES
RES
REG
MI
MD
RES
REG
MI
MD
RES
instr 3
Previs˜
ao Est´
atica de Desvios
Resolve risco de controle ao
supor qual a dire¸c˜ao tomada
e seguir executando sem esperar pelo
resultado da compara¸c˜ao
1. Prevˆ
e n˜
ao-tomado: sempre prevˆe que desvios
n˜ao ser˜ao tomados
,
continua buscando na seq¨
uˆencia das instru¸c˜
oes (PC+4).
Somente quando o desvio ´e tomado ocorrem bolhas.
Se desvio tomado,
anula
instru¸c˜
oes
ap´os o desvio
– se decis˜ao em MEM →
trˆes bolhas:
BUSCA, DECOD, EXEC
– se decis˜ao em DECOD →
uma bolha:
BUSCA
Implementa¸c˜ao deve garantir que instr anuladas n˜ao mudam o estado
→
f´acil no MIPS porque mudan¸cas de estado ocorrem nos 2 ´
ultimos
est´agios: MEM (mWr) ou RES (rWr)
Busca re-inicia no destino do desvio
(penalidade ≤ 2 bolhas)
Tratamento de Riscos de Controle
•
Tratamento de riscos de controle ´e MUITO importante
pelo impacto no desempenho
⊲
de
1/3 a 1/6 de todas instru¸c˜
oes
s˜ao desvios
⊲
penalidade de um, dois ou trˆes ciclos
⊲
processadores com mais est´agios tem desempenho pior
•
Atrasa instru¸c˜
oes at´e decidir se desvia → perde desempenho
•
Previs˜ao de desvios →
prever dire¸c˜ao do desvio
∗
reduz/elimina penalidade se previs˜ao correta
∗
pode aumentar penalidade quando previs˜ao ´e errada
∗
T´ecnicas:
previs˜ao est´atica
– segue sempre mesmo caminho
previs˜ao dinˆamica
– depende do comportamento do programa
UFPR BCC CI212 2016-2— previs˜ao de desvios 11
Desvios em DECOD
... .... ... .... ... .... .... ... ... .. ... ... .... ... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... . ... ... .... qqqqqqqqq qqqqqqqqq qq qqqqqqqqqqqqqqqqqqq q ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... ... .... ... ... ... qqqqqqqqq qqqqqqqqq qq qqqqqqqqqqqqqqqqqqq q ... ... ... ... ... ... ... ... ... ... ... .. ... qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqqq qqqqq qqqqq qqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqregC
prxPC
A==B & BEQ
EM
MR
opc=BEQ
fwdDaluB
DE
fwdCBD
rWr
mWr
opULA
rDest
✈ qqqqqqqqqqqqqqqqqqqqqqqqqqqq ✈ ✈ ✈ ✈ ✈ ✈ ✈ ✈ ... .. ... ... ... ... ... ... ... . ... . ... ... ... . ... ... ... ... rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr r rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr ... .... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq q ... .. ... ... ... ... qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq q qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq ... . ... rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrr rrrrr rrr rrrrr rrrrr rrrrr rrrrr rrrrr rrrrr rrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrr rr rr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rrr rrr rrr rr rr ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqq .. ... ... .... ... ... ... . .. .... .... .... .... .... .... .. ... .... .... ... ... ... .... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qA
B
4
endLer
P
C
MI
0 1instr
c
b
a
C
1 0M
ender
leDados
escDados
cmp sll 2 ULA 1R
1 0 extSinal 32 16 0Previs˜
ao Est´
atica de Desvios (cont)
Resolve risco de controle ao
supor qual a dire¸c˜ao tomada
e seguir executando sem esperar pelo
resultado da compara¸c˜ao
2. Prevˆ
e tomado: prevˆe que todos os desvios ser˜ao tomados,
prevˆ
e tomado
sempre
causa uma bolha se circuito de previs˜ao em DECOD
Na medida em que a penalidade aumenta (maior n´
umero de est´agios),
previs˜ao est´atica piora desempenho
Com circuito mais complexo ´e poss´ıvel tentar prever comportamento
do desvio
dinamicamente
durante execu¸c˜ao do programa
3. Previs˜
ao Dinˆ
amica de Desvios: prevˆe desvios em
tempo de execu¸c˜ao, usa informa¸c˜ao coletada na execu¸c˜ao
adiante
Erro de previs˜
ao → tomado (❀ anula instru¸c˜ao)
qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qq ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq ... .... ... .... ... .... ... ... ... ... ... ... ... ... ... ... .... ... .... .... .... .... ... .... .... ... ... ... ... ... ... ... ... ... ... . ... ... ... . ... ... ... ... ... .... .... .... .... ... .... .... .... ... ... ... ... ... ... ... ... ... ... ... .. ... ... ... ... ... ... ... ... ... ... .... .... .... .... ... .... .... ... ... ... ... ... ... ... ... ... ... .... ... ... ... .... ... ... ... ... ... .... .... .... .... ... .... .... ... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... .... .... .... ... .... .... ... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqq qqqqqq qqqqqq q qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq q qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq
MD
REG
REG
ciclo 2
ciclo 1
ciclo 3
ciclo 4
ciclo 5
ciclo 6
ciclo 7
ciclo 8
MI
MD
REG
MI
REG
4: beq r1,r2,4
8: sub r4,r1,r5
28: or r8,r1,r9
24: and r6,r1,r7
MI
REG
MD
REG
MD
REG
MI
REG
Para anular instru¸c˜ao na BUSCA, adicionar sinal
BUSCA.flush
que for¸ca 0s no campo do opcode no registrador B/D,
transformando instru¸c˜ao em NOP.
UFPR BCC CI212 2016-2— previs˜ao de desvios 14
Acerto na previs˜
ao → desvio n˜
ao-tomado
qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqqq qq ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qq ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqqq q
MD
REG
REG
ciclo 2
ciclo 1
ciclo 3
ciclo 4
ciclo 5
ciclo 6
ciclo 7
ciclo 8
MI
MD
REG
MI
REG
4: beq r1,r2,2
8: sub r4,r1,r5
N˜ao h´a perda de tempo
Desvios Atrasados
de antes
do destino
ap´
os desvio
add r1,r2,r3
sub r4,r5,r6
add r1,r2,r3
beq r2,r0,dest
...
beq r2,r0,dest
delay slot
...
delay slot
...
add r1,r2,r3
sub r4,r5,r6
...
beq r2,r0,antes
...
delay slot
...
...
add r1,r2,r3
beq r2,r0,dest
...
beq r2,r0,dest
add r1,r2,r3
...
sub r4,r5,r6
...
add r1,r2,r3
...
...
beq r2,r0,antes
...
sub r4,r5,r6
...
Desvios Atrasados
•
Sempre executa a pr´oxima instru¸c˜ao
OK com pipelines simples
i:
beq r1,r0, dst
i+1:
sub r2,r8,r9
sempre ´
e executada
...
dst:
add r3,r4,r5
• ´
E necess´ario que
branch delay slot
seja preenchido
≥ 1
NOP
∗
preenche com instru¸c˜ao
de antes do desvio (i-1)
∗
preenche com instru¸c˜ao
de destino
⋆
SE ´e seguro executar instru¸c˜ao de destino
⋆
ajuda somente no caso do desvio tomado
∗
preenche com instru¸c˜ao
ap´os o desvio (i+2)
⋆
SE ´e seguro executar instru¸c˜ao ap´os o desvio
⋆
ajuda somente no caso do desvio n˜ao-tomado
UFPR BCC CI212 2016-2— previs˜ao de desvios 17
Atrasar a Decis˜
ao
•
Circuito de decis˜ao e c´alculo do endere¸co de destino em DECOD
•
Um
desvio atrasado
sempre executa a pr´oxima instru¸c˜ao (PC+4)
→
desvio tem efeito somente
ap´os
aquela instru¸c˜ao
∗
Montador do MIPS move uma “instru¸c˜ao segura” para a
posi¸c˜ao imediatamente ap´os o desvio,
assim
escondendo
a bolha causada pelo desvio
instru¸c˜ao segura porque n˜ao ´e afetada pelo desvio
•
Em processadores com mais de 5 est´agios e emiss˜ao m´
ultipla,
o atraso no desvio fica maior e necessita mais de uma instru¸c˜ao
⋆
desvios atrasados perderam a vantagem/popularidade para outras abordagens
dinˆamicas mais flex´ıveis (embora mais caras)
⋆
crescimento no n´
umero de transistores dispon´ıveis tornou abordagens
dinˆamicas relativamente baratas
•
Desvios atrasados s˜ao um caracter´ıstica da arquitetura!
Bˆ(
→
CdI MIPS1 define desvios atrasados
Previs˜
ao Dinˆ
amica de Desvios – hardware
✉ ✉ ✉ rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr r rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr r ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ rr rrr rr rrr rrr rr rrr rr rrr rr rrr rr rrr rrr rr rrr rr rrr rr rrr rr rrr rr rrr rrr rr rrr rr rrr rr rrr rr rrr rrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣t
mem
de
instr
P
C
4
desvia?
p?
n
destino corrigido
confirma previs˜ao
DECOD
BUSCA
tabela de previs˜ao de desvios
destino previso
PC indexa tabela e se previs˜ao ´e para tomar desvio (t),
ent˜ao carrega destino previsto no PC
Previs˜
ao Dinˆ
amica de Desvios
Para prever desvios ´e necess´ario:
1. coletar e registrar hist´
orico de cada instru¸c˜ao de desvio
2. registro deve ter “boa qualidade”
3. usar a previs˜ao para antecipar a busca da instru¸c˜ao de destino
UFPR BCC CI212 2016-2— previs˜ao de desvios 20
Escalonamento de instru¸c˜
oes
Compilador pode re-ordenar instru¸c˜
oes para eliminar (algumas) bolhas
muda ordem eliminando conflitos com recursos
risco estrutural
aumenta distˆancia entre produ¸c˜ao e uso de valor
risco de dados
decis˜ao no in´ıcio ou no final do la¸co
risco de controle
original
re-escalonado
1:
lw r1, 0(r10)
lw r1, 0(r10)
2:
add r4, r1, r4
lw r5, 10(r12)
3:
sw r4, 0(r10)
add r4, r1, r4
4:
lw r5, 10(r12)
sub r8, r5, r9
5:
sub r8, r5, r9
sw r4, 0(r10)
6:
add r6, r8, r8
add
r6
, r8, r8
*
7:
sw r6, 20(r12)
sw
r6
, 20(r12)
*
*
dependˆencia em r6 permanece
Previs˜
ao Dinˆ
amica de Desvios (cont)
Exemplo: executa trˆes voltas do la¸co e ent˜ao prossegue:
s sssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss s sssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s ssssssssssssssssssssssssssssssssss s sssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssprevis˜ao
? t t T N t t T N t t T N
resultado
t
t t
n
t
t t
n
t
t t
n
t
certo?
E
E
E
E
E
E
Duas
previs˜oes erradas,
a cada vez que seq¨
uˆencia muda,
ou a cada passagem pelo la¸co
neste exemplo
x = 10;
for (i=0; i<3; i++) {
x = ...
}
z = x - 2;
Previs˜
ao Dinˆ
amica de Desvios (cont)
Tabela com 2
m
bits no est´agio de busca
•
acessa tabela com m bits do PC
∗
tabela cont´em 1 se desvio foi tomado na ´
ultima passada
∗
tabela cont´em 0 se desvio n˜ao foi tomado na ´
ultima passada
•
prevˆe que nesta execu¸c˜ao tomar´a mesmo caminho que na anterior
•
atualiza o bit quando errar a previs˜ao
♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
0
1
1
0
desvio tomado - 1
PC
2
m
elementos
...
desvio n˜ao-tomado - 0
m bits
UFPR BCC CI212 2016-2— previs˜ao de desvios 23
Previs˜
ao Dinˆ
amica de Desvios cont
Uma
tabela com hist´
orico de desvios
(branch history table, BHT)
no est´agio de busca cont´em um bit que indica se o desvio foi tomado
na sua ´
ultima execu¸c˜ao
BHT ´e indexada pelos m bits menos-significativos do PC
Bit pode prever incorretamente:
pode ser de outro desvio com os mesmos m bits-ms do PC,
ou pode ser a previs˜ao errada para esta ‘passada’
→
n˜ao pode afetar corretude, s´
o desempenho
Se previs˜ao ´e errada, anula instru¸c˜
oes incorretas,
re-inicia busca no endere¸co correto, e
inverte bit de previs˜ao
Previsores melhores: correla¸c˜
ao de previs˜
oes
Desvios em instru¸c˜
oes distintas podem ser relacionados:
if (a%2 == 0) {
f1:
for (i=0; i<a; i++) {
...
//
beq r1,r2,f1
}
} else {
f2:
for (j=N; j>a; j--) {
...
//
beq r3,r4,f2
}
}
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rrr rrr rrr rr rrr rrr rrr rrr rr rrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrρ
σ
if (a%2==0)
π
desvios ρ e σ
dependem de π
Previsores melhores: contadores de 2 bits
Contador de dois bits implementa histerese e melhora previs˜ao:
previs˜ao
t
t
t
t
t
t
t
t
t
t
t
t
t
estado
wt st st st wt st st st wt st st st wt
resultado
t
t
t
n
t
t
t
n
t
t
t
n
t
certo?
E
E
E
ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s ssssssssssssssssssssssssssssssssss ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssPrevis˜
oes erradas caem para a metade
neste exemplo.
rrrrrrrrr rrrrrrrrr rrrrrrrr rrrrrrr rrrrr rrrrr rrrr rrrr rrrr rrrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rrr rrr rr rrr rr rrr rrr rrr rrr rrr rrrr rrrr rrrr rrrrr rrrrr rrrrrrrrr rrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrr rrrrrrrrrrrrrr rrrrrrrrr rrrrrrrrr rrrrrrrrr rrrrrr rrrrr rrrrr rrrrr rrrr rrrr rrr rrr rrrr rrr rrr rrr rrr rrr rrr rrr rr rrr rr rrr rrr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rrr rr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrrrr rrr rrrrrr rrrrrr rrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrr rrr rrrrrrrrr rrrrrrrrr rrrrrrrrr rrrrrr rrrrr rrrrr rrrr rrrr rrrr rrrr rrr rrrr rrr rrr rrr rrr rrr rrr rrr rr rrr rr rrr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrrrr rrrrr rrrrr rrrrrrrrr rrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrr rrrrr rrrr rrrr rrrr rrr rrrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rrr rr rr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrrr rrrr rrrrr rrrrrrr rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr r rrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr r rrrrrrrrrrrrrrrrrrr rr rrrrrrrrrrrrrrrrrrrrrrrrr rrr rr rrr rrr rr rrr rrr rr rrr rrr rr rrr rrr rr rrr rrr rrr rrr rr rrr rrr rr rrr rrr rr rrr rrr rr rrr rrr rr rrr rrr rr rrr rrr rrrrrr rrr rrrr rrrr rrrrr rrr rrrr rrr rrrr rrrr rrrrr rrr rrrr rrr rrrrr rrr rrrrr rrr rrrrr rrr rrrrr rrr rrrrr rrr rrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
11
strong
taken
10
weak
taken
n˜ao-tomado
tomado
n˜ao-tomado
n˜ao-tomado
tomado
tomado
01
weak
notTkn
00
strong
notTkn
n˜ao-tomado
tomado
UFPR BCC CI212 2016-2— previs˜ao de desvios 26
Previs˜
ao Dinˆ
amica de Desvios (cont)
Na previs˜ao com um bit, ocorrem duas previs˜oes erradas
a cada mudan¸ca com rela¸c˜ao `a hist´
oria recente
p.ex: executa trˆes voltas do la¸co e ent˜ao prossegue:
previs˜ao
? t t T N t t T N t t T N
resultado
t
t t
n
t
t t
n
t
t t
n
t
certo?
E
E
E
E
E
E
s s s s s s s s ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss s s s s s s s s ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s sssssssssssssssssssssssssssssssssss s s s s s s s s ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssCom este m´etodo s˜ao
duas
previs˜oes erradas
a cada vez que seq¨
uˆencia muda ou a cada passagem pelo loop
Prev. Dinˆ
amica de Desvios – correlacionamento (ii)
if (a%2 == 0) {
π
f1:
for (i=0; i<a; i++)
//
beq r1,r2,f1
π → ρ
} else {
π
f2:
for (j=N; j>a; j--)
//
beq r3,r4,f2
π → σ
}
Hist´oria dos desvios divide
BHT em regi˜oes
previsor deve ser “treinado”
durante execu¸c˜ao
qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq qqqqqqqqqq qqqqqqqqqq qqqqqqqqqqqqqqqqqqqq qq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqq ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqq qqqqqqqqqq qqqqqqqqqqqqqqqqqqqq qq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqq ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣ qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣ ♣00
11
...
10
01
01
BHR
PC
BHT
11
...
10
01
BHR
PC
BHT
01
00
π
σ
π
ρ
Prev. Dinˆ
amica de Desvios – correlacionamento (i)
Correlacionamento de desvios:
Branch History Register (BHR)
´e um reg de deslocamento que
recebe resultado da avalia¸c˜ao da condi¸c˜ao de desvio
m
bits do PC combinados com r bits do BHR indexam BHT
BHR registra hist´
oria dos r desvios mais recentes,
porque estes interferem na escolha do previsor do desvio corrente
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr r rrrr rrrr rrrr rrrrr rrrr rrrrrrrrrrrrrrrrrrrrr rrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr r ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣ ♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣
00
11
...
10
01
BHT
01
BHR
m bits
tomado/n˜ao-tomado
PC
(cond de desvio [de EXEC])
2
m
previsor
deve ser
“treinado”
durante
execu¸c˜ao
UFPR BCC CI212 2016-2— previs˜ao de desvios 29
Previsores melhores: correla¸c˜
ao de previs˜
oes (cont)
if (a%2 == 0) {
f1:
for (i=0; i<a; i++)
//
beq r1,r2,f1
} else {
f2:
for (j=N; j>a; j--)
//
beq r3,r4,f2
}
Portanto a id´
eia ´
e:
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rr rrr rrr rrr rr rrr rrr rrr rrr rr rrr rrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
ρ
σ
if (a%2==0)
π
desvios ρ e σ
dependem de π
•
manter hist´
oria de todos os desvios recentes
=
⇒
hist´
oria aproxima caminho seguido pelo programa
•
Branch History Register
(BHR) ´e um registrador de deslocamento
que mant´em resultado dos ´
ultimos N desvios
•
PC e BHR s˜ao combinados para acessar tabela de previs˜ao
•
taxas de acerto ficam entre 80% e 90%
Interrup¸c˜
oes e Excess˜
oes
•
Interrup¸c˜
oes
∗
geralmente com causa externa ao processador
ass´ıncronas
∗
n˜ao s˜ao relacionadas a uma instru¸c˜ao espec´ıfica
∗
Exemplos: interrup¸c˜ao de dispositivo; falta de energia
•
Excess˜
oes
∗
relacionadas `a execu¸c˜ao de uma instru¸c˜ao espec´ıfica
s´ıncronas
∗
Exemplos: overflow, instru¸c˜ao inv´alida
• Traps
∗
relacionadas `a execu¸c˜ao de uma instru¸c˜ao espec´ıfica
∗
rotina (hw+sw) de tratamento de excess˜oes,
chamadas de sistema
Tabela de Previs˜
ao de Destino
qqqqqqqqq qqqqqqqqqq qqqqqqqqqq qqqqqqq qqqqqqq qqqqqq qqqqq qqqqq qqqqq qqqqq qqqqq qqqq qqqq qqqq qqqq qqqq qqqq qqqqq qqqqq qqqqq qqqqqq qqqqqq qqqqqqqq qqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqq qq qqqqqqqqqq qqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqq qqq ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ qqqqq qqqqq qqqqq qqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣ ♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣♣ qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqq
PC
10
20
habil
20
32
PC
01
11
hist
0x506c add r3, r4, r5
0x5070 slti r8, r10, 100
0x5074 bne r0, r8, -0x1078
0x4000 beq r1, r2, 0x1068
506c
4000
destino
desvio
4000 ≫ 10
5074 ≫ 10
...
indexa tabela com 2
m
elementos com m bits do PC
UFPR BCC CI212 2016-2— previs˜ao de desvios 32
Previs˜
ao Dinˆ
amica de Desvios (cont)
A Tabela de Hist´orico de Desvios (THD) prevˆe quando
o desvio ´e tomado, mas n˜ao diz
para onde ´e
o desvio
Uma
Tabela de Previs˜ao de Destino
(branch target buffer, BTB)
no est´agio de busca mant´em o endere¸co de destino, evitando a bolha.
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr r rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr rr r
prevˆe
desvio
acesso
`a mem
destino
bolha!
PC
computa
altera PC
prevˆe
acesso
desvio
destino
prevˆe
destino
computa
PC
`a mem
altera PC
Interrup¸c˜
oes Precisas
•
Interrup¸c˜
oes Precisas
facilitam MUITO o trabalho do SO
na continua¸c˜ao do programa, ou na depura¸c˜ao
•
Excess˜ao/trap
∗
todas instru¸c˜
oes antes da causadora completam
∗
nenhuma das instru¸c˜
oes ap´os a causadora completam
∗
instru¸c˜ao causadora ou
completou
ou
n˜ao iniciou
∗
PC aponta instru¸c˜ao causadora
•
Interrup¸c˜ao
∗
Mesmo que excess˜ao, mas 6 ∃ instru¸c˜ao causadora
∗
Deve parecer que ocorreu entre instru¸c˜
oes
∗
PC aponta para instru¸c˜ao que seria executada
Interrup¸c˜
oes/Excess˜
oes Precisas
Uma interrup¸c˜ao ou excess˜ao ´e considerada
precisa
se existe
uma ´
unica instru¸c˜ao (ou ponto de interrup¸c˜ao) tal que
todas as instru¸c˜
oes anteriores `aquela tenham alterado o estado,
e nenhuma instru¸c˜ao ap´os (e incluindo) aquela
tenham modificado o estado.
Isso significa que a execu¸c˜ao pode ser re-iniciada a partir do
ponto de interrup¸c˜ao e resultados corretos ser˜ao produzidos
UFPR BCC CI212 2016-2— previs˜ao de desvios 35
Interrup¸c˜
oes e Excess˜
oes – arquitetura
•
Registrador de Interrup¸c˜ao
∗
vetor de bits indicando quais interrup¸c˜
oes/excess˜
oes ocorreram
•
Registrador de m´ascara
∗
vetor de bits indica quais interr/excess˜
oes est˜ao desabilitadas
∗
escrever no registrador de m´ascara ´e
instru¸c˜ao privilegiada
∗
alguns bits podem ser atualizados em modo usu´ario (overflow)
∗
algumas interrup¸c˜
oes/excess˜
oes n˜ao s˜ao mascar´aveis
•
dois modos de execu¸c˜ao:
usu´ario
e
sistema
∗
modo usu´
ario tem poucos privil´egios
– execu¸c˜ao de instru¸c˜ao
privilegiada causa excess˜ao (viola¸c˜ao de previl´egio)
∗
modo sistema pode executar ∀ instru¸c˜ao
– SO tem acesso a
todos os recursos do sistema
Excess˜
ao de Aritm´
etica
qqqqq qqqqq qqqqq qqqqq qqqqqqqqqqqqqqqqqqqqqq qqqqq qqqqq qqqqq qqqqq qqqqqqqqqqqqqqqqqqqqqq qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqq qqqqq qqqqq qqqqq qqqqq qqqqqqqqqqqqqqqqqqqqqqB
D
Ex
M
R
B
D
Ex
M
R
B
D
Ex
M
R
B
D
Ex
R
anulada
excess˜ao (exec)
B
D
Ex
M
R
B
D
Ex
M
R
salta para tratador
in´ıcio do tratador
anulada
M
•
Instru¸c˜
oes anteriores podem completar
•
anula todas instru¸c˜
oes subseq¨
uentes (mais novas)
Implementa¸c˜
ao de interrup¸c˜
oes/traps
•
Precis˜ao ´e importante
•
Interrup¸c˜
oes e excess˜oes simultˆaneas nos v´arios segmentos
∗
interrup¸c˜
oes de E/S – “antes” da busca
∗
busca – falta de p´agina, referˆencia desalinhada, protection fault
∗
decod – instru¸c˜ao ilegal ou privilegiada
∗
exec – excess˜oes de aritm´etica (overflow, divis˜ao por zero)
∗
mem – falta de p´agina, referˆencia desalinhada, protection fault
∗
res – nenhuma
UFPR BCC CI212 2016-2— previs˜ao de desvios 38
Tratamento de interrup¸c˜
oes/traps
Quando ocorre interrup¸c˜ao/trap:
•
efetua salto para rotina do SO
∗
vetor de tratadores, em geral fixado pela arquitetura/CdI
→
CdI mips1 define 3-6,
CdI x86 define 256 (?)
•
computa endere¸co de retorno
•
salva informa¸c˜ao de estado essencial
∗
PC
∗
CCs (condition codes)
∗
PSW (processor status word)
•
troca modo de execu¸c˜ao:
usu´ario
→
sistema
Exerc´ıcios
1) Complemente o desenho da aula passada incluindo todos os
circuitos mostrados nos slides 5 e 10.
2) Complemente o diagrama do slide 5 com os circuitos para as
para as instru¸c˜oes JAL e JR.
3) Como o circuito do slide 5, combinado com um dos m´etodos
de previs˜ao de desvios, resolve seq¨
uˆencias como as abaixo?
A
B
C
end1:
add r1,r2,r3
add r1,r2,r3
add r1,r2,r3
end2:
beq r4,r0,end10
beq r4,r0,end5
beq r4,r0,end10
end3:
sub r5,r6,r7
beq r5,r0,end10
sub r6,r6,r7
end4:
j end20
j end1
beq r8,r0,end10
end5:
xor r8,r9,r9
sub r6,r7,r8
xor r9,r2,r3
end6:
beq r9,r0,end20
4) Projete uma Tabela de Previs˜ao de Destino que armazene o endere¸co de destino.
Qual a organiza¸c˜ao da tabela? Quais cuidados devem ser tomados com a
atualiza¸c˜ao da tabela?
UFPR BCC CI212 2016-2— previs˜ao de desvios 41