Chapter 1: Introduction
1.3 DFM Challenges and Limitations
It is very important to start with the basic understanding of semiconductor design and manufacturing processes prior to discuss the DFM role and challenges in SI. Let us start with the design side where an IC is characterized by electrical parameters (functions) where it undergoes a complex manufacturing process with approximately 200+
operations, 1100+ steps and 8 weeks of processing, however the number of steps and operations vary with the selected technology. A chip is designed using CAD tools and design libraries (reusable blocks of circuits). It follows the design simulation steps where design rules are validated and electrical and parasitic (unwanted) parameters are extracted using SPICE models and technology files. The drifts and variations are adjusted through layout optimization. The design is further simulated using DFM rules and/or models (CAA and hotspot analyses) to find out potential drifts in drawn features and printed images that could result in manufacturability and yield losses. These potential failures are addressed by either changing the design or layout optimization. Upon validation, the design moves to the mask preparation step. The masks are glass plates with an opaque layer of chrome carrying the target chip layout. For one product the mask set consists of 15 to 35 individual masks depending on the technology. They are used to fabricate thousands of transistors and a network of interconnected wires to form an electronic chip (Figure 1.5) on silicon wafer.
Figure 1.5 - Cross section of an electronic chip (transistors and interconnects)
The transistors and interconnects are the geometric shapes which are fabricated through repetitive sequence of deposition, lithography, etching, polishing, measurement, SPC etc. process operations. It is known that the process imperfection results in drift of geometric shapes of transistors a.k.a. devices and interconnects which can ultimately lead to the product failure. The DFM methods are focused on finding such potential drifts and its subsequent resolution by the designer before it enters in the production line. It is quite evident that the role of DFM methods is highly critical as it allows only manufacturable and yieldable designs to move on. In the design flow, we can simply say that the DFM rules and/or models are used to distort the drawn features followed by electrical characterization to ensure the product functionality.
The DFM is inserted in the design flow upon circuit layout completion by the designer, where geometric
shapes are drifted based on the DFM rules and/or models for a given technology. The electronic design automation tools are then used to characterize and extract the electrical and parasitic parameters. The design and wire layout is optimized until these parameters comply with the technology and product specification. To ensure volume production, the DFM methods are used to optimize product masks where geometric shapes are compensated against process drifts to keep printed layout as close as possible to the optimized layout that passed the CAD simulations.
A chip is manufactured on a wafer (Figure 1.6) made from silicon (Si). The wafer is divided in horizontal/vertical lines crossing each other known as the scribe lines. These scribe lines serve dual purpose: (i) they contain test structures used for metrology and/or inspection and (ii) they are used to cut the wafer and separate individual dies (chips). The notch is a cut in the wafer and it is used to describe the crystal orientation and wafer position during process and metrology operations. A site (field) is composed of individual dies whereas the number of dies in a site is characterized by the product mask. In order to monitor intra-die variations the test structures could be placed within the field at different positions. The electronic product undergoes metrology and inspection steps to ensure product quality where decisions are made based on the parametric yield to either scrap or move the wafer to next steps. These measurements are done on the test structures in scribe lines or fields; however, the product itself goes for a functional test at the end of the manufacturing process to sort the bad and good chips.
Figure 1.6 - Structure of the product wafer
Let us discuss the basic DFM concept and its evolution to the current challenges (Figure 1.7 and Figure 1.8).
The designers design a new IC chip and send for manufacturing to assess its manufacturability. The design is then improved based on the recommendations by the manufacturing plant because process imperfection results in printed layout which is deviated from the drawn layout. It results in design respins, delays and costs. To avoid and/or minimize these respins, we simulate the designed chips using design rules and models on the manufacturability, yield and cost criteria. The design rules, DFM rules and models are extracted from the data collected across the production line against significant drifts and variations and this process is equally applicable for the technology alignment and adoption efforts. The success of SI lies in our ability to make the feedback loop more efficient and effective so that newly emerging spatial drifts and variations are quickly analyzed based on huge data volumes collected across the production lines. It shall help in the technology lead times and costs reduction.
Figure 1.7 - The role of DFM in SI
Site Die
Notch Position A
B
0 1 2 3 4 5 6 7 8 9 10
-11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1
0 1 2 3 4 5 6 7 8 9 10 11 12 -13-12 -11-10 -9 -8 -7 -6 -5 -4 -3 -2 -1
0 1 2 3 4 5 6
-1 -2 -3 -4 -6 -5
5
4
3
2
1
0
-1
-2
-3
-4
-5
DFM => Modeling Design and Manufacturing Interface
Manufacturing
Manufacturing Variability Designers
Design Respin
C { Manufacturability, Yield, Cost … }
c c
Models Rules CAD Simulations
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The concept equivalent to “DFM” was coined by Mr. LeBlanc (French) and Mr. Eli Whitney (American) in 1778 and 1788 respectively [Dummer, 1997] by proposing a system for the production of musket. It received an industry wide recognition as “producibility through interchangeable parts”. Mr. Roger W. Bolz is credited for organized DFM methodology [Bolz, 1958] as an alternative term for “producibility”, introduced in his book “The producibility handbook”; however Design for Manufacturability “DFM” received industry wide acceptance around 1960 [Boothroyd, 1968]. Let us formally extend the DFM concept. In the SI it is defined as the ability to reliably predict downstream life cycle needs and issues during early phases of design [Herrmann et al., 2004]. It is focused on economic benefits from the volume production by trading off cost-quality-time triangle [Raina, 2006] and is classified as [Mehrabi et al., 2002] product DFM (producing manufacturable designs within defined processes) and process DFM (developing processes with less rework and high manufacturability). The most appropriate classification of DFM methods in the SI is physical and electrical DFM [Appello et al., 2004]. The physical DFM refers to the process variations that result in geometric shape drifts during manufacturing whereas electrical DFM is focused on the characterization of parametric and functional product yields. The parametric characterization refers to the extraction of key electrical and parasitic parameters whereas functional characterization mainly refers to the signal timing and delays that result in the faulty products to ensure product functionality.
Figure 1.8 - Historical evolution of the DFM
It is evident that most of the manufacturability and yield issues are related with the process imperfection and/or equipment drifts due to which we are not able to accurately print the design layout on silicon wafer (Figure 1.9). Such drifts either result in electrical failures (electrical DFM) or physical failures (physical DFM) ultimately resulting in product failure. The process imperfection leads to the manufacturability and yield loss mechanisms which are classified as systematic or random. The random fault mechanisms can neither be modeled nor controlled but they can be minimized by following robust/recommended rules, however the systematic fault patterns can be transformed into rules and/or models for their subsequent use during CAD simulations. Please refer to section-B.6 of Annexure-B for detailed understanding of most common manufacturability and yield loss mechanisms.
a) IC chip design b) Design layout c) printed layout
Figure 1.9 – Drifts in drawn features and printed imagesIn 1980 the DFM concept was adapted as a yield enhancement strategy in the SI (Figure 1.8). It went very well till 250nm technology [Cliff, 2003 and Radojcic et al., 2009] but after that the increasing complexity of the circuit layout and shrinking sub wavelength lithography resulted in multiple respins and yield losses with 193nm stepper and 130nm node (Figure 1.10). The introduction of the compensation techniques like Optical Proximity Correction (OPC) and Resolution Enhancement Technique (RET) emerged as an extended design flow (DFM flow) to mitigate the yield loss mechanisms. These methods are used during the mask data preparation to ensure manufacturability and yield. Beyond this point the manufacturability and yield losses can only be controlled through process control and recipe adjustments, however new systematic drifts patterns in the printed design layouts resulting in parametric and functional yield losses can be modeled for the technology improvements.
Figure 1.10 - Lithography and feature size [Radojcic et al., 2009]
From above facts it is evident that stretching the CMOS technology below 45nm size is difficult without extending the traditional DFM methodology. The DFM has evolved from design rules to DFM rules like (layout/routing rules) and DFM models like Critical Area Analysis (CAA), Chemical Mechanical Polishing (CMP), Shape, Yield, Leakage and [McGregor, 2007] Statistical Static Timing Analysis (SSTA) to mitigate the potential yield losses. Our efforts are ideally focused to produce first time correct design that can be ramped without manufacturability issues and yield loss. The reasons behind the unsuccessful DFM implementation [Seino et al., 2009] are lack of awareness on the importance of DFM by the product designers [Ahmed and Abdalla, 2000], less understanding of designs influence on the manufacturing, wrong variations analysis, inability to perform multi- source root cause analyses and different perceptions of the engineers/managers. There is one thing common in these DFM methods and it is “Data“.
In this thesis we are primarily focused on improving effectiveness of the R&D effort so that DFM can be put back on track in the technology alignment and adoption processes to exploit the economic benefits. Let us formally define the potential DFM challenges within technology alignment and adoption processes (Figure 1.11). In technology alignment we are focused on process alignment, based on test (representative) products, where data captured across the production line is analyzed using DFM methods (R&D efforts) to find root cause against the yield limitations and model to hardware gaps. These root causes are further classified as systematic or random and transformed into rules and/or models. New rules and/or models are fed back to the technology models for their subsequent use in CAD simulations; however processes are also improved to achieve the target yields.
The design libraries are qualified as per new rules and models (design rules, DFM rules, models) for their subsequent use by the designers as reusable components to reduce the technology lead times. In technology adoption process, we use product prototypes and follow the process alignment link like the one we have seen in the technology alignment in the above paragraph. The data captured from the process is analyzed with Manufacturing For Design (MFD) methods a.k.a. APC/AEC methods to find causes against the drifts and yield losses. The MFD methods differ from the DFM in the sense that they are focused on the process, equipment or recipe adjustments to ensure the manufacturability of a given design whereas DFM provides us with new rules and/or models to ensure a first time correct design. The feedback to the process results in quick and rapid technology adoption for given yield
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targets, however the feedback link to improve the technology do not exist because design kits are frozen at this stage and any proposed change shall need requalification of all design libraries which is costly and time consuming.
Figure 1.11 - The role of DFM in technology alignment and adoption processes
It is evident that the effectiveness of R&D efforts depends on the input data which at present is the single- source (lot/wafer/site); hence, our engineers are not able to exploit the huge data volumes collected across the production line. The goal of this thesis is to find and remove the limiting factors associated with the single-source root cause analysis and provide generic scientific contributions to enable multi-source (lot/wafer/site/die) and test structure position based dynamic data exploitation. It shall result in efficient root cause analysis and effective DFM methods. If the analyses results are quickly transformed into rules and/or models followed by its inclusion in the technology models, the designs shall result in higher yield and manufacturability. It shall also result improvements in technology alignment and adoption lead times and costs. So in order to put DFM back on track we suggest (i) a shift from MFD to DFM efforts and (ii) single-source to multi-source site/die/position based root cause analysis within the technology alignment and adoption processes.