1 ESPRISCV CPU
4.3 Functional Description
4.3.1 Structure
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4 eFuse Controller (EFUSE)
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eFuseController(EFUSE)
Table 41. Parameters in eFuse BLOCK0
Parameters Bit
Width
Hardware Use
Write-Protect Bits in EFUSE_WR_DIS
Description
EFUSE_WR_DIS 32 Y N/A Disable writing of individual eFuses.
EFUSE_RD_DIS 7 Y 0 Disable software from reading eFuse blocks BLOCK4~10.
EFUSE_DIS_ICACHE 1 Y 2 Disable ICache.
EFUSE_DIS_USB_JTAG 1 Y 2 Disable usb-to-jtag function.
EFUSE_DIS_DOWNLOAD_ICACHE 1 Y 2 Disable ICache in Download mode.
EFUSE_DIS_USB_SERIAL_JTAG 1 Y 2 Disable usb_serial_jtag peripheral.
EFUSE_DIS_FORCE_DOWNLOAD 1 Y 2 Disable chip from force-entering Download mode.
EFUSE_DIS_TWAI 1 Y 2 Disable TWAI Controller.
EFUSE_JTAG_SEL_ENABLE 1 Y 2 Set 1 to use jtag directly.
EFUSE_SOFT_DIS_JTAG 3 Y 31 Disable JTAG by programming 1 to odd number of bits. JTAG can be re-enabled via HMAC peripheral.
EFUSE_DIS_PAD_JTAG 1 Y 2 Hardware Disable JTAG permanently.
EFUSE_DIS_DOWNLOAD_ MANUAL_ENCRYPT 1 Y 2 Disable flash encryption in Download boot mode.
EFUSE_USB_EXCHG_PINS 1 Y 30 Exchange USB D+/D- pins.
EFUSE_VDD_SPI_AS_GPIO 1 N 30 Set this parameter to 1 to override the function of the VDD SPI pin and use it as a normal GPIO pin instead.
EFUSE_WDT_DELAY_SEL 2 Y 3 Select RTC WDT timeout threshold.
EFUSE_SPI_BOOT_CRYPT_CNT 3 Y 4
Enable SPI boot encryption and decryption. This feature is enabled when odd number of bits are set in this parameter, disabled other- wise.
EFUSE_SECURE_BOOT_KEY_ REVOKE0 1 N 5 Revoke the first secure boot key when enabled.
EFUSE_SECURE_BOOT_KEY_ REVOKE1 1 N 6 Revoke the second secure boot key when enabled.
EFUSE_SECURE_BOOT_KEY_ REVOKE2 1 N 7 Revoke the third secure boot key when enabled.
EFUSE_KEY_PURPOSE_0 4 Y 8 Key0 purpose, see Table4-2.
EFUSE_KEY_PURPOSE_1 4 Y 9 Key1 purpose, see Table4-2.
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eFuseController(EFUSE)
Parameters Bit
Width
Hardware Use
Write-Protect Bits in EFUSE_WR_DIS
Description
EFUSE_KEY_PURPOSE_2 4 Y 10 Key2 purpose, see Table4-2.
EFUSE_KEY_PURPOSE_3 4 Y 11 Key3 purpose, see Table4-2.
EFUSE_KEY_PURPOSE_4 4 Y 12 Key4 purpose, see Table4-2.
EFUSE_KEY_PURPOSE_5 4 Y 13 Key5 purpose, see Table4-2.
EFUSE_SECURE_BOOT_EN 1 N 15 Enable secure boot.
EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE 1 N 16 Enable aggressive Secure boot key revocation mode.
EFUSE_FLASH_TPUW 4 N 18 Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15, delay will be 7.5 ms.
EFUSE_DIS_DOWNLOAD_MODE 1 N 18 Disable all download boot modes.
EFUSE_USB_PRINT_CHANNEL 1 N 18 Set this parameter to 1, the usb print function will be disabled.
EFUSE_DIS_USB_DOWNLOAD_MODE 1 N 18 Disable the USB OTG download feature in UART download boot mode.
EFUSE_ENABLE_SECURITY_DOWNLOAD 1 N 18 Enable UART secure download mode (read/write flash only).
EFUSE_UART_PRINT_CONTROL 2 N 18
Set UART boot message output mode. 2’b00: Force print; 2’b01:
Low-level print, controlled by GPIO 8; 2’b10: High-level print, con- trolled by GPIO 8; 2’b11: Print force disabled.
EFUSE_FORCE_SEND_RESUME 1 N 18 Force ROM code to send an SPI flash resume command during SPI boot.
EFUSE_SECURE_VERSION 16 N 18 Secure version (used by ESP-IDF anti-rollback feature).
EFUSE_ERR_RST_ENABLE 1 N 19 1: use BLOCK0 to check error record registers; 0: disable such check.
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Table4-2lists all key purpose and their values. Setting the eFuse parameter EFUSE_KEY_PURPOSE_ndeclares the purpose of KEYn(n: 0~5).
Table 42. Secure Key Purpose Values Key Purpose Values Purposes
0 For users (software-only)
1 Reserved
2 XTS_AES_256_KEY_1 (flash/SRAM encryption and decryption) 3 XTS_AES_256_KEY_2 (flash/SRAM encryption and decryption) 4 XTS_AES_128_KEY (flash/SRAM encryption and decryption) 5 HMAC Downstream mode (both JTAG and DS)
6 JTAG in HMAC Downstream mode
7 Digital Signature peripheral in HMAC Downstream mode
8 HMAC Upstream mode
9 SECURE_BOOT_DIGEST0 (secure boot key digest) 10 SECURE_BOOT_DIGEST1 (secure boot key digest) 11 SECURE_BOOT_DIGEST2 (secure boot key digest)
Table4-3provides the details of parameters in BLOCK1~BLOCK10.
Table 43. Parameters in BLOCK1 to BLOCK10
BLOCK Parameters Bit Width Hardware
Use
Write-Protect Bits in EFUSE_WR_DIS
Software Read-Protect
Bits in EFUSE_RD_DIS
Description
BLOCK1 EFUSE_MAC 48 N 20 N/A MAC address
EFUSE_SPI_PAD_ [0:5] N 20 N/A CLK
CONFIGURE [6:11] N 20 N/A Q (D1)
[12:17] N 20 N/A D (D0)
[18:23] N 20 N/A CS
[24:29] N 20 N/A HD (D3)
[30:35] N 20 N/A WP (D2)
[36:41] N 20 N/A DQS
[42:47] N 20 N/A D4
[48:53] N 20 N/A D5
[54:59] N 20 N/A D6
[60:65] N 20 N/A D7
EFUSE_SYS_DATA_PART0 78 N 20 N/A System data
BLOCK2 EFUSE_SYS_DATA_PART1 256 N 21 N/A System data
BLOCK3 EFUSE_USR_DATA 256 N 22 N/A User data
BLOCK4 EFUSE_KEY0_DATA 256 Y 23 0 KEY0 or user data
BLOCK5 EFUSE_KEY1_DATA 256 Y 24 1 KEY1 or user data
BLOCK6 EFUSE_KEY2_DATA 256 Y 25 2 KEY2 or user data
BLOCK7 EFUSE_KEY3_DATA 256 Y 26 3 KEY3 or user data
BLOCK8 EFUSE_KEY4_DATA 256 Y 27 4 KEY4 or user data
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BLOCK Parameters Bit Width Hardware
Use
Write-Protect Bits in EFUSE_WR_DIS
Software Read-Protect
Bits in EFUSE_RD_DIS
Description
BLOCK9 EFUSE_KEY5_DATA 256 Y 28 5 KEY5 or user data
BLOCK10 EFUSE_SYS_DATA_PART2 256 N 29 6 System data
Among these blocks, BLOCK4~9 stores KEY0~5, respectively. Up to six 256-bit keys can be written into eFuse. Whenever a key is written, its purpose value should also be written (see table4-2). For example, when a key for the JTAG function in HMAC Downstream mode is written to KEY3(i.e., BLOCK7), its key purpose value 6 should also be written to EFUSE_KEY_PURPOSE_3.
BLOCK1~BLOCK10 use the RS coding scheme, so there are some restrictions on writing to these parameters.
For more detailed information, please refer to Section4.3.1.3and Section4.3.2.
4.3.1.1 EFUSE_WR_DIS
ParameterEFUSE_WR_DISdetermines whether individual eFuse parameters are write-protected. After EFUSE_WR_DIShas been programmed, execute an eFuse read operation so the new values would take effect.
Column “Write-Protect Bits inEFUSE_WR_DIS” in Table4-1and Table4-3list the specific bits in EFUSE_WR_DISthat disable writing.
When the write-protect bit of a parameter is set to 0, it means that this parameter is not write-protected and can be programmed, unless it has been programmed before.
When the write-protect bit of a parameter is set to 1, it means that this parameter is write-protected and none of its bits can be modified, with non-programmed bits always remaining 0 while programmed bits always remain 1.
4.3.1.2 EFUSE_RD_DIS
Only parameters in BLCOK4~BLOCK10 may be read-protected against software reads, as shown in column
“Software Read-Protect Bits inEFUSE_RD_DIS” of Table4-3. AfterEFUSE_RD_DIShas been programmed, execute an eFuse read operation so the new values would take effect.
If a bit inEFUSE_RD_DISis 0, it means that its parameters are not read-protected against software; if a bit in EFUSE_RD_DISis 1, it means that its parameters are read-protected against software.
Other parameters that are not in BLOCK4~BLOCK10 can always be read by software.
However, even if BLOCK4~BLOCK10 are set to be read-protected, they can still be read by hardware modules, if the EFUSE_KEY_PURPOSE_nbit is set accordingly.
4.3.1.3 Data Storage
Internally, eFuses use hardware encoding schemes to protect data from corruption, which are invisible for users.
All BLOCK0 parameters except forEFUSE_WR_DISare stored with four backups, meaning each bit is stored four times. This backup scheme is not visible to software.
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BLOCK1~BLOCK10 use RS (44, 32) coding scheme that supports up to 6 bytes of automatic error correction.
The primitive polynomial of RS (44, 32) isp(x) =x8+x4+x3+x2+ 1.
Figure 41. Shift Register Circuit (first 32 output)
Figure 42. Shift Register Circuit (last 12 output)
The shift register circuit shown in Figure4-1and4-2processes 32 data bytes using RS (44, 32). This coding scheme encodes 32 bytes of data into 44 bytes:
• Bytes [0:31] are the data bytes itself
• Bytes [32:43] are the encoded parity bytes stored in 8-bit flip-flops DFF1, DFF2, ..., DFF12 (gf_mul_n, where n is an integer, is the result of multiplying a byte of data ...)
After that, the hardware burns into eFuse the 44-byte codeword consisting of the data bytes followed by the parity bytes.
When the eFuse block is read back, the eFuse controller automatically decodes the codeword and applies error correction if needed.
Because the RS check codes are generated on the entire 256-bit eFuse block, each block can only be written once.