A FAULT TOLERANT FPGA BASED
IMAGE ENHANCEMENT FILTER
USING SELF HEALING ALGORITHM
K.SRI RAMA KRISHNA
Professor and Head, Dept. of ECE, V R Siddhartha Engineering College, Vijayawada, Krishna (dist), A.P-520007,
A.GURUVA REDDY*
Professor, Dept. of ECE,
NRI Institute of Technology, Pothavarappadu(V), Agiripalli(M), Krishna (Dt), A.P- 521 212.
M.N.GIRI PRASAD
Principal,
JNTU college of Engg, Pulivendula, Kadapa (dist). A.P – 516390 Abstract:
An original approach to automatic design of image filters is presented in this paper. The proposed solution employs Field Programmable Gate Array reconfigurable hardware at simplified functional level and produces high quality image when image features are corrupted by different types of noise. In addition, parallel architectures can be used to ease the enormous computational load due to different operations conducted on image data sets. Self healing circuit is the one which can compete against traditional designs in terms of quality and implementation cost in Xilinx’s chips. During the first phase, schemes for testing the configured processing elements of a reconfigurable circuit evolved for image enhancement application is presented. In the second phase, the internal Processing Elements in evolved circuit found faulty, they are restructured such that the sparse processing elements replace the faulty processing elements both functionally and structurally. Simulation results show that the evolved circuit is inherently testable and can restructure itself by avoiding the faulty Processing Elements and make use of sparse ones. In third phase implantation of FPGA based image enhancement filter using Virtex-IV application board.
Keywords: Reconfigurable hardware; Processing element; Image enhancement filter; Self healing circuit; Genetic algorithm; Fault tolerant circuit, Intellectual Property.
1. Introduction
Non-linear Image processing [10] with good flexibility and adaptability is highly desirable in several applications such as image transformation, correction of distortion effects, noise removal, histogram equalization etc. Conventional adaptive filter lacks the flexibility for adapting to changes in architecture and is therefore suitable for compensating non-uniform variations in Signal-to-Noise Ratio (SNR). It is also reported that conventional adaptive filter performs well, only when, the spatial density of the noise is less. In this paper, a reconfigurable computing Field Programmable Gate Array (FPGA) architecture [11] is designed for adapting to the changes in task requirements or changes in environment, through its ability to reconfigure its own hardware structure dynamically and autonomously with design objectives such as high performance, specialization and adaptability.
architecture and an associated design methodology that has both flexibility and autonomous restructuring [1] of Processing Elements. The reconfiguration [4] process is achieved using an evolutionary algorithm such as Genetic Algorithm (GA).
2. Reconfigurable Hardware
The reconfigurable hardware consists [1] of configuration bits which is obtain from an image, configuration bits is given as input to the reconfigurable circuit, it evolves the function of each processing element based on the self healing algorithm which is explained in next section. The reconfigurable circuit [2] is designed to give executable program to reconfigure the incoming bits according to the algorithm. The executable program dumped into the Virtex-IV Chip as shown in Figure 1.
Figure 1 Block diagram of Reconfigurable hardware
The VRC is implemented as a combinational circuit using the concepts of pipelining. It consists of processing elements (PE’s) arranged in rows and columns. In this work, a total of 25 PE’s are selected and are arranged in four rows and six columns with the 25th PE representing the final output.
3. Flow Diagram of Reconfiguration in VRC
The configuration bits are obtained using genetic algorithm and are downloaded into the
Evolutionary
[6] reconfiguration circuit which results in relocation of hardware modules inside VRC. The flow diagram of reconfiguration process is shown in figure 2.Figure 2 Flow diagram of VRC using Genetic Algorithm
Configuration
Bits
Reconfigurable
Circuit
Virtex-IV
Chip
Executable
chromosomes. Each chromosome encodes a common set of parameters that describe a collection of electronic components and their interconnections, thus each set of parameter values represents an electronic circuit. The set of all possible combinations of parameter values defines the search space of the algorithm, and the circuits that they represent define the solution space of the algorithm.
4. Self Healing Algorithm for Image Noise Filtering
The Self Healing algorithm for noise removal in the image is performed as follows: 1. Read the corrupted image and store it in input buffer
2. Generate initial population of size ‘n’ with each of chromosome length L. Each chromosome contains details of the interconnection between PE’s and the function to be performed by the PE.
3. For each chromosome in the population
a. Take 3x3 overlapping window and input the nine pixel value to the VRC which processes and replaces the center pixel. Every pixel value of the filtered image is processed using a corresponding pixel and its eight neighbors. This process is illustrated in Figure 3 and is repeated for the whole image.
b. Calculate the mean difference per pixel using the reference image and assign it as the fitness value.
c. Retain the chromosome that has maximum fitness.
Figure 3 Different Pixel Windows processed by the evolved circuit In Figure 3, Ip,q represents the pixel value at pth row and qth column respectively.
4. Apply the crossover and mutation operation on the selected chromosome to get the next generation strings. The roulette wheel selection procedure is chosen here.
5. Replace the old population
6. Repeat from step 3 for a specified number of generations ‘N’.
5. FPGA Implementation
In order to create FPGA design [7], a designer has several options for algorithm implementation. Originally intended as a simulation language, VHDL (Very high speed integrated circuit Hardware description Language) represents a formerly proprietary hardware design language. VHDL was chosen as a target design language in this work because of its familiarity and wide-ranging support, both in terms of software development tools and vendor support. In the first stage, a design is created using VHDL, in the next stage syntax of the code is verified and the design is synthesized or compiled into a library. Then the design is simulated to check its functionality. Finally the design is processed with vendor-specific place-and-route tools and mapped onto a specific FPGA in software.
I
1,2I
1,3I
1,4I
2,2I
2,3I
2,4I
3,2I
3,3I
3,4I
1,1I
1,2I
1,3I
2,1I
2,2I
2,3I
3,1I
3,2I
3,3Stage I 1st 3x3 window represented to VRC and I2 2 replaced by filter output
The VHDL code of the algorithm described in the previous section is developed and imported into the Xilinx FPGA image processing board. The Evolvable hardware [9] is configured for accepting nine 8-bit inputs I0 – I8 and produce a single 8-bit output which processes gray-scaled (8 bits/pixel) images. Every pixel value of the filtered image is calculated using a corresponding pixel and its eight neighbors. The operation performed on the selected input pixels depends on the configuration bits downloaded into the configurable memory from the genetic unit. The VRC consists of 25 PEs as shown in Figure 4. Four PEs are implemented at a single stage of the pipeline.
Each PE can process two 8-bit inputs and produce a single 8-bit output. The outputs of PEs are equipped with registers. The two inputs of every PE can be connected to one of the outputs from the previous l columns where l is the level back parameter.
The configuration bit stream consists of ten bits for each PE. The output of the PE is given by
}
sel3
mux(sel2),
mux(sel1),
{
F
Output
(1)The fewer the functions, the faster is the evolution. Further functions can be included depending on the resource requirements, as there is a trade-off between the functionality and the complexity of the hardware structure.
To deal with the existence of good and bad parts, it is necessary to propose a fault tolerant [5] model, i.e., a model to detect the occurrence of a fault. The most popular model is the Stuck-At model. The short circuit/open circuit model can be a closer fit to reality, but is harder to incorporate into logic simulation tools. In stuck at model, a faulty gate input is modeled as S-A-0 or S-A-1. These faults most frequently occur due to gate oxide shorts or metal to metal shorts. In this work, the power consumed by each PE is monitored and is used as an indication of the healthy or unhealthy status of a PE. It is observed that the variation in power level is sufficient enough to detect the occurrence of S-A-0 and S-A-1 fault.
6. Evolved Architecture
An architecture evolved for filtering the noise using C language is present shown in Figure 4. Nine inputs (pixel values) are used to calculate a new pixel value. The parameters of the evolved network are: 9 inputs, 1 output, circuit topology 6x4, l-back=2. Only utilized programmable elements are highlighted.
Figure 4 Virtual Reconfigurable Circuit
7. VHDL Implementation Results
Figure 5 Simulation of VRC
Figure 6 Schematic diagram of VRC
Figure 8 Internal schematic of Processing Element
The standard test image, Lena as shown in figure 9a is used for study and the results. In figure 9b shows Additive Gaussian noise with mean 0 and standard deviation 0.05 is added. The results obtained with Median filter and proposed image enhancement filter are shown in Figure 9c and 9d respectively. It is observed that Median Filter does not effectively remove Gaussian noise and performs only in edge regions, with blur effects still present in continuous regions. The image enhancement filter performed well both in edge and continuous regions and effectively removed Gaussian noise.
Figure 9 a: Original Image, Figure 9 c: Restored image using Median filter Figure 9 b: Gaussian noise added image Figure 9 d: Restored image using Image enhancement filter
8. Conclusion
A fault tolerant FPGA based image enhancement filter was presented in this work. The fault tolerant model gives Virtual Reconfigurable circuit consisted of multiple Processing Elements and autonomous restructuring of internal processing elements of an evolved FPGA circuit.It is shown that it is possible to successfully evolve noise removal filters that produce better image quality than a standard median filter using self healing algorithm and this part is performed inside the FPGA along with the VRC
References
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[9] Murakawa, M. et al.: Evolvable Hardware at Function Level. In: Proc. of the Parallel Problem Solving from Nature PPSN IV, LNCS 1141, Springer-Verlag Berlin, pp. 62–72, 1996.
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