Enhancing the bandwidth of a-IGZO TFT amplifiers using circuit design techniques

September, 2019

Ricardo Martins Felício Marques Rodrigues

[Nome completo do autor]

[Nome completo do autor]

[Nome completo do autor]

[Nome completo do autor]

[Nome completo do autor]

[Nome completo do autor]

[Nome completo do autor]

Bachelor in Micro and Nanotechnologies Engineering

[Habilitações Académicas] [Habilitações Académicas] [Habilitações Académicas] [Habilitações Académicas] [Habilitações Académicas] [Habilitações Académicas] [Habilitações Académicas]

Enhancing the Bandwidth of a-IGZO TFT

Amplifiers Using Circuit Design Techniques

Dissertation submitted in partial fulfillment of the requirements for the degree of

Master of Science in

Micro and Nanotechnologies Engineering

Adviser: Dr. Pedro Barquinha, Associate Professor, Faculty of Sciences and Technology NOVA University of Lisbon

Co-adviser: Dr. Pydi Ganga Bahubalindruni, Assistant Professor, Indian Institute of Technology Goa

iii Enhancing the Bandwidth of a-IGZO TFT Amplifiers Using Circuit Design Techniques

Copyright © Ricardo Martins Felício Marques Rodrigues, Faculty of Sciences and Technology, NOVA University of Lisbon.

The Faculty of Sciences and Technology and the NOVA University of Lisbon have the right, per-petual and without geographical boundaries, to file and publish this dissertation through printed copies reproduced on paper or on digital form, or by any other means known or that may be invented, and to disseminate through scientific repositories and admit its copying and distribution for non-commercial, educational or research purposes, as long as credit is given to the author and editor.

v "If you think you can do a thing or think you can't do a thing, you're right."

vii

Acknowledgments

Finalizing this thesis ends a chapter of my life that I’m so grateful to cherish. This section is reserved to mention and acknowledge those that were important to the completion of this final task. For that, I would like to thank:

In first place, Professor Rodrigo Martins and Professor Elvira Fortunato for the genesis of the excellent Micro and Nanotechnology Engineering course for which I’m honored to have been part of in its first decade of existence. To complement it, the excellent institutions CEN-IMAT|i3N and CEMOP were also created by these professors, together with DCM, where nu-merous advances are performed in the vanguard of technology and where I had the honors of learning the vast concepts that encompass all that was taught in this course.

My supervisor, Professor Pedro Barquinha, that even though most of my work was out-side his area of expertise, had pivotal contributions for the completion and organization of this master thesis.

To my co-supervisor, Professor Pydi Ganga, for all the hours spent in Skype teaching me about electronics and simulations, for always pushing me to work hard and getting better and better results and for giving me access to the machine that hosted Cadence,

To Professor Luis Oliveira from DEE that helped me figure out how to finally measure the negative capacitance.

To Professor Nuno Correia from Uninova that provided me access to the machines that hosted Cadence with a-IGZO and CMOS technology.

To all the professors from DCM and DEE that sparked my curiosity in the most diverse themes in microelectronics and nanotechnology overall and for all the hours spent teaching and guiding me throughout the course.

To Ângelo Santos for teaching me how to design the different layouts for future fabrica-tion of the amplifiers.

À minha família por todo o apoio que me deram ao longo destes 23 anos da minha vida e a quem devo maior parte do que sou, nomeadamente aos meus pais Ana e Jorge, à chata da minha irmã Maria, a todo o carinho dado pela minha prima Inês e pela minha tia Gina e tio Kiko, à minha prima Joana, Sérgio e Rita. Também ao meu tio Daniel que sem ele isto não seria

viii

possivel, começando pela ajuda na decisão da escolha de curso. Isto também sem esquecer uma das pessoas que me vai estar no coração para sempre e que para tal nunca esquecerei os momentos maravilhosos da minha infância ao lado da minha Avó Raquel.

A ti Inês, por todos os momentos de carinho, amor, riso, tristeza e saudade que me fize-ram crescer a olhos vistos ao longo destes cinco anos. A todas as doidices que vivemos, viagens que fizemos e momentos inesquecíveis que desfrutamos, o mais sincero obrigado por estares ao meu lado. Espero ser a teus olhos tudo aquilo que és aos meus.

O clássico agradecimento aos bacanos do chat, ao cão dos roketes que é o Digas Barrigas, ao artista/tradutor/programador/cebola/RP do Lux/buzina Simão, ao meu amigo carteiro Nuninho Bartolomeu, ao pressionador profissional de dâblius Bernas (primo do cão), ao d-d-d-Diogo Sabino, ao meu faqueiro favorito pelas incontaveis horas passados juntos big Fred, ao melhor produtor da FCT G.U.I., ao João Rodrigues que se sente sempre só, ao meu melhor amigo Matakes (caroxo) pelo qual ainda espero a minha fita, ao Martini Vermelho.. e ao Ro-drigo esse animal do campo que está sempre correto no que diz. Que a nossa amizade seja duradoura.

A todos os outros que dão sentido à existência do curso, Tó géniozinho, Carol, Rolo mano do 158, Carlos Streamer, Inês Tavares, Joan, Neto, João Viera, Mafalda e todos os restan-tes que me possa ter esquecido.

ix

Abstract

Amorphous oxide thin-film transistor (TFT) technology has become central in flexible and low-cost electronic applications. However, there are some limitations of the technology for circuit implementation, particularly the lack of stable and reproducible p-type oxide TFTs, limited speed due to poor semiconductor mobility and to large channel lengths when com-pared to single crystalline Si devices. These limitations demand novel circuit design tech-niques using only n-type TFTs to achieve high-speed circuits meeting the requirement of prac-tical applications. This work aims to improve the low unity current gain frequency of opera-tion of a-IGZO based amplifiers using only circuit-based techniques, without changing the device structure, fabrication steps and materials. To achieve this objective, a generated nega-tive capacitance is connected in parallel to the output node of an oxide TFT based amplifier, reducing the total effective capacitance present at this node. The output pole is shifted to a higher value, improving significantly the frequency response of the amplifier.

Simulations in Cadence environment were performed in five different amplifier struc-tures, employing a-IGZO TFTs based on an in-house model developed with artificial neural networks. Up to three-fold improvement on bandwidth was verified, with minimal increases in power consumption and chip area. The concepts explored here are thus quite relevant to enhance low-MHz range circuits, as required for RFID and biomedical applications.

Keywords: Negative Miller Capacitance Compensation; a-IGZO TFT; Unity Current

xi

Resumo

A tecnologia de transístores de filme fino (TFT) baseados em óxidos amorfos tem-se tor-nado central em aplicações eletrónicas flexíveis de baixo custo. No entanto existem limitações da tecnologia quanto à implementação em circuitos, tais como a falta de TFTs de óxidos de tipo-p estáveis e reproduzíveis, limites na velocidade do dispositivo devido à baixa mobili-dade do semicondutor e grandes dimensões do dispositivo quando comparadas com disposi-tivos de Si cristalino. Estas limitações requerem técnicas de design de circuitos inovadoras que apenas utilizem transístores de tipo-n capazes de permitir a criação de circuitos de altas velo-cidades que cumpram os requisitos das aplicações práticas. Este trabalho procura melhorar a baixa frequência de ganho de corrente unitário de funcionamento dos amplificadores basea-dos em a-IGZO, usando apenas técnicas de design de circuito, sem mudar a estrutura do dis-positivo, passos de fabricação, condições do processo e materiais. Para atingir este objetivo, uma capacitância negativa é conectada em paralelo ao nó de output de um amplificador base-ado em TFTs de a-IGZO, reduzindo a capacitância total presente neste nó. Isto causa uma mudança do polo do output para valores mais elevados, melhorando significativamente a res-posta em frequência do amplificador.

Simulações em ambiente Cadence foram realizadas em cinco estruturas diferentes, utili-zando TFTs de a-IGZO baseados num modelo caseiro desenvolvido com redes artificiais neu-rais. Melhorias de banda até três vezes o valor original são reportadas, com aumentos mínimos de consumo de energia e de área ocupada. Os conceitos aqui explorados são relevantes para a melhoria de circuitos com operação a poucos MHz, como é necessário para RFIDs ou aplica-ções biomédicas.

Palavras-Chave: Compensação com Capacitâncias Negativas de Miller; a-IGZO TFT;

xiii

Contents

List of Figures ... xv

List of Tables ... xvii

Symbols ... xix

Acronyms ... xxi

1 Motivation and Objectives ... 1

2 Introduction... 3

2.1. The Evolution of the TFT Technology... 3

2.2. Different TFT Structures and Operation Principle ... 4

2.3. Challenges of AOS TFT Based Amplifiers ... 6

3 Methodology ... 9

3.1. Simulation Conditions and Tools ... 9

4 Results and Discussion ... 11

4.1. Negative Capacitance Generation ... 11

4.1.1. Miller theorem ... 11

4.1.2. Negative Capacitance Generator ... 12

4.2. CMOS Proof of Concept ... 13

4.2.1. Single-ended Cascode with Bootstrapping ... 14

4.3. Bandwidth Enhancement of a-IGZO TFT based amplifiers with NCG ... 15

4.3.1. Negative Capacitance Generator ... 16

4.3.2. Positive Feedback Differential Amplifier ... 18

4.3.2.1. Positive feedback differential amplifier frequency response ... 19

4.3.3. Single-ended and Differential Cascode with Bootstrapping ... 21

4.3.3.1. Single-ended and differential cascode with bootstrapping frequency response ... 23

4.3.4. Amplifier Using Bootstrap Gain Enhancement and Common Mode Feedback ... 24

4.3.4.1. Amplifier using bootstrap gain enhancement and common mode feedback frequency response 26 4.3.5. Pseudo CMOS Based Amplifier ... 28

xiv

5 Conclusions and Future Perspectives ... 31

Bibliography ... 33

A Cadence Virtuoso Schematics ... 37

xv

List of Figures

Figure 2.1 – Cross sectional schematic of the four most used setups in n-type TFT, based on [11]. ... 5 Figure 2.2 – Measured characteristic curves of an a-IGZO TFT, adapted from [23]. (a)

Transfer characteristics with different TFT channel lengths, with 𝑉𝐷𝑆 = 16 V and W = 20 µm. (b) Output characteristics with 𝑉𝐺𝑆 from -2 V to 8 V values for L = 40 µm. ... 6 Figure 4.1 - (a) Amplifier schematic with a feedback capacitor and (b) equivalent circuit

schematic representing the Miller effect. ... 12 Figure 4.2 - Schematic of different negative capacitance generators. (a) Differential NC pair.

(b) Drain input cross-coupled NC circuit. (c) Source input cross-coupled NC circuit. Adapted from [31]. ... 13 Figure 4.3 - Block diagram of the NCG integrated with the amplifier. ... 13 Figure 4.4 - (a) Simulated negative capacitance values for different pairs of cross-coupling

capacitors and (b) respective frequency response. ... 14 Figure 4.5 - MOSFET amplifier before and after the NCG application (a) Gain. (b) Phase. .... 15 Figure 4.6 - Different circuit characteristics for each value of cross-coupling capacitors

dimensions in the NCG. (a) Gain. (b) Phase. (c) Generated capacitance. ... 16 Figure 4.7 - (a) NCG full layout design with external pads. (b) NCG detail. ... 18 Figure 4.8 - Positive feedback based differential amplifier (a) schematic and (b) small-signal

equivalent. ... 19 Figure 4.9 - (a) Positive feedback based amplifier with NCG full layout design with external

pads. (b) Amplifier plus NCG detail. ... 19 Figure 4.10 - Positive feedback amplifier with and without NCG application (a) gain plots,

and (b) phase plots. ... 20 Figure 4.11 - (a) Single-ended and (b) differential cascode with bootstrapping schematic. (c)

Single-ended cascode with bootstrapping small-signal equivalent and (d)

feedback path schematic. ... 22 Figure 4.12 - (a) Single-ended cascode with bootstrapping with NCG full layout design with

xvi

bootstrapping with NCG full layout design with external pads. (b) Amplifier plus

NCG detail. ... 22

Figure 4.13 - Single-ended cascode with bootstrapping with and without NCG application (a) gain, and (b) phase frequency response plots. Differential cascode with bootstrapping with and without NCG application (c) gain, and (d) phase frequency response plots. ... 24

Figure 4.14 - Amplifier using bootstrap gain enhancement and CMFB (a) schematic, (b) feedback path, and (c) small-signal equivalent circuit for the differential output. 26 Figure 4.15 - (a) Bootstrap gain enhancement with CMFB based amplifier with NCG full layout design with external pads. (b) Amplifier plus NCG detail. ... 26

Figure 4.16 - Amplifier using bootstrap gain enhancement and CMFB with and without NCG application (a) gain, and (b) phase frequency response plots. ... 27

Figure 4.17 - Pseudo-CMOS based amplifier (a) schematic and (b) small-signal equivalent circuit for the first stage output. ... 29

Figure 4.18 - (a) Pseudo-CMOS based amplifier with NCG full layout design with external pads. (b) Amplifier plus NCG detail. ... 29

Figure 4.19 - Pseudo-CMOS based amplifier with and without NCG application (a) gain, and (b) phase frequency response plots. ... 30

Figure A.1 - NCG schematic using MOSFETs. ... 37

Figure A.2 - Single-ended cascode with bootstrapping schematic with NCG, using MOSFETs. ... 37

Figure A.3 - NCG schematic using a-IGZO TFTs. ... 38

Figure A.4 - Positive feedback based amplifier schematic using a-IGZO TFTs. ... 38

Figure A.5 - Single-ended cascode with bootstrapping schematic using a-IGZO TFTs. ... 39

Figure A.6 - Differential cascode with bootstrapping schematic using a-IGZO TFTs. ... 39

Figure A.7 - Gain enhacement with common-mode feedback amplifier using a-IGZO TFTs. 40 Figure A.8 - Pseudo-CMOS based amplifier using a-IGZO TFTs. ... 40

xvii

List of Tables

Table 2.1 - Comparison of TFT technologies with different semiconductor layers, based on [6]–[8], [10], [11], [17], [18]. ... 4 Table 4.1 – Parameter comparison for different capacitance values of the cross-coupling

capacitors. ... 17 Table 4.2 - Summary of the results obtained from the simulated application of the NCG to

the positive feedback based amplifier. ... 21 Table 4.3 - Summary of the results obtained from the simulated application of the NCG to

the Single-ended and differential cascode with bootstrapping. ... 23 Table 4.4 - Summary of the results obtained from the simulated application of the NCG to

the amplifier with bootstrapping gain enhancement and CMFB. ... 28 Table 4.5 - Summary of the results obtained from the simulated application of the NCG to

the Pseudo-CMOS based amplifier. ... 30 Table 5.1 – State of the art, and simulation values before and after NCG comparison for the

different amplifiers. State of the art examples include output loads and are fabricated circuits. (a) Positive feedback differential amplifier. (b) Single-ended cascode w/ bootstrapping. (c) Differential cascode w/ bootstrapping. (d) Amplifier using bootstrap gain enhancement and CMFB. (e) Pseudo-CMOS based amplifier. ... 32 Table B.1 – Different component dimensions for the a-IGZO NCG and the different

xix

Symbols

𝐴𝑓 Feedback Gain

𝐶𝑜𝑥 Gate dieletric capacitance per unit area 𝑓𝑇 Unity current gain frequency

𝑔𝑚 Transistor’s transconductance 𝑔𝑑𝑠 Transistor’s channel conductance

𝐼𝐷𝑆 Current flow between the drain and source 𝑉𝐷𝑆 Voltage between drain and source

𝑉𝐺𝑆 Voltage between gate and source

𝑉𝑇 Threshold voltage

𝜇𝐹𝐸 Field-effect mobility 𝜇𝑆𝐴𝑇 Saturation mobility

xxi

Acronyms

a-Si:H Hydrogenated Amorphous Silicon a-IGZO Amorphous Indium-Gallium-Zinc-Oxide

AOS Amorphous Oxide Semiconductor

AMOLED Active Matrix Organic Light-Emitting Diode ANN Artificial Neural Network

CMFB Common Mode Feedback

CMOS Complementary Metal-Oxide Semiconductor

DRC Design Rule Check

EC Equivalent Circuit

FET Field Effect Transistor

GBW Gain Bandwidth Product

LTPS Low-Temperature Polycrystalline Silicon

LVS Layout Versus Schematic

MOSFET Metal Oxide Semiconductor Field-Effect Transistor NCG Negative Capacitance Generator

OTFT Organic Thin-Film Transistor RFID Radio Frequency Identification SRAM Static Random-Access Memory

TFT Thin-Film Transistor

1

1

Motivation and Objectives

In the past few years, there has been a renewed importance in amorphous Indium-Gal-lium-Zinc-Oxide Thin-Film (a-IGZO) thin-film-transistor (TFT) technology. It shows outstand-ing electrical characteristics when compared to other TFT technologies that allow flexible elec-tronics, such as, amorphous silicon or organic-based semiconductors. Coupling this fact with the possibility of low-temperature fabrication in low-cost large-scale environment creates a whole new range of applications. Examples such as RFID [1] or biomedical wearables [2] re-quire oxide TFT circuits (especially OpAmps) operating at MHz ranges, while state of the art work is mostly limited to kHz ranges [2–4] due to inherent technology limitations and para-sitics due to large device dimensions.

This substantial effort to enhance even further the performance levels of flexible, low-cost technology must be divided into different areas, such as picking the right semiconductors, optimizing the various fabrication steps and developing new circuit design techniques. With a-IGZO TFTs having a mobility at least one order of magnitude lower than the complementary metal-oxide semiconductor (CMOS) devices there is a demand for high-speed design tech-niques at circuit level [5]. The main objective of this work will consist in translating a negative Miller capacitance technique, that has been applied successfully in CMOS circuits as a band-width enhancer, to amorphous oxide semiconductor (AOS) TFT technology as to mitigate one of the major drawbacks that are present in this field.

The application of this novel technique to a-IGZO TFT based circuit blocks throughout this work is done through various steps such as the design and simulation confirmation of a working negative Miller capacitance generator in CMOS technology, followed by the design of various amplifiers based in a-IGZO TFTs but instead with nMOS transistors, which operate under a much more precise and studied model. This negative capacitance will then be con-nected to the outputs of the different amplifiers, as a proof of concept. After the confirmation, this technique will then be translated into a-IGZO TFT based amplifiers.

3

2

Introduction

In this chapter an introductory overview of the major topics addressed in this thesis will be given, focusing the oxide TFT’s technological evolution and current state of the art, most common structures, operation principle and limitations of the technology in circuit design. There is a constant need for the enhancement of the properties of the circuits based on this technology. For that purpose, novel circuit design techniques must be studied.

One main area in which TFTs are being widely used is in flexible and transparent tech-nology, due to the ability of low-cost and low-temperature fabrication, allowing for produc-tion over a large area in flexible substrates.

2.1. The Evolution of the TFT Technology

In the past few years, research involving all the different segments of the TFT technology has been blooming [6]. a-Si:H, organic and low-temperature polycrystalline silicon TFTs (LTPS TFTs) are a few examples of these advances [7]–[10]. There isn’t, however, a technology that simultaneously allows large-scale fabrication, flexible substrates, and optimal electrical per-formance.

All these factors taken into consideration lead to the pursuit of new technologies. This is how the focus on oxide TFTs started to grow in the last years. While presenting a low produc-tion cost and processing temperatures, oxide TFTs have shown outstanding mobility values compared to its counterparts, coupled with large scale fabrication [11]–[13]. Oxide TFTs started gaining ground with Nomura et al. in 2003 [12] with a single-crystalline IGZO semi-conductor layer TFT that, while displaying a great electrical performance with a mobility of 80 cm2 _V-1 _s-1_{, still required a processing temperature of 1400°C, and later in 2004 [13], when} the same group presented results with an amorphous IGZO based TFT fabricated at room temperature, capable of showing a mobility of 9 cm2_V-1_s-1_{, threshold voltage of 1 to 2 V and an} on/off ratio of 103_{. In Table 2.1 it is possible to observe a summary of the different TFT} tech-nology characteristics. With each passing year, oxide TFTs are becoming more central due to the exceptional inherent properties. The most studied and therefore optimized oxide TFT is based on the a-IGZO semiconductor. There are, although, other very promising oxide TFTs

Chapter 2 - Introduction

4

based on other oxides such as ZnO, with a processing temperature of 90 °C and a 7.53 cm2 _V-1 s-1 _{mobility [14] or zinc-tin-oxide (ZTO) showing a mobility of 27.3 cm}2 _V-1 _s-1 _{with a 500°C} processing temperature [15]. The search for p-type oxide TFTs is also ongoing, as oxide p-type TFTs using SnOx were reported presenting a 0.87 cm2 V-1 s-1 mobility with a maximum pro-cessing temperature of 400 °C [16].

Table 2.1 - Comparison of TFT technologies with different semiconductor layers, based on [6]– [8], [10], [11], [17], [18].

Oxide TFT a-Si:H TFT LTPS TFT Organic TFT Mobility (cm2 _V-1 _s-1_{) <60 <1 <100 <10}

Aging Stability Good Good Good Poor

Processing Temperature (°C) RT - 300 200-300 <500 RT

Fabrication Process

Sputtering, Print-ing or

Solution-based

PECVD Laser Excimer & CVD

Evaporation, Printing or

Solu-tion-based Uniformity Good Good Poor Poor Flexibility Yes No No Yes Transparency Yes No No Yes Device NMOS NMOS CMOS PMOS

Oxide TFTs based in a-IGZO do present great electrical properties, as seen in [19]. The different fabrication processes are also being expanded, such as solution-based processes, where the ability to not use photolithographic masks makes this a low-cost process. Y. S. Rim

et. al. produced, at room temperature, an a-IGZO TFT through solution-based processes, with

a mobility of 22.16 cm2 _V-1 _s-1_{. Combining all these different factors turns oxide-based TFTs into} a very promising technology for circuit integration in the most varied applications such as RFID tags [1], biomedical wearable devices [2], AMOLED backplanes [20] or even touch sen-sors [21].

2.2. Different TFT Structures and Operation Principle

The TFT is essentially a FET, comprised of three terminals, the gate, source and drain electrodes, a semiconductor layer and a dielectric layer. The semiconductor layer is placed

Chapter 2 - Introduction

5

between the drain and the source terminals while the dielectric layer is placed between the semiconductor layer and the gate terminal. The most common setups of these layers can be seen in Figure 2.1, the architectures vary from each other through the location of the three terminals relative to the semiconductor layer.

TFTs operate through the control of current flow (𝐼𝐷𝑆) between the drain and source ter-minal by the voltage applied to the gate and drain terter-minal (𝑉𝐺𝑆 and 𝑉𝐷𝑆), exactly like other FET devices. Considering an n-type TFT, its operation principle is defined as enhancement mode (usually called as normally off), or as depletion mode (in this case normally on), if the threshold voltage value (𝑉𝑇) is positive or negative, respectively. Generally, the enhancement mode of operation is preferred since it requires no voltage value applied at the gate to turn the transistor off, minimizing power dissipation and simplifying circuit design, as opposed to de-pletion mode [22].

Figure 2.1 – Cross sectional schematic of the four most used setups in n-type TFT, based on [11].

If 𝑉𝐺𝑆≪ 𝑉𝑇 the transistor is in its off state or subthreshold region, as there is almost no conductive channel between the source and drain, resulting in a very low 𝐼𝐷𝑆 value. If there is a positive value of voltage between the drain and source (𝑉𝐷𝑆), and 𝑉𝐺𝑆 > 𝑉𝑇 the transistor will be in it's on state. This is due to the electrons in the semiconductor (which is inherently n-type) accumulated near the dielectric and semiconductor interface which forms a conductive channel, resulting in a current flow from drain to source.

The IV characteristic curves of an a-IGZO TFT can be seen in Figure 2.2, and through the output characteristics (b) it is possible to define the two different regimes. The linear regime

Chapter 2 - Introduction

6

can be observed when 𝑉𝐷𝑆 < 𝑉𝐺𝑆− 𝑉𝑇, which results in a linear increase in 𝐼𝐷𝑆, and can be ex-pressed by:

𝐼𝐷𝑆≈ 𝜇𝐹𝐸. 𝐶𝑜𝑥 𝑊

𝐿 ((𝑉𝐺𝑆− 𝑉𝑇)𝑉𝐷𝑆) (2.1)

where 𝐶𝑜𝑥 is the gate dielectric capacitance per unit area in F/cm2, 𝜇𝐹𝐸 is the field-effect mobility in cm2 _V-1 _s-1 _{and W and L are the width and length of the TFT channel, respectively.}

The other regime occurs when 𝑉𝐷𝑆 > 𝑉𝐺𝑆− 𝑉𝑇, and the TFT is said to be in saturation mode. The TFT’s semiconductor layer close to the drain becomes depleted and the pinch-off effect takes place. Saturation mode is highly relevant for amplifier implementation and can be represented by:

𝐼𝐷𝑆 ≈ 𝜇𝑆𝐴𝑇. 𝐶𝑜𝑥 𝑊

2𝐿(𝑉𝐺𝑆− 𝑉𝑇)

2 _(2.2)

where 𝜇𝑆𝐴𝑇 is the saturation mobility in cm2 V-1 s-1.

Figure 2.2 – Measured characteristic curves of an a-IGZO TFT, adapted from [23]. (a) Transfer characteristics with different TFT channel lengths, with 𝑉𝐷𝑆 = 16 V and W = 20 µm. (b) Output characteristics with 𝑉𝐺𝑆 from -2 V to 8 V

values for L = 40 µm.

2.3. Challenges of AOS TFT Based Amplifiers

The unity current gain frequency (𝑓𝑇) dictates the maximum frequency at which the TFT behaves in an expected way, limiting its efficient use. This value can be expressed by:

𝑓_𝑇≈ 𝑔𝑚

2𝜋𝐶𝐺 (2.3)

Chapter 2 - Introduction

7

The limitations present in a-IGZO based amplifiers have their origin in the large parasitic capacitances that exist in oxide TFTs, as seen in the general expression for most amplifiers of the output dominant pole:

𝜔𝑃𝑜𝑢𝑡=

1

2𝜋𝑅𝑒𝑞𝑂𝑢𝑡𝐶𝑒𝑞𝑂𝑢𝑡 (2.4)

where 𝑅𝑒𝑞𝑂𝑢𝑡 is the equivalent output resistance and 𝐶𝑒𝑞𝑂𝑢𝑡 is the equivalent output ca-pacitance at the output node to the ground.

Due to low intrinsic mobility caused by the amorphous nature of the oxide, one way to increase the bandwidth of oxide TFT based amplifiers is by decreasing the overall effective capacitance present at the output node from the TFTs. Several techniques in this topic have been studied. Dual-gate a-IGZO TFTs [24] increases transconductance, compensating the high parasitic capacitance values, at a cost of extra steps in the fabrication process. Self-aligned and stripe patterned source/drain TFTs can be part of high-speed circuits [25], [26] as the parasitic capacitances are reduced through the much smaller overlaps between gate and contacts, how-ever, these techniques require a much higher resolution, different fabrication conditions and steps resulting in higher costs. Even though smaller TFT dimensions and smaller overlaps can also be a path to reduce parasitics [23], this method creates new obstacles such as non-idealities in smaller transistor dimensions, as well as resulting in a higher cost of fabrication due to more expensive facilities.

Our proposal, further expanded in chapter 4, is to decrease the output effective capaci-tance without changing the device’s characteristics through a circuit design technique named negative Miller capacitance compensation. By adding a generated negative capacitance in par-allel to the output node, a negative value of capacitance appears in the expression of 𝐶𝑒𝑞𝑂𝑢𝑡, reducing its overall magnitude and therefore increasing the value of frequency at which the dominant pole is located, resulting in a larger bandwidth of operation. This can be seen through the new expression of the dominant pole:

𝜔𝑃𝑜𝑢𝑡=

1

2𝜋𝑅𝑒𝑞𝑂𝑢𝑡(𝐶𝑒𝑞𝑂𝑢𝑡+ 𝐶𝐼𝑒𝑞) (2.5)

where 𝐶𝐼𝑒𝑞 is the resultant capacitance from the negative Miller compensation as seen later in expression 4.3. This technique has been widely applied in CMOS technology, however, its application in TFT is completely novel and will be studied for the first time in this work.

9

3

Methodology

3.1. Simulation Conditions and Tools

All the designs and simulations were performed mainly using the software from Ca-dence Design Systems. The schematics and layout designs for each structure were created us-ing the Virtuoso System Design Platform, while the simulations for each respective circuit were performed in the Spectre Circuit Simulator.

In this work, as discussed before, nMOS and a-IGZO TFTs were used. The models used for CMOS transistors is the 130nm model. For a-IGZO TFTs, the used model was developed in-house using artificial neural network (ANN) based equivalent circuits (EC) in order to pre-dict the static and dynamic behavior of the device. In this model, an EC is constructed from the device structure, as lumped elements which are individually modeled using ANN. These elements are later connected as part of the EC and implemented in Verilog-A [27].

All the size values for the different transistors were obtained via the interpretation of the transfer function for the different amplifiers, in order to obtain the best possible gain. None of the amplifiers were designed with output impedance loads, so a smaller GBW is expected after fabrication.

As for the different layout designs, the process design kit (PDK) is based on the in-house existing at CEMOP/UNINOVA. Errors such as misalignment of the masks are one of the safety factors that are considered in the PDK. In order to confirm that the layouts are properly de-signed features such as design rule check (DRC) and layout versus schematic (LVS) were used.

The DRC is a set of rules imposed by the limitations in the fabrication process, that need to be followed by the schematic. These rules consider parameters such as maximum and min-imum overlap between Source/Drain and Gate layers, minmin-imum separation between each via in the same layer, minimum width of a via of a single layer or even the minimum width of a hole in M1 in order to connect the Source/Drain to Gate layers.

The LVS compares the designed layout to the equivalent schematic, checking if every component and electrical connections between each component are present. This way it is pos-sible to know if the layout going into fabrication is completely correct and matches the sche-matic perfectly.

11

4

Results and Discussion

This chapter is divided into four major parts. The first part will consist of the explanation of the theory behind the negative Miller compensation circuit design technique and its effect on the amplifier’s frequency response, as well as its application in a real-world a-IGZO based circuit. It will be followed by a very small part dedicated to a proof of concept in CMOS tech-nology. This is due to the availability of much more precise CMOS transistor models. In the third chapter, there will be various subsections dedicated to the method of operation of each amplifier, layout and to the results and analysis of the negative Miller compensation technique applied to each amplifier.

4.1. Negative Capacitance Generation

The negative capacitance generation technique is extensively studied for CMOS technol-ogies and can be employed by several different circuit topoltechnol-ogies. The chosen circuit topology for generating negative capacitance will be discussed a few sub-chapters below.

The Miller theorem establishes that if there is a floating impedance connected to two different voltage sources in series, it can be replaced by two different impedances connected to the ground. This theorem is widely used in circuit analysis, such as analysis of feedback based circuits and amplifiers at higher frequencies [28]. This theorem’s visual representation can be seen in Figure 4.1, where C is the floating impedance. As expected, the feedback capac-itor, when employed between the input and the output nodes of an amplifier, can be repre-sented as a capacitance between the input node and the output node to the ground, CM1 and CM2 respectively. The value of the output capacitor is closer to the value of the capacitor C and both are represented as follows:

𝐶𝑀1 = 𝐶(1 − 𝐴) (4.1)

𝐶𝑀2 = 𝐶 (1 − 1

𝐴) (4.2)

where A is the gain of the amplifier.

4.1.1. Miller theorem

Chapter 4 – Results and Discussion

12

Figure 4.1 - (a) Amplifier schematic with a feedback capacitor and (b) equivalent circuit schematic representing the Miller effect.

Negative Miller capacitance generation, in this case, due to the use of negative capaci-tance, is based on the Miller effect theory, where the impact of the feedback capacitance is shown on the input capacitance. For this effect to take place, the capacitor must be connected around a non-inverting amplifier with a gain A≫1. This leads to the final value of the equivalent input capacitance (𝐶𝐼𝑒𝑞) at the NCG, not taking the amplifier into account, which would be math-ematically expressed by:

𝐶𝐼𝑒𝑞 = 𝐶𝐼𝑛𝑝𝑢𝑡+ (1 − |𝐴|)𝐶 (4.3)

where 𝐶𝐼𝑛𝑝𝑢𝑡 is the input capacitance of the NCG structure and is smaller than C. By the expression 4.3, it is then possible to see that applying this technique in the output of an ampli-fier would result in the removal of the undesired capacitance at that node. The negative value of the equivalent input capacitance when added in parallel with the output capacitance of the amplifier denies the parasitic capacitance at the output node of the amplifier, resulting in an increase of the bandwidth of the amplifiers, as seen in expression 2.5.

Negative capacitance can be achieved through different structure setups. It is known that negative capacitances can be created using a cross-coupled capacitance pair in a positive feedback loop configuration [29]. The most common structures can be observed in Figure 4.2, where the optional inductors in (b) and (c) are used to increase the bandwidth.

In this work, in order to simplify the fabrication of the circuit and to keep the power consumption and chip area low, the used negative capacitance generator (NCG) is seen in

4.1.2. Negative Capacitance Generator

Chapter 4 – Results and Discussion

13

Figure 4.2 (a). The integration of the NCG in the circuit block is achieved by connecting its output to the matching output of the amplifier, as seen in Figure 4.3. This way the NCG is separated from the main amplifier as a way to avoid more parasitic capacitances originated from the cross-coupling capacitor [30]. To match the biasing of the NCG to the amplifier there is a need to adjust the load resistor, however, that also changes the gain of the NCG. Different values of load resistance are used throughout this work.

Figure 4.2 - Schematic of different n egative capacitance generators. (a) Differential NC pair. (b) Drain input cross-coupled NC circuit. (c) Source input cross-coupled NC circuit. Adapted from [31].

Figure 4.3 - Block diagram of the NCG integrat ed with the amplifier .

4.2. CMOS Proof of Concept

Taking into consideration all the work done on this topic some structures were designed and tested along with the use of negative capacitance, only using CMOS technology. This step was performed based on the availability of highly precise metal oxide semiconductor

field-Chapter 4 – Results and Discussion

14

effect transistor (MOSFET) models. The design of the NCG structure in CMOS technology is replicated from Figure 4.2 and can be seen in Figure A.1.

The obtained negative capacitance values for five different cross-coupling capacitors and respective frequency responses can be observed in Figure 4.4. As expected, higher values of capacitance correspond to higher values of negative capacitance, however, it does come at a cost of smaller GBW and chip area. Smaller capacitances also mean a higher GBW and chip area but this comes at a heavy cost of phase margin. For this reason, and for the fact that the impact in the amplifier’s bandwidth is minimal, 50fF cross-coupling capacitors were chosen for the CMOS amplifier.

Figure 4.4 - (a) Simulated negative capacitance values for different pairs of cross-coupling capacitors and (b) re-spective frequency response.

To test the effect of the NCG, a simple single-ended cascode with bootstrapping only using nMOS (derived from the lack of p-type transistors in amorphous oxide technology) was designed based on [3]. For the simple purpose of proof of concept, in this section there will only be a display of results. Detailed circuit analysis of this amplifier operation can be found further in sub-chapter 4.3.3., corresponding to the same circuit but in a-IGZO technology. The schematic of the amplifier designed in CMOS technology can be found in Figure A.2.The gain and phase of the amplifier before and after the application of the NCG can be seen in Figure 4.5.

Chapter 4 – Results and Discussion

15

Through the gain and phase curves, it is possible to see everything that was predicted before. In the phase curve in Figure 4.5 (b) it is possible to see the first pole in the left being pushed to lower frequencies and the second, dominant pole pushed to higher frequencies, resulting in an increase in 𝑓𝑇 as seen in (a). Since the gain of the NCG was 24.9 dB when biased to match the amplifier and the amplifier presented a 32.8 dB gain when combined the ampli-fier’s gain will decrease to 29 dB. Through the application of the NCG, the GBW increased from 67.2 MHz to 106.8 MHz, showing a 59% increase in the maximum frequency of operation, while only increasing power consumption from 0.2 mW to 0.38 mW. The minimum feature size present is 500 nm and a maximum of 1.8 V for power supply was used.

Figure 4.5 - MOSFET amplifier before and after the NCG application (a) Gain. (b) Phase.

In the next chapter, after proving that the technique can be used only using n-type tran-sistors, the same NCG structure was designed using a-IGZO TFTs with the objective of in-creasing the GBW without sacrificing other parameters such as gain or power consumption.

4.3. Bandwidth Enhancement of a-IGZO TFT based

amplifi-ers with NCG

In this sub-chapter, a detailed analysis of the NCG and each different amplifier in a-IGZO technology will be presented as well as the schematic and layout designs, to understand how the negative capacitance would affect its performance. The results from the application of the NCG in the different amplifiers will be presented and analyzed, complemented by a

Chapter 4 – Results and Discussion

16

comparison with current state-of-the-art literature. To avoid repetition, a more in-depth anal-ysis is done for the first amplifier. The circuit schematics of the application of the NCG in Virtuoso software can be seen in Annex A. All the transistors dimensions for the a-IGZO NCG and different amplifiers can be found in Table B.1 in Annex B.

The structure used for negative capacitance generation in a-IGZO technology is the same as seen in Figure 4.2. The first part of the NCG design was to confirm that it did generate a negative capacitance and which capacitance values for the cross-coupling capacitors would be best suited for the use in this project. The gain, phase, and generated negative capacitance value can be observed in Figure 4.6. It is possible to observe through the different curves that this NCG behaves the same way as the NCG in CMOS technology. We can observe how the dominant pole is shifted for higher frequencies for lower capacitance values, leading to a higher GBW, in the phase and gain curves respectively.

Figure 4.6 - Different circuit characteristics for each value of cross-coupling capacitors dimensions in the NCG. (a) Gain. (b) Phase. (c) Generated capacitance.

Chapter 4 – Results and Discussion

17

Keeping in mind the final objective of this work, in order to ensure a good performance and stability in the fabricated a-IGZO based amplifiers, the phase margin of the NCG for dif-ferent values of capacitance in the cross-coupling capacitors was studied, and the results can be observed in Figure 4.6 (b). If a smaller value was to be used, the GBW of the amplifiers would see a bigger increase, but this does come at a cost of much smaller phase margin in the NCG, leading to greater instabilities.

For each different application of the NCG, a different load resistor value was used in order to ensure proper biasing, which also affects the phase margin. In order to keep the phase margin always above 60°, no matter the application, the chosen capacitance values for the cross-coupling capacitors in this part of the project was 100fF and 330fF. Two different values were used and studied in the NCG in order to get the best results from each different amplifier. The gain of the NCG isn’t affected by the dimensions of the cross-coupling capacitors.

Table 4.1 – Parameter comparison for different capacitance values of the cross-coupling capacitors.

20fF 50fF 80fF 100fF 150fF 200fF 330fF

GBW (MHz) 9.50 5.99 4.73 4.23 3.45 2.98 2.32 Phase Margin (°) 28.55 43.89 54.08 59.98 70.03 78.05 92.38

For higher values of cross-coupling capacitor dimensions, the second pole shifts for higher frequencies as seen in Figure 4.6 (b). The effect of higher capacitance values in the phase curves doesn’t seem to have any implications when applied to the amplifiers other than the lower expected impact in the GBW value. These values of higher capacitance do show a higher phase margin and, if high enough, this higher value can have a positive impact in the phase margin of the amplifier itself, as seen further in this chapter. In Figure 4.6 (a), as expected, the flatband gain remains the same for lower frequencies, but the GBW does decrease due to higher impedances introduced by the bigger capacitors. In Figure 4.6 (c), it is possible to see how the generated capacitances are larger than observed in MOS technology in Figure 4.4 (a) due to the larger impedances resultant from the TFT’s low mobility and gate overlap capaci-tances.

The designed layout for the NCG that was later applied to all the a-IGZO based ampli-fiers can be seen in Figure 4.7, with an area of approximately 0.12 mm2_{. Further study into the}

Chapter 4 – Results and Discussion

18

capacitance generated by the NCG must be done, in order to comprehend how the unavoida-ble parasitic capacitances from the overlaps of the different vias impact the general perfor-mance of the circuit and its application.

Figure 4.7 - (a) NCG full layout design with external pads. (b) NCG detail.

The positive feedback differential amplifier is a circuit topology that has been exten-sively studied [2], [8], [32]. The schematic and small-signal equivalent can be seen in Figure 4.8. Vout+ and Vout- are the differential outputs of the amplifier while Vin+ and Vin- are the differential input voltages. The operation of the amplifier is heavily based on 𝑔𝑚 cancellation of the load transistors (M3 and M4). The feedback formed by M6-M10 has a feedback gain (𝐴𝑓). This value must be ensured to be lower than 1, in order to keep the amplifier stable and still maintain a high gain.

Through the small-signal equivalent, where 𝑉𝐺3 is equal to 𝑉𝑜𝑢𝑡 times the feedback gain, it is possible to extract the transfer function:

𝐴𝑉 =

𝑔𝑚1

(1 − 𝐴𝑓)𝑔𝑚3+ 𝑔𝑑𝑠1 + 𝑔𝑑𝑠3 (4.4)

where 𝑔𝑑𝑠 is the channel conductance.

The dominant pole’s expression is seen in equation 4.4. In this case 𝑅𝑒𝑞𝑂𝑢𝑡 and 𝐶𝑒𝑞𝑂𝑢𝑡 are:

𝑅

= 𝑟

|| [

(1−𝐴𝑓)𝑔𝑚3

||𝑟

],

with 𝐴1 being the gain of the transistor M1.

Chapter 4 – Results and Discussion

19

Figure 4.8 - Positive feedback based differential amplifier (a) schematic and (b) small -signal equivalent.

The final layout of this structure with NCG integration can be found in Figure 4.9.

Figure 4.9 - (a) Positive feedback based amplifier with NCG full layout design with external pads. (b) Amplifier plus NCG detail.

4.3.2.1.

Positive feedback differential amplifier frequency response

The obtained curves resulting from the connection of the outputs of the two NCGs to the outputs of the amplifier can be seen in Figure 4.10. From the gain frequency response it is possible to observe how the pole is shifted forwards, increasing GBW. The value of the result-ing gain evens out between the gain of the amplifier and the gain of the NCG, decreasresult-ing or

Chapter 4 – Results and Discussion

20

increasing. In this case, the gain decreases due to a smaller NCG gain value. In most cases throughout this work, this happens due to the need for proper biasing and a certain value of the load resistor in the NCG, locking the obtainable gain to that value.

Higher gain can be obtained using a larger power supply, although that does come at a cost of much larger power consumption. Without the NCG the amplifier was showing a 35.8 dB flatband gain with a GBW of 481 kHz. The value of the gain decreases to 27.6 dB since the NCG presents a 25 dB gain. The amplifier with the NCGs shows a 1.50MHz GBW for the 100fF NCG and 1.22 MHz for the 330fF NCG. This was achieved with a power consumption increase from 0.5 mW to 0.8 mW and a chip area increase from 0.84 mm2 _{to 1.39 mm}2_{. The amplifier} used a 10 V power supply while the NCG used a 15 V power supply. A minimum feature size of 10 µm was used. The value of the load resistor in the NCG for correct biasing is 1.0134 MΩ. It is possible to see in Table 4.2 all the summarized simulation results.

Figure 4.10 - Positive feedback amplifier with and without NCG application (a) gain plots, and (b) phase plots.

These results are subject to change in fabricated circuits due to an introduction of para-sitic capacitances resulting from the interception of the different metal vias in different layers. All the observed results were expected, the increase in GBW coupled with the decrease of gain due to the smaller NCG gain. It is very important to note one important effect that occurs when using different values for cross-coupling capacitance. When bigger capacitors in the NCG are used, the equivalent output capacitance will be higher (as seen in expression 4.3).

Chapter 4 – Results and Discussion

21

Table 4.2 - Summary of the results obtained from the simulated application of the NCG to the positive feedback based amplifier.

Gain (dB) Phase Margin GBW Pwr con-sumption Chip area Min. fea-ture size Before NCG 35.7 102° 481 kHz 0.5 mW 0.84 mm2 _{10 µm} After NCG 100fF 27.6 94.2° 1.50 MHz 0.8 mW 1.39 mm2 _{10 µm} 330fF 102.3° 1.22 MHz

If this value is much higher than the output capacitance shown by the amplifier when integrating the NCG, instead of having a smaller positive capacitance, the output node will experience a very high negative capacitance. This means that the capacitance value from the cross-coupling capacitors must be carefully tailored to each amplifier in order to obtain the smallest output capacitance while maintaining a proper phase margin as explained before. In this case, since the amplifier has a high enough phase margin, we can opt to use the NCG with the smaller capacitance, achieving a much higher GBW.

The cascode with bootstrapping structure was adapted from [3]. A single-ended and a differential design were analyzed and simulated, and their schematic and respective small-signal equivalent can be found in Figure 4.11. A differential version was developed to observe the differences from single-ended to differential when applying the NCG, as well as to have to ability to test a more robust structure with increased noise immunity. Regarding the single-ended variant, this structure operates with the transistors M1, M2, and M3 in saturation, where the transistors M4 and M5 are in cut-off due to being in series with a capacitor and high-im-pedance branches from M2 and M3. The output signal is fed back to M2 and M3 through the feedback circuit created by the capacitors and the bias transistors M4 and M5 [3].

The feedback path can be described through Figure 4.11 (d), where the biasing transis-tors (M4 or M5) can be described by a parallel combination of the off resistance (𝑅𝑜𝑓𝑓) with the off capacitance (𝐶𝑜𝑓𝑓) in series with the capacitor C. The feedback gain (𝐴𝑓) is kept at a value near 1 and is expressed by:

𝐴𝑓 = 𝑣4 𝑣𝑜 , 𝑣4 = 𝑣𝑜 (𝑅𝑜𝑓𝑓||_𝑠𝐶1 𝑜𝑓𝑓) 1 𝑠𝐶 + (𝑅𝑜𝑓𝑓||_𝑠𝐶1 𝑜𝑓𝑓) = 𝑣𝑜 1 1 +𝐶𝑜𝑓𝑓_𝐶 (4.6)

4.3.3. Single-ended and Differential Cascode with Bootstrapping

Chapter 4 – Results and Discussion

22

Through the small-signal equivalent circuit the gain of the amplifier is: 𝑖𝑜≈ 𝑔𝑑𝑠2 𝑔𝑚 𝑣𝑜, 𝑅𝐿 = 𝑣𝑜 𝑖𝑜 ≈ 𝑔𝑚𝑟𝑑𝑠2 , 𝑣𝑜 𝑣𝑖𝑛 = −𝑔𝑚(𝑟𝑑𝑠||𝑔𝑚𝑟𝑑𝑠2) (4.7) The equivalent output resistance (𝑅𝑒𝑞𝑂𝑢𝑡) and equivalent output capacitance (𝐶𝑒𝑞𝑂𝑢𝑡) can be expressed by:

𝑅

= 𝑟

||𝑅

,

where 𝐴1 is the gain of the transistor M1.

Figure 4.11 - (a) Single-ended and (b) differential cascode with bootstrapping schematic. (c) Sin-gle-ended cascode with bootstrapping small-signal equivalent and (d) feedback path schematic.

The final layout of both structures with NCG integration can be found in Figure 4.12.

Figure 4.12 - (a) Single-ended cascode with bootstrapping with NCG full layout design with ex-ternal pads. (b) Amplifier plus NCG detail. (c) Differential cascode with bootstrapping with NCG full layout design with external pads. (b) Amplifier plus NCG detail.

Chapter 4 – Results and Discussion

23

4.3.3.1.

Single-ended and differential cascode with bootstrapping

fre-quency response

The obtained curves resulting from the connection of the outputs of the two NCGs to the outputs of the two amplifiers can be seen in Figure 4.13.

The results obtained were as expected. Regarding the single-ended variant of the struc-ture, the gain increases after the integration since the gain of the NCG is 29.6 dB. The same happens for the differential variant, with an NCG gain of 31 dB. In the single-ended structure, the output capacitance is low enough that the NCG with 330fF will generate a much higher output negative capacitance. This way, the output node will be experiencing a higher absolute capacitance than before the integration of the NCG, decreasing the GBW. For this, it is advisa-ble to use the 100fF NCG for the single-ended structure. The integration of the NCG in this structure also shifts the first pole to the left, this way the low-frequency value of GBW ceases to exist, resulting in better control of the operation of the amplifier at lower frequencies.

In the differential structure, since the output capacitance is larger than the 330fF NCG’s negative output capacitance, it is possible to observe positive results regarding 𝑓𝑇. This way it is possible to use the 100fF NCG in both structures. A power supply of 15 V was used for the amplifiers, while the NCG required 17 V. The value of the load resistor in the NCG for correct biasing is 1.2 MΩ for the single-ended structure and 1 MΩ for the differential structure. The achieved positive results can be observed in Table 4.3.

Table 4.3 - Summary of the results obtained from the simulated application of the NCG to the Single-ended and differential cascode with bootstrapping.

Gain (dB) Phase Mar-gin GBW Pwr con-sumption Chip area Min. feature size Single ended Before NCG 26.0 68° Low: 60 Hz 0.4 mW 0.93 mm2 20 µm High: 3.35 MHz After NCG 100fF 27.6 65° 3.67 MHz 0.74 mW 1.29 mm2 20 µm - Amp 330fF 79° 2.29 MHz 10 µm - NCG Differ-ential Before NCG 22.5 66.6° Low: 81 Hz 0.87 mW 2.69 mm2 20 µm High: 2.26 MHz After NCG 100fF 26.0 63.4° 3.05 MHz 1.21 mW 3.18 mm2 20 µm - Amp 330fF 79.8° 2.86 MHz 10 µm - NCG

Chapter 4 – Results and Discussion

24

Figure 4.13 - Single-ended cascode with bootstrapping with and without NCG application (a) gain, and (b) phase frequency response plots. Differential cascode with bootstrapping with and without NCG application (c) gain, and (d) phase frequency response plots.

This amplifier structure using bootstrap gain enhancement and common-mode feedback (CMFB) has been adapted from a dual-gated pentacene-based OTFT amplifier from [9]. In this block, seen in Figure 4.14, several techniques were used such as bootstrapping of the transim-pendance in order to have a higher gain than a diode-connected load, CMFB to increase the tolerance to 𝑉𝑇 variations and a differential to single-ended converter stage.

The transistors M1 to M4, M7, and M10 to M13 operate in the saturation region, while M8 and M9 operate in linear mode. The CMFB loop is formed through transistors M8 and M9. The working method of this technique implies that if there is a positive variation in Vout, the current passing through M8 and M9 will increase, which leads to an increase in 𝐼𝐷𝑆7. Since 𝐼𝐷𝑆7

4.3.4. Amplifier Using Bootstrap Gain Enhancement and Common

Mode Feedback

Chapter 4 – Results and Discussion

25

is the sum of 𝐼𝐷𝑆1 and 𝐼𝐷𝑆2 this will lead to an increase in the voltage drop in the load transistors M3 and M4, which will lower Vout as seen in expression, denying the positive variation seen in the beginning. The opposite happens for negative variations of Vout.

𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷− 𝑉𝐺𝑆𝐿𝑜𝑎𝑑 (4.9)

The feedback (𝐴𝑓) given from the bootstrapping structure is explained through Figure 4.14 (b) and is given by:

𝑉𝑥 = 𝐶 ∗ 𝑉𝑜𝑢𝑡 𝐶 + 𝐶𝐷𝑖𝑜𝑑𝑒𝑀5 ⇔ 𝑉𝑥 𝑉𝑜𝑢𝑡 = 𝐶 𝐶 + 𝐶𝐷𝑖𝑜𝑑𝑒𝑀5 = 𝐴𝑓 (4.10)

The amplifying done by this block is also based on 𝑔𝑚 cancellation of the load transistors and it can be obtained mathematically through Figure 4.14 (c), where:

𝑉𝐺3= 𝑉𝑥− 𝑉𝑜𝑢𝑡 = (𝐴𝑓− 1)𝑉𝑜𝑢𝑡 (4.11) which will result in:

𝑔𝑚1𝑉𝑖𝑛+ 𝑉𝑜𝑢𝑡(𝑔𝑑𝑠1+ 𝑔𝑑𝑠3) + (1 − 𝐴𝑓)𝑉𝑜𝑢𝑡𝑔𝑚3 = 0 ⇔ ⇔𝑉𝑜𝑢𝑡 𝑉𝑖𝑛 = −𝑔𝑚1 (1 − 𝐴𝑓)𝑔𝑚3+ 𝑔𝑑𝑠1+ 𝑔𝑑𝑠3 (4.12)

If 𝐴𝑓 ≈ 1 then 𝑔𝑚1≫ 𝑔𝑑𝑠1+ 𝑔𝑑𝑠3 which will result in high gain. The equivalent output resistance (𝑅𝑒𝑞𝑂𝑢𝑡) and equivalent output capacitance (𝐶𝑒𝑞𝑂𝑢𝑡) can be expressed by:

𝑅

= 𝑟

||𝑟

,

where 𝐴1 is the gain of the transistor M1.

The method of operation of the differential to single-ended stage, comprised by the tran-sistors M10 to M13 is given by:

𝑔𝑚12𝑟𝑑𝑠10 1 + 𝑔𝑚12𝑟𝑑𝑠10

∗ 𝑉𝑜𝑢𝑡+≈ 1 ∗ 𝑉𝑜𝑢𝑡+, 𝑉𝑜𝑢𝑡 = 𝑉𝑜𝑢𝑡−− 𝑉𝑜𝑢𝑡+ (4.14) due to 𝑔𝑚12𝑟𝑑𝑠10 ≫ 1.

Chapter 4 – Results and Discussion

26

Figure 4.14 - Amplifier using bootstrap gain enhancement and CMFB (a) schematic, (b) feedback path, and (c) small-signal equivalent circuit for the differential output.

The final layout of this structure with NCG integration can be found in Figure 4.15.

Figure 4.15 - (a) Bootstrap gain enhancement with CMFB based amplifier with NCG full layout design with external pads. (b) Amplifier plus NCG detail.

4.3.4.1.

Amplifier using bootstrap gain enhancement and common mode

feedback frequency response

The obtained curves resulting from the connection of the outputs of the two NCGs to the outputs of the amplifier can be seen in Figure 4.16.

Chapter 4 – Results and Discussion

27

Figure 4.16 - Amplifier using bootstrap gain enhancement and CMFB with and without NCG application (a) gain, and (b) phase frequency response plots.

The gain of the amplifier after the integration increases due to higher NCG gain. As ex-pected, the GBW value increases more for the 100fF than for the 330fF cross-coupling capaci-tors. Since the phase margin of this circuit is 60°, using the 100fF NCG is not advisable since the phase margin after the integration lowers to 58°, creating potential instabilities. However, after fabrication and the introduction of parasitic capacitances, using the 100fF NCG may re-veal other results. The phase also behaves as expected. The first pole at the 1kHz mark is shifted to the left, while the second pole near the 10 kHz mark is shifted to the right, increasing the bandwidth of the circuit. Upon application of the NCG, the GBW of the amplifier is in-creased from 619 kHz to 1.17 MHz for the 330fF NCG and to 1.34 MHz for the 100fF NCG, while increasing power consumption from 0.23 mW to 0.53 and chip area from 2.1 mm2 _{to 2.8} mm2_{. A 10 V power supply was used for the amplifier, while the NCG required a 15 V power} supply.

In this amplifier, the differential outputs of the NCG are connected to the differential outputs of the first stage. If the connection was made to the single-ended stage since it acts as a buffer, the NCG would have no effect and no positive results would be visible, not to be confused with a single-ended application, which has already provided good results as seen in

Chapter 4 – Results and Discussion

28

sub-chapter 4.4.2. before. This way the bootstrapping capacitors and differential stage parasitic capacitances are canceled by the negative capacitance generated, increasing the bandwidth.

Table 4.4 - Summary of the results obtained from the simulated application of the NCG to the amplifier with bootstrapping gain enhancement and CMFB .

Gain (dB) Phase Margin GBW Pwr con-sumption Chip area Min. fea-ture size Before NCG _{23.7 60.0° 619 kHz 0.23 mW 2.1 mm}2 _{10 µm} After NCG 100fF 29.3 58.3° 1.34 MHz 0.53 mW 2.8 mm2 _{10 µm} 330fF 66.5° 1.17 MHz

The pseudo-CMOS based amplifier has been adapted from [4]. This structure, seen in Figure 4.17 (a) uses a pseudo-CMOS inverter as a load for the transistors M1 and M2. Its method of operation is essentially the same as the positive feedback-based amplifier and the bootstrap gain enhancement with CMFB amplifier, as it is also based in 𝑔𝑚 cancellation of M4. The higher load impedance provided by the pseudo-CMOS configuration will provide a higher open-loop gain than a simple diode-connected load inverter. After several simulations, it was found that the best results in denying the output capacitance would be obtained if the outputs of the NCG were connected to the output of the second stage.

Assuming 𝑉𝑥 is a multiplier of the feedback gain obtained from the circuit formed by M1, M6 and M3 then the expression for the gain of the first stage is:

𝑉𝑦

𝑉𝑖𝑛= 𝐴𝑉=

−𝑔𝑚2

(1 − 𝐴𝑓)𝑔𝑚4+ 𝑔𝑑𝑠2+ 𝑔𝑑𝑠4 (4.15) When ensuring that 𝐴𝑓 ≈ 1, and if 𝑔𝑚 ≫ 𝑔𝑑𝑠 then the gain will be mainly dependent on the transconductance of M2.

The equivalent output resistance (𝑅𝑒𝑞𝑂𝑢𝑡) and equivalent output capacitance (𝐶𝑒𝑞𝑂𝑢𝑡) can be expressed by:

𝑅

= 𝑟

||𝑟

,

where 𝐴13 is the gain of M13.

Chapter 4 – Results and Discussion

29

Figure 4.17 - Pseudo-CMOS based amplifier (a) schematic and (b) small-signal equivalent circuit for the first stage output.

The final layout of the structure can be found in Figure 4.18.

Figure 4.18 - (a) Pseudo-CMOS based amplifier with NCG full layout design with external pads. (b) Amplifier plus NCG detail.

4.3.5.1.

Pseudo CMOS frequency response

The obtained curves resulting from the connection of the outputs of the two NCGs to the outputs of the amplifier can be seen in Figure 4.19.

Chapter 4 – Results and Discussion

30

The gain of the amplifier increases as expected upon the integration of the NCG, since it displayed a greater gain. Regarding 𝑓𝑇, the increase happens as expected, as the 100fF NCG provides a greater increase in 𝑓𝑇 in comparison to the 330fF NCG. The phase curve in this amplifier sees a change when comparing the different sizes of cross-coupling capacitors as the 330fF NCG. The pole is shifted more to the right because there is the use of a smaller 100fF cross-coupling capacitance, as mentioned before.

This pole, however, is accompanied by a zero to its right that when shifted to the right by the 100fF NCG is affected by two poles, which doesn’t happen in application of the 330fF NCG, since the zero that accompanies the pole moves far away enough from its base position, but not far enough as the 100fF NCG to go unnoticed. This causes what can be seen around the 1 MHz mark in the phase frequency response plot of the application of the 330fF NCG.

Figure 4.19 - Pseudo-CMOS based amplifier with and without NCG application (a) gain, and (b) phase frequency response plots.

Table 4.5 - Summary of the results obtained from the simulated application of the NCG to the Pseudo-CMOS based amplifier.

Gain (dB) Phase Margin GBW Pwr con-sumption Chip area Min. fea-ture size Before NCG 18.6 118° 223 kHz 1.6 mW 1.97 mm2 _{10 µm} After NCG 100fF 26.3 95° 892 kHz 1.8 mW 2.60 mm2 _{10 µm} 330fF 77° 775 kHz

31

5

Conclusions and Future Perspectives

The work done for this dissertation had the main focus on increasing the frequency of operation of a-IGZO based amplifier structures, without changing any of the device's intrinsic properties. This was achieved using negative Miller capacitance compensation.

First, there was the need to fully understand the Miller’s theorem, and how it was pos-sible to generate a negative capacitance. This was first tested in standard 130 nm CMOS mod-els that have been broadly studied and therefore are much more accurate. This provided a basis in how the application of a negative capacitance worked in several simple amplifier blocks, and what it was to be expected when a-IGZO TFTs were used. To generate a negative capacitance there is a need for a feedback capacitor connected around a non-inverting ampli-fier with gain A≫1, for this a simple differential ampliampli-fier with cross-coupling capacitances was used. The cross-coupling capacitors dictate how much negative capacitance is generated, as well as the load resistor since the equivalent output capacitance varies is multiplied by the gain of the structure.

In a CMOS based single-ended cascode with bootstrapping, an increase of 59% in the value of GBW, from 67.2 MHz to 106.8 MHz was obtained with a minimal impact on power consumption and chip area. The final gain obtained is dependent on the gain of the NCG, although this gain can be controlled through higher or lesser power supplies.

In a-IGZO TFT technology, five different amplifiers were tested with and without the application of the NCG, the obtained results before and after the application of the NCG com-pared with state-of-the-art literature can be seen in Table 5.1. It is possible to see how the unity current gain frequency increases for each different amplifier when the output capacitance is denied by the applied negative capacitance. Some amplifiers, such as the positive feedback amplifier report 200% increases in the GBW value, while other amplifiers that show a higher base GBW don’t report such a high increase due to the effectiveness of the NCG at higher frequencies. The gain of the NCG is fixed due to the need to have a matching bias with the amplifier, however, this can be changed by increasing the power supply of the NCG.

It is expected that these structures when fabricated will report a smaller GBW when compared to the simulations, due to all the parasitic components that are related to the

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32

cation of circuits, such as parasitic capacitances resulting from the overlap of different metal-lization layers. This also impacts the performance of the NCG as proved before, as higher parasitic capacitances will decrease its impact on the amplifier performance.

Table 5.1 – State of the art, and simulation values before and after NCG comparison for the different ampli-fiers. State of the art examples include output loads and are fabricated circuits . (a) Positive feedback differ-ential amplifier. (b) Single -ended cascode w/ bootstrapping. (c) Differdiffer-ential cascode w/ bootstrapping. (d) Amplifier using bootstrap gain enhancement and CMFB. (e) Pseudo-CMOS based amplifier.

(a) (b) (c) (d) (e) w/o NCG w/ NCG [2] w/o NCG w/ NCG [3] w/o NCG w/ NCG w/o NCG w/ NCG w/o NCG w/ NCG [4] GBW (MHz) 0.48 1.50 0.20 3.35 3.67 0.02 2.26 3.05 0.62 1.17 0.22 0.89 0.03 Gain (dB) 35.7 26.7 10.0 26.0 27.6 22.0 22.5 26.0 23.7 29.3 18.6 26.3 22.5 Phase Mar-gin (°) 102 94 X 68 65 X 67 63 60 67 118 95 X

State of the art results tends to have smaller GBW due to being fabricated real-world circuits and including large output impedance loads. Taking these results into account, using this technique can result in very high increases in GBW while not tampering with the inner structure of the a-IGZO TFT. This means that employing this technique can be extremely fa-vorable in the future of amorphous oxide TFT based structures, as an intrinsic disadvantage of it can be denied by the simple use of a negative capacitance generator. Considering that this is a flexible technology with enormous potential, this increase in GBW can be useful for a plethora of applications such as low-cost RFID and biomedical devices and apparel, flexible displays or any type of circuit employing AOS TFTs that relies on its frequency of operation.

Further tests need to be conducted in order to prove its efficiency in real-world applica-tions, as well as if this technique can be applied in the various nodes of the amplifiers instead of just the output. New techniques can be used for the negative capacitance generation such as the use of different NCG as seen in Figure 4.2, in order, as these have been studied for CMOS technology, and its benefits can be of good use in TFT applications.