Comparing the Schedulers and Power Saving Strategies with SPARTS
www.hurray.isep.ipp.pt
Technical Report
HURRAY-TR-111104 Version:
Date: 11/23/2011
Muhammad Ali Awan Borislav Nikolic
Stefan M. Petters
Technical Report HURRAY-TR-111104 Comparing the Schedulers and Power Saving Strategies with SPARTS
© IPP Hurray! Research Group
www.hurray.isep.ipp.pt 1
Comparing the Schedulers and Power Saving Strategies with SPARTS
Muhammad Ali Awan, Borislav Nikolic, Stefan M. Petters
IPP-HURRAY!
Polytechnic Institute of Porto (ISEP-IPP) Rua Dr. António Bernardino de Almeida, 431 4200-072 Porto
Portugal
Tel.: +351.22.8340509, Fax: +351.22.8340509
E-mail: [email protected], [email protected], [email protected] http://www.hurray.isep.ipp.pt
Abstract
We have developed SPARTS, a simulator of a generic embedded real-time device. It is designed to be extensible to
accommodate different task properties, scheduling algorithms and/or hardware models for the wide variety of
applications. SPARTS was developed to help the community investigate the behaviour of the real-time embedded
systems and to quantify the associated constraints/overheads.
Comparing the Schedulers and Power Saving Strategies with SPARTS
Muhammad Ali Awan Borislav Nikoli´c Stefan M. Petters Cister Research Unit, ISEP-IPP, Porto, Portugal
{ maan,borni,smp } @isep.ipp.pt
Abstract—We have developed SPARTS, a simulator of a generic embedded real-time device. It is designed to be extensible to accommodate different task properties, scheduling algorithms and/or hardware models for the wide variety of applications.
SPARTS was developed to help the community investigate the behaviour of the real-time embedded systems and to quantify the associated constraints/overheads.
I. I NTRODUCTION
Nowadays, there is an ever increasing demand for embedded systems. These devices interact with their environment and perform computations which may have to satisfy several constraints. Embedded systems with timing requirements are called Real-Time embedded Systems. In addition to timing constraints and function correctness, these devices often have limited or intermittent power supply. Technology enhance- ments and cost reduction mandated integration of the multiple functionalities into one device. Along with this, the design itself grew more complex. For instance, in modern cars safety critical applications are integrated with comfort functionality.
In order to provide efficient execution of such systems, spe- cific scheduling algorithms are needed. They are very diverse in terms of requirements and produced results. Given those, there is the question of evaluating the scheduling approaches and identifying the trade-offs involved in employing one strategy over another. One approach in tackling this problem is to build a system model. It gives the possibility to hide unnecessary and negligible details, so only aspects of interest need to be implemented and tested. This method is very fast and can provide the comparison between different scheduling approaches or associated power management schemes. We have developed SPARTS (Simulator for Power-Aware Real- Time Systems) that can model aforementioned different sys- tem behaviour aspects.
Numerous available tools target different areas of stated problems. However, several limitations are recognised as the greatest drawbacks of their use. Some simulators [1]–[3] utilise an unnecessarily detailed approach in simulation which has a huge impact on the performance. Others lack in expressiveness while defining new functionalities and/or adapting existing ones for personal needs, e.g. [4]. Furthermore, commercial tools such as SymTA/S [5] or RapiTime [6] are for obvious reasons closed systems not accessible to casual users.
This work was supported by the RePoMuC project, ref. FCOMP-01- 0124-FEDER-015050, funded by FEDER funds through COMPETE (POFC - Operational Programme ’Thematic Factors of Competitiveness) and by National Funds (PT) through FCT-Portuguese Foundation for Science and Technology, and the RECOMP project, funded through the FCT under grant ref. ARTEMIS/0202/2009, as well as by the ARTEMIS Joint Undertaking, under grant agreement Nr. 10202.
II. SPARTS O VERVIEW
SPARTS simulates a generic real-time device and is imple- mented as a discrete-event execution environment. It provides extensive flexibility in task-set generation for different scenar- ios and purposes. The task-sets can be used for schedulability tests as well as for simulation purposes. The modular structure of SPARTS allows easy development and integration of new scheduling algorithms for both, single and multi-core systems.
The results of the simulations give indications about the perfor- mance and various overheads incurred by different scheduling approaches (pre-emptions, energy consumptions, migrations for multi-cores, etc). SPARTS can be extended and adapted to fit the needs of the user in the area of interest.
SPARTS performs the simulation in event-driven manner.
Rather than doing a cycle-step execution, SPARTS works by looking backward into the interval between two consecutive job releases and simulates the execution without unnecessary cycle-level granularity. This feature is implemented with a Timers mechanism. Timers represent possible interrupts of the execution process, such as, new arrival of a job, expiration of a deadline, completion of an execution etc. The simulation jumps to the point in time when the first timer would fire. At this moment possible actions corresponding to the interrupts and the intervening time like power attribution are serviced.
The architecture of SPARTS is depicted on Figure 1. For easier use and extensibility, we separated the responsibilities by encapsulating limited functionalities within different mod- ules and providing the interfaces for them to communicate.
The input parameters are delivered to the Task-Set Generator (TSG), which creates the tasks for a particular simulation run.
Generated task-set is then passed to Job Generator (JG) and job instances for the desired simulation time are produced.
The Job Sequencer (JS) orders the jobs by their release times and prepares the stream for the execution. Finally, the Execution Environment (EE) executes the stream of jobs and collects required parameters for the reporting tool to do further analyses.
Several performance bottlenecks recognised in related work
are addressed in SPARTS. Firstly, the simulation process is
driven by discrete events and executes by looking into the
past. With this approach we save the computation and yet
provide ”correct” execution modelling. This allows to perform
the simulations of large task-sets for long periods of time
with high temporal efficiency. Additionally, this gives the
possibility to manually configure the granularity of the system
and adapt it to the particular needs of the user. Secondly,
SPARTS breaks the simulation time into smaller pieces, which
Hardware Model
Input Parameters Task−Set Generator
Task Task
Task Task
Job Job Job Job
Job
Job Job Job
Job
Job Sequencer Event Event Event
Job Generator
Scheduler Execution Environment
Fig. 1. The Simulator Architecture
10−2 10−1 100 101 102 103 104 105
0.5 1 1.5 2 2.5 3 3.5
Horizon Size (Logarithmic Scale)
Actual Simulation Time (in Seconds)
LC−EDF
Fig. 2. Horizon size trade-off
1000 200 300 400 500 600 700 800 900 1000
1 2 3 4 5 6 7 8
Actual Simulation Time (in Seconds)
Simulated Time (in Seconds)
EDF (No Horizon) LLF (No Horizon) ERTH (No Horizon) EDF (With Horizon) LLF (With Horizon) ERTH (With Horizon)