21 aula

Interface Hardware-Software

Aula 2-1

Arquitetura Processadores Intel x86

Prof. Dr. Stefan Michael Blawid

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Tópicos

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Tópicos

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ISA Intel x86 History

Evolution ensuring backward compatibility: 8080 (1974): 8-bit microprocessor

8086 (1978): 8080 extension to 16 bits Dedicated 16-bit registers

8087 (1980): Floating point coprocessor Add floating point statements and stack

80286 (1982): 24-bit addresses and Memory Management Unit (MMU) Memory protection model

80386 (1985): 32-bit extension (called IA-32) Addressing Modes and Additional Operations 32-bit registers and addressing

I486 (1989): Pipeline utilization, on-chip caches Compatible Competitors: AMD, Cyrix, …

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ISA Intel x86 History (cont.)

Always evolving …

Pentium (1993): Superscalar

Later versions included Multi-Media eXtension (MMX) instructions

The Famous FDIV Instruction Bug Pentium III (1999)

Added Streaming SIMD Extensions (SSE) instructions and associated registers

70 instructions added, 4 single precision floating point operations could be done in parallel

Pentium 4 (2001)

Added 144 instructions (SSE2)

It allowed double precision floating point operations to be performed in parallel

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ISA Intel x86 History (cont.)

And even more so …

AMD64 (2003): Extended the architecture to 64 bits Increased registers to 64 bits

Increased number of registers

EM64T – Extended Memory 64 Technology (2004) AMD64 adopted by Intel (with refinements)

Added 13 SSE3 instructions Intel Core (2006)

Added 54 SSE4 instructions AMD64 (2007)

Added 170 SSE5 instructions

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Processor Execution Cycle

1) Fetch an instruction from the memory

2) Decode the instruction (i.e., identify the instruction)

3) Execute the instruction (i.e., perform the action specified by the instruction)

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Storing Multibyte Data

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Tópicos

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Intel 32-bit Architecture (IA-32)

Ten 32-bit and six 16-bit registers

Grouped into general, control, and segment registers

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Data registers

There are four 32-bit data registers that can be used for arithmetic, logical, and other operations. They can be used as follows:

Four 32-bit registers (EAX, EBX, ECX, EDX); or Four 16-bit registers (AX, BX, CX, DX); or

Eight 8-bit registers (AH, AL, BH, BL, CH, CL, DH, DL) Some specific uses, e.g.,

EAX (or AX, or AL) must contain one operand for multiplication ECX (or CX) must contain the loop count for iterative instructions

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Example

MUL CL

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Index and Pointer Registers

Index Registers should be used in statements that manipulate strings: These types of statements usually implicitly increment / decrement these registers.

The pointer registers are mainly used to maintain the stack ESP holds the address of the top of the stack and is

incremented / decremented by POP / PUSH instructions

EBP is the base pointer for memory access

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Segment Registers

Support the segmented memory organization and point to where these segments are located in the memory

CS points to the instruction part DS points to the data part

SS points to the stack segment

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Control Register: Instruction pointer

IP points to the next instruction to be executed within the current code segment

Cannot be explicitly changed by programmer Implicitly modified by certain instructions

32-bit (EIP) or 16-bit (IP) addresses

The FLAGS register (next slide) stores the CPU state (status flags) and also controls it (control and system flags)

Implicitly modified by the instructions

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Control register: FLAGS

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Tópicos

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Where Are the Operands?

Instructions use the format: [label] mnemonic [operands] [;comment] Most assembly language instructions require operands

An operand required by an instruction may be in any one of the following locations:

in a register internal to the processor; in the instruction itself;

in main memory (usually in the data segment); at an I/O port

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Addressing Modes

In arithmetic / logical instructions first operand is origin and destiny

Register-addressing mode is the most efficient way of specifying operands because they are within the processor and, therefore, no memory access is required

Immediate Addressing mode: Operand is in the code segment Memory Addressing: Operand is in the data segment

First source/destiny operator Second source operator

Register Register

Register Immediate

Register Memory

Memory Register

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Register-Addressing Mode

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Immediate Addressing Mode

The immediate source operand can be an 8,16 or 32-bit number Cannot be used for segment registers!

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Memory Addressing Modes

To locate a data item in the data segment, we need two components: the segment start address and an offset value within the segment. The offset value is often called the effective address. Various memory-addressing modes differ in the way the offset value of the data is specified. For 16-bit addresses:

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Direct Addressing Mode

The offset value is specified directly as part of the instruction Must be specified using square brackets ([])

Default segment is DS, otherwise must be specified, e.g.:

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Indirect Addressing Mode

The effective address of the data is in one of the general registers Must be specified using square brackets ([])

Only BX, BP, SI, DI can be used.

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Based Addressing

The effective address is computed: A register acts as the base register and a displacement value is added

Must be specified using square brackets ([]) Only BX, BP can be used as base register Value must be a signed 8- or 16-bit number Default segment is DS for BX and SS for BP

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Indexed Addressing

Similar to base addressing, however only SI and DI (index) registers can be used as base registers

Must be specified using square brackets ([]) Default segment is DS

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Based-Indexed Addressing

Memory operand address is the result of the sum of segment, base register, index register, and offset value

Specification of a displacement value not required Must be specified using square brackets ([])

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Memory addressing for 32-bit addresses

A scale factor may be applied for indexed and based-indexed addressing (support for two-dimensional arrays)

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I/O port addressing

Specific to I/O, the operand is given by the (immediate) address of a port or is given by the address contained by the DX register

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Tópicos

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IA-32 instruction format

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Instruction prefixes

Prefix Bytes Modify Operation: Lock and repeat; Segment override; Branch hints; Operand-size override; Address-size override

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Opcode

The primary opcode of the instruction. Some instructions already

codify additional informations in their own opcode. Example: direction of the operation (increment/decrement)

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Postfix bytes

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If the instruction specifies an immediate operand, the operand always follows any displacement bytes. An immediate operand can be 1, 2 or 4 bytes.

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Some Conclusions about x86

Complex instructions make implementation difficult

HW translates instructions to simpler micro operations: Simple instructions are translated one-to-one; Complex instructions, however, one-to-many

Microengine similar to RISC

Market makes processor economically viable Performance comparable to RISC

Compilers avoid complex instructions Compatibility ties processor design

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Tópicos

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X86 Processor Modes of Operation

Commitment to legacy code compatibility has led Intel to adopt modes of operation on its processors

Depending on the version of the processor for which the code was written, it will run in a particular mode of operation on a newer processor.

The mode of operation determines which architecture instructions and features are accessible

Example: The IA-32 architecture

Real mode: Uses 16-bit addresses, provided to run programs written for the 8086 processor.

Protected mode: Uses 32-bit addresses, native mode of the IA-32 architecture

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Protected Mode Memory Architecture

Index: Selects one of 8192 descriptors

TI: Selects one of two descriptor tables

RPL: Identifies the privilege level for protected access 32-bit offset:

Segments can span the entire memory address space (4GB) of a Pentium

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Real Mode Memory Architecture

The memory address space is 1MB ➡ 20-bit physical memory address

Four least significant zero bits are not stored

16-bit offset: Segments span 64kB

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Real-mode segments overlap

For each logical memory address, there is a unique physical memory address

One logical address can refer to the same physical memory address