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(1)

Corrente Contínua

Ultra-Alta Tensão

em

Panorama Atual

(2)

Madeira HVDC Transmission System

Bipole 2 Project and Studies: Relevant Aspects

(3)

Madeira HVDC Transmission System:

Madeira HVDC Transmission System:

S. Antônio Jirau Filtro AC Filtro AC 4 x9 5 4 M C M -T C -1 0 5 km 4x2312MCM – 2375km 4x2312MCM – 2375km +600kV CC -600kV CC Pólo 1 1575MW Pólo 2 1575MW 1575 MVA 44x75MW 3x1250MVA 44x71,6MW

SE

Vilhena

P. Velho Ariq.J. ParanáP.Bueno Coxipo

Ribeirãozinho Itumbiara Rio Verde 2x954MCM 12 km Back-to-back MT Samuel Trindade Araraquara Araraquara (Furnas) (CTEEP) 1575 MVA Filtro AC Filtro AC 4x2312MCM – 2375km 4x2312MCM – 2375km +600kV CC -600kV CC Pólo 1 1575MW Pólo 2 1575MW 1575 MVA 1575 MVA -25/50 Mvar CE -25/50 Mvar CE Rio BrancoAbunaUnivers.

(4)
(5)

Objectives of the System Engineering Studies:

Objectives of the System Engineering Studies:

• Dimension and specify all the converter station

equipment

• Verify the specified performance requirements of the

HVDC transmission system

• Perform AC and DC protection coordination of the

converter station

(6)

Main System Studies for BP2:

Main System Studies for BP2:

Basic Engineering Studies

Basic Engineering Studies

 Main Circuit Design

 Reactive Power Compensation

Equipment Design Studies

Equipment Design Studies

 TOV, TRV and Insulation Coordination  Circuit Current Requirements

 AC and DC Filter Rating

DC Control and Protection Studies

DC Control and Protection Studies

 Operation and Control Strategy  Switchgear Control and Sequences

(7)

Main System Studies for BP2:

Main System Studies for BP2:

Thyristor Valves Studies

Thyristor Valves Studies

 Valve Electrical and Thermal Design  Valve Mechanical Design

 Redundancies and Reliability

System Performance Studies

System Performance Studies

 Fundamental Frequency Dynamic Performance (Stability Study)  AC and DC Filter Performance (and Inductive Coordination)

 PSCAD/EMTDC Dynamic Performance Study (DPS)  RTDS Dynamic Performance Study (DPS)

 Subsynchronous Oscillations  Radio and Carrier Interference  Audible Noise

(8)

Main Scheme Parameters:

Main Scheme Parameters:

• Provides the main parameters, the basic steady-state

operating modes and the basic control philosophy

• Quantities determined by the main circuit calculations:

 Rated power and voltage of the converter transformers  Reactances of the converter transformers

 Range and step size of the LTC of the converter transformers

 Maximum and minimum values of Vdc, Idc and Pdc for each operating

mode, considering measurement errors, control dead-band, etc.

(9)

Main Scheme Parameters:

Main Scheme Parameters:

• Operating Configurations

 Bipolar (P3 on L3 and P4 on L4)

 Monopolar with Ground Return (P3/L3 or P4/L4 out of service)  Monopolar with Metallic Return (Neutral of P3 on L4)

• Operating Modes in Bipolar or Monopolar Operation

 Nominal Voltage (600 kV)  Reduced Voltage (420 kV)

 High Mvar Consumption (High Gamma)

 Paralleled Converters (P1 // P3 and/or P2 // P4)

 Paralleled Transmission Lines (L1 // L3 and/or L2 // L4)  Crossed Line (P3 on L1 or P4 on L2)

(10)

Thyristor Valves:

Thyristor Valves:

5” (125 mm) 8.5 kV thyristor with electrical triggering (ETT)

5” (125 mm) 8.5 kV thyristor with electrical triggering (ETT)

3 redundant thyristor levels 3 redundant thyristor levels

78 thyristors per valve (including redundancy) 83 thyristors per valve

(including redundancy)

7 valve modules in series per valve 7 valve modules in series per valve

1 x 12 pulse bridge per pole 1 x 12 pulse bridge per pole

6 double valves per pole 6 double valves per pole

Suspended valves Suspended valves

Indoor, air insulated and water-cooled Indoor, air insulated and water-cooled

(11)
(12)

H400 Thyristor Valve Module:

H400 Thyristor Valve Module:

(13)

H400 Thyristor Valve Module:

H400 Thyristor Valve Module:

(14)

Doublevalve

Doublevalve

Arrangement:

Arrangement:

7.5m

(15)

Doublevalve

(16)

Thyristor Valve Arrangement:

Thyristor Valve Arrangement:

2 poles Porto Velho Porto Velho Araraquara Araraquara 2 poles

6 double valves per pole (12 valves) 7 modules per valve

78 thyristor levels per valve Total = 1872 thyristor levels

6 double valves per pole (12 valves) 7 modules per valve

(17)

Converter Transformers:

Converter Transformers:

243 kV 258 kV

Rated valve-winding voltage

500 kV 500 kV

Rated line side voltage

1.25% 1.25% Tap step ±7.5% 0.15 pu -4.5% to +35.5% 958 MVA 1-phase, 2-winding Porto Velho Porto Velho ±7.5% Design tolerance (absolute)

0.15 pu Nominal impedance

-6.5% to +33.5% Tap range

902 MVA Rated power (6-pulse, 3ø)

(18)

Converter Transformers:

Converter Transformers:

Porto

Porto VelhoVelho

Y

(19)

Converter Transformers:

Converter Transformers:

Porto

Porto VelhoVelho

Y

(20)

Reactive Power Compensation Design:

Reactive Power Compensation Design:

• Main Requirements of ANEEL Edital:

 AC voltage at converter bus: 475 kV < V < 550 kV  System frequency: 59.5Hz < f < 60.5Hz

 Outage of the largest sub-bank of the entire station  Reactive power from the AC system (Porto Velho):

 Limited by a power factor of 0.93 (overexcited) at machines terminals  Proportional to the DC power rating of BP2 (3150 MW)

(21)

Reactive Power Compensation Design:

Reactive Power Compensation Design:

• Questions raised during the project:

 What should be the available reactive power provided by the AC system

at Porto Velho, since the system configuration and important parameters have changed from those of the auction?

 It was agreed to use the value of the basic design stage, i.e. 705 Mvar

 How to consider the measurement errors and tolerances?

 ANEEL Edital is silent on this subject

(22)

Reactive Power Compensation Design:

Reactive Power Compensation Design:

• Questions raised during the project:

 ANEEL Edital for BP2 (LF-CC) requests that the reactive power

compensation considers the outage of the largest sub-bank of the entire

station, not of each individual bipole.

 BP1 should be responsible for the spare sub-bank

 ANEEL Edital presented no specific requirement for joint operation

 At low power, a relatively high amount of capacitance for each bipole/B2B independently is required due to harmonic performance restrictions

 Care should be taken in joint operation to deal with the network capability to absorb this excessive reactive power, self-excitation of generators, etc.

 Operation restrictions should apply in this case: limit maximum AC voltage, turn-off converters, etc.

(23)

Reactive Power Compensation Design:

Reactive Power Compensation Design:

Porto Velho

Total Mvar = 5 x 247 = 1235 Mvar

Total

Total

Mvar

Mvar

= 5 x 247 =

= 5 x 247 =

1235

1235

Mvar

Mvar

(24)

•RdcRdc maxmax •

•VdcrVdcr min within min within control

control deadbanddeadband •

•VdcVdc error = 0.5%error = 0.5% •

•IdcIdc error = 0.5%error = 0.5% •

•αα error = 1error = 1ºº •

•XtXt toltol maxmax •

•VacVac minmin •

•f minf min

Porto Velho

Reactive Power Compensation Design:

Reactive Power Compensation Design:

662,7

662,7 MvarMvar

(25)

Reactive Power Compensation Design:

Reactive Power Compensation Design:

Araraquara

Total Mvar =

4 x 305 + 2 x 316

= 1852 Mvar

Total

(26)

•RdcRdc minmin •

•VdcrVdcr min within min within control

control deadbanddeadband •

•VdcVdc error = 0%error = 0% •

•IdcIdc error = 0%error = 0% •

•γγ error = 0error = 0ºº •

•XtXt toltol maxmax •

•VacVac minmin •

•f minf min

Araraquara

Reactive Power Compensation Design:

Reactive Power Compensation Design:

~0

(27)

AC Filter Design:

AC Filter Design:

• AC System frequency range:

 Continuous: 60 ± 0.5 Hz

 Short duration (20 seconds): 56 to 66 Hz

• AC voltage range:

 475 kV to 550 kV on both terminals

• AC voltage negative phase sequence:

 1% for performance calculations  2% for rating calculations

• Ambient temperature range:

(28)

AC Filter Design:

AC Filter Design:

• Network impedance was not provided in ANEEL Edital, but after several

discussions both BP1 and BP2 have used the same scatter points (but

different envelopes)

 The calculation of Z(w) considered different generation scenarios, single

contingencies, system frequency variation, variation of resistance with harmonic frequency, no loads, grouping of adjacent harmonics, etc.

• Harmonic currents were calculated using non-classical methodology

considering AC/DC interaction (ALSTOM’s JESSICA) for all harmonics

 Worst case parameters deterministically combined to maximize the current

generation: full range of DC power, AC voltage and control angles; tolerances and asymmetries on converter transformer impedances and control angles; etc.

• Performance calculated using resonance-method

(29)

AC Filter Design:

AC Filter Design:

• Harmonic performance requirements:

C B A

Requirement

No requirement Low ambient Overload

Short-time Overload Long-time Overload

AC Network: N and N-1 Filter banks: N

Reduced voltage (70%) High Gamma (High Mvar)

AC Network: N and N-1 Filter banks: N and N-1 Normal (Bipolar)

Reverse Power Parallel Operation

(30)

AC Filter Design:

AC Filter Design:

• Harmonic distortion limits:

THD = 1,5%

0,4%

27

All

0,3%

0,6%

3 a 25

Limit (%)

Order

Limit (%)

Order

Even

Odd

1

100

= ⋅

h h

V

D

%

V

50 2 2 =

=

h h

THD

D

(

)

50 1 1 =

=

h h h

V W

TIF

V

(31)

AC Filter Design:

AC Filter Design:

• Filter arrangement for Araraquara

• Relatively strong and

well-damped network

• Low-order filters were not

required

• Broad-band damped filters • Capacitors to complement

the reactive compensation

• Common filter design was

agreed with BP1

• Pre-existing harmonics

(32)

AC Filter Design:

AC Filter Design:

• Filter arrangement for Porto Velho

2.59 uF 2 x A – 247 Mvar 698 Ω 12.6 mH 1.84 uF 37.7 uF 4354 Ω 0.77 uF 6822 Ω 186.5 mH 18.99 mH 247 Mvar 3/13/40

• Network with very low damping • Wide range of harmonic

impedance (90 generators!)

• Low-order filters were required to

avoid severe resonances (mainly at low power)

• Use of triple-tuned filters

• Different configuration from BP1 • Joint performance was not an

issue

• Rating has considered the

(33)

DC Filter Design:

DC Filter Design:

• ANEEL Edital put responsibility on manfacturer/utility for determining suitable limits of the equivalent disturbing current (Ieq) along the DC line

• But this is not possible without a detailed inductive co-ordination study (i.e. assess the impact of induced harmonics in all telephone systems)

• None of the necessary data for this was available at the basic design stage. So the initial Ieq limits were arbitrarily chosen based on previous experience and the DC filters had to be designed according to these limits

• A detailed inductive co-ordination study was conducted after filter design and has confirmed the selected limit values of disturbing current assumed for

almost all circuits and operating conditions

Rare short-time conditions and filter outages 4000 mA

Monopolar, reduced voltage and reverse power operation with all filters available

2200 mA

(34)

DC Filter Design:

DC Filter Design:

• DC Harmonic Model

Three-pulse harmonic model of converters Return paths for triplen

(35)

DC Filter Design:

DC Filter Design:

• DC Filter, Neutral Capacitor and Smoothing Reactor

Configuration (per pole per station)

The smoothing reactor is split into 3 units:

• 1 x 15mH on HV side • 2 x 150mH on LV side The smoothing reactor is split into 3 units:

• 1 x 15mH on HV side • 2 x 150mH on LV side

Due to the smoothing reactor arrangement and to the flow of high-order triplen harmonics (non-characteristics), the ST50 filter is connected direct to ground

Due to the smoothing reactor arrangement and to the flow of high-order triplen harmonics (non-characteristics), the ST50 filter is connected direct to ground

Common filter design was agreed with BP1 Common filter design was agreed with BP1

50th

(36)

DC Filter Design:

DC Filter Design:

• Example of Ieq Profile: Bipolar, 600kV

Lower away from the stations

Higher close to the stations

(37)

DC Filter Rating:

DC Filter Rating:

• It was noticed that harmonic orders higher than 50th (up to 64th) had an considerable effect on the voltage ratings of reactor L3 of filter Type A (6th/12th/50th) and reactor L1 of filter Type B (50th)

• This is because both Type A and Type B filters are tuned at 50th, so higher

order harmonics (mainly 63th) have significant impact on the rating

(38)

Basic Control Philosophy:

Basic Control Philosophy:

→ Change α to keep constant Idc

→ Tap-changer control to keep 10°< α < 16.5°

(39)

Basic Control Philosophy:

Basic Control Philosophy:

Idc

Idc ControlControl

(40)

Basic Control Philosophy:

Basic Control Philosophy:

→ Fast DC voltage control cascaded with slow γ control (γORD=18.5º) → Tap-changer control to keep 592.5 kV < Vdcr < 607.5 kV

(41)

Basic Control Philosophy:

Basic Control Philosophy:

→ Fast DC voltage control

cascaded with slow γ

(42)

VDCOL IORDr VORD Vdcr IORDLr LOOP 1 Idc Idcr ERR1 LOOP 5 α Max ERR5 αr AMXORD (165º) LOOP 7 Vdc Max ERR7 RVORD (1.1 pu) Vdcr LOOP 8 α Min ERR8 αr AORDR (2º) FRAO (120º) ≤0 >0 Force Retard ERRr LOOP SELECTION LOGIC

Normal operating mode

Phase Loop Control (Rectifier):

Phase Loop Control (Rectifier):

(43)

Phase Loop Control (Inverter):

Phase Loop Control (Inverter):

Normal operating mode

(44)

∑ ∑ V O R D ∑

Pole Power Control:

Pole Power Control:

ORD ORD ORD

P

I

=

V

Power Trim function

VORD x PORD characteristic

Short-Time Overload Limiter (STOL) 1 1+T st 1 1+T st

(45)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

• Demonstrate that the response of the HVDC scheme to a variety of transient disturbances will ensure stable operation under severe operation conditions • Evaluate the dynamic interactions between the HVDC scheme and the

associated AC systems • Mains aspects of interest:

 Recovery from faults

 Commutation failure performance

 Voltage and frequency control on the AC side

 Damping of low-frequency oscillations

• Detail HVDC control system representation, including firing control

(46)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

(47)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

Bypass inverter during 3ø inverter faults

Fault duration t(s) VrmsY 0.6 0.3 1.0 t(s) 30ms 12ms 1 0 BPY F1Y F5Y F9Y F7Y F11Y F12Y F4Y F2Y F8Y F10Y F6Y F3Y T 2 T 2 T 2 T 2 T 2 T 2 T 2 T 2 IDCY 0.01500 [H] 0.300 [H] T 2 T 2 T 2 T 2 • During commutation failures, inverter is

naturally “by-passed”

(48)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

Bypass inverter during 3ø inverter faults

AR_3Fa.adf: IdcF_Y:1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.3 0.6 0.9 1.2 1.5 1.8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 Idc

Idc (without Bypass)(without Bypass) Idc

Idc (with Bypass)(with Bypass) Bypass command

Bypass command

Pdc

Pdc (without Bypass)(without Bypass) Pdc

Pdc (with Bypass)(with Bypass) Bypass command

(49)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

“Gamma Kick” based on commutation failure indication

∑ CFY ∆γord 1 0 0 20 Toff=50ms CF duration t(s) t(s)

• Included mainly to deal with remote and non-bolted faults • Voltage distortion during the fault period lead to commutation failure during recovery

(50)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

“Gamma Kick” based on commutation failure indication

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Pdc

Pdc (without Gamma Kick)(without Gamma Kick) Pdc

Pdc (with Gamma Kick)(with Gamma Kick)

CFY (without Gamma Kick) CFY (without Gamma Kick)

CFY (with Gamma Kick)

CFY (with Gamma Kick)

3

3øø inverter faultinverter fault to

(51)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

Recover from faults to VORD = 0.9 pu

Note: The VORD output is fed only in VDCOL and Phase-Loop Control, not in Pole Power Control Fault duration t(s) VdcX 0.6 0.1 1.0 t(s) 1.0 0.9 VORD Rate = 0.02 pu/s Rate = 0.02 pu/s

• As part of recovery strategy, DC voltage order (VORD) is

recovered to 90% after faults • Rump up to 100% is performed slowly

• Due to frequency control, DC current is increased, which

increases overlap and reduces γ

(52)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

Power-Frequency Control (PFC)

• The PFC modulates the DC power order to stabilize the frequency variations at Porto Velho side

• A high-gain path is added to deal with unsuccessful auto-reclosure of faulted lines

3 pu/pu

6 pu/pu fmin = 57.5 Hz

(53)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

(54)

(file AR_3Fa.adf; x-var Domain) VLWY:1 VLWY:2 VLWY:3 0,0 0,4 0,8 1,2 1,6 2,0 -800 -600 -400 -200 0 200 400 600 800

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

• Typical response for a 3ø fault at Araraquara

(file AR_3Fa.adf; x-var Domain) CFY:1

0,0 0,4 0,8 1,2 1,6 2,0 0,0 0,2 0,4 0,6 0,8 1,0 1,2 CFY CFY Va

Va VbVb VcVc AC voltage collapsesAC voltage collapses at inverter side due to

at inverter side due to

solid fault

solid fault

A commutation failure

A commutation failure

starts at the inverter

starts at the inverter

and holds for the whole

and holds for the whole

fault period

(55)

(file AR_3Fa.adf; x-var Domain) PdcF_X:1 IdcF_X:1 Iordrl:1 0,0 0,4 0,8 1,2 1,6 2,0 -0,50 -0,25 0,00 0,25 0,50 0,75 1,00 1,25 1,50

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

• Typical response for a 3ø fault at Araraquara

PdcX PdcX 160 160 msms IdcX IdcX

(file AR_3Fa.adf; x-var Domain) Alpha_X:1

0,0 0,4 0,8 1,2 1,6 2,0 0 30 60 90 120 150 AlphaX AlphaX Idc

Idcincreases dueincreases due to commutation to commutation failure failure Inverter control Inverter control forms a by

forms a by--passpass

Rectifier control

Rectifier control

increases

increases αα(over 90(over 90°°))

DC power reverts

DC power reverts

due to

due to VdcVdcreversalreversal

Rectifier VDCOL keep

Rectifier VDCOL keep

Idc

Idcflowing during theflowing during the fault (IMIN=0.5)

fault (IMIN=0.5)

IordX

(56)

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

• Typical response for a 3ø fault at Araraquara

AR_3Fa.adf: CFY:1 AR_3Fb.adf: GammaKick_Loop3:1 0,0 0,4 0,8 1,2 1,6 2,0 0 5 10 15 20 25 30 CFY CFY Gamma

Gamma KickKick

(file AR_3Fa.adf; x-var Domain) Gamma_Y:1

0,0 0,4 0,8 1,2 1,6 2,0 0 30 60 90 120 150 180 GammaY GammaY Inverter control Inverter control increase

increase γγordordbyby2020°°

(

(GammaGammaKickKick))

Gamma stays high

Gamma stays high

during power recovery

during power recovery

to prevent post

to prevent post--fault fault commutation failures

(57)

(file AR_3Fa.adf; x-var Domain) VrmsY:1 0,0 0,4 0,8 1,2 1,6 2,0 0,7 0,8 0,9 1,0 1,1 1,2 1,3

(file AR_3Fa.adf; x-var Domain) PdcF_X:1

0,0 0,4 0,8 1,2 1,6 2,0 -0,6 -0,3 0,0 0,3 0,6 0,9 1,2

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

• Typical response for a 3ø fault at Araraquara

PdcX

PdcX

VrmsY

VrmsY During recovery, voltage drops due to increase of During recovery, voltage drops due to increase of

DC current and high

DC current and high γγ

At fault clearing, no

At fault clearing, no

power is being

power is being

transmitted while filters

transmitted while filters

are still connected. Thus

are still connected. Thus

an overvoltage appears.

(58)

(file AR_3Fa.adf; x-var Domain) Iordrl:1+DPFC:1 Iordrl:1 0,0 0,4 0,8 1,2 1,6 2,0 0,5 0,6 0,7 0,8 0,9 1,0 1,1 1,2

(file AR_3Fa.adf; x-var Domain)

factors: 1 Wmaq_SCF2:1 60 0,0 0,4 0,8 1,2 1,6 2,0 60,0 60,5 61,0 61,5 62,0 62,5 63,0 63,5

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

• Typical response for a 3ø fault at Araraquara

Frequency

Frequency

The AC voltage drop is

The AC voltage drop is

aggravated by this

aggravated by this

increase of DC current

increase of DC current

Due to load rejection,

Due to load rejection,

S.Antonio

S.Antonioand and JirauJirau machines speed up and

machines speed up and

frequency rises

frequency rises

The power

The power--frequency frequency controller (PFC) of HVDC

controller (PFC) of HVDC

increases

increases IordIordto limit to limit the over

the over--frequencyfrequency

IordX

IordX

IordX

(59)

(file AR_3F_original.adf; x-var Domain) VrmsY:1 0 1 2 3 4 5 0,0 0,3 0,6 0,9 1,2 1,5

(file AR_3F_original.adf; x-var Domain)

factors: 1 Wmaq_SCF2:1 60 0 1 2 3 4 5 58,5 59,5 60,5 61,5 62,5 63,5

PSCAD Dynamic Performance Study (DPS)

PSCAD Dynamic Performance Study (DPS)

• Typical response for a 3ø fault at Araraquara

Frequency Frequency VrmsY VrmsY After HVDC recovery, After HVDC recovery,

voltage and frequency

voltage and frequency

oscillate and stabilize in

oscillate and stabilize in

normal values

(60)

Conclusions:

Conclusions:

• The converter station equipment has been designed to meet all the performance requirements of the ANEEL Edital and according to the manufacturer practices and international standards

• The basic project design is under approval process by ONS and the beginning of commercial operation is provisioned to April 2013

• Negative aspects of the project:

 Lack of data, unclear definition of responsibilities and ambiguous requirements of ANEEL Edital

 Absence of specific requirements for joint operation

 Difficulty in exchanging models and important information between the manufacturers due to confidentiality aspects

 The factors above caused many times long-running discussions, re-design during the project and sometimes contractual conflict

(61)

Thank you!

Fernando Cattan Jusan Eletrobras Furnas

E-mail: cattan@furnas.com.br

Fernando Cattan Jusan Eletrobras Furnas

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