Capítulo 6 Pipeline Morgan Kaufmann Publishers

(1)



1998 Morgan Kaufmann Publishers

Capítulo 6

Pipeline

(2)



1998 Morgan Kaufmann Publishers

Pipeline: analogia com linha de produção

• Tempo de fabricação de um carro: C+M+C+P+A

• Taxa de produção (carros/h): medido na saída

– Throughput (vazão): depende do número de estágios e do

balanceamento

• Objetivo do pipeline:

– distribuir e balancear o tempo em cada estágio

– otimizar o uso de HW dos estágios (taxa de ocupação)

– resumo: aumentar a velocidade e diminuir o hardware

carro1

Chassi Mec

Carroc. Pint.

Acab.

carro2

Chassi Mec

Carroc. Pint.

Acab.

carro3

Chassi Mec

Carroc. Pint.

Acab.

(3)

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1998 Morgan Kaufmann Publishers

Pipelines

• Melhorar o desempenho através do aumento do throughput

• tempo de execução de uma instrução: 8 ns e 9 ns (com ou sem pipe)

• throughput: 1 instr / 8ns (sem pipeline) ou 1 instr / 2 ns (com)

• # de estágios = 5; ganho de 4:1;

Instruction

fetch

Reg

ALU

access Reg

Data

8 ns

Instruction

_fetch

Reg

ALU

_{access Reg}

Data

8 ns

Instruction

_fetch

8 ns

Time

lw $1, 100($0)

lw $2, 200($0)

lw $3, 300($0)

2

4

6

8

10

12

14

16

18

2

4

6

8

10

12

14 ...

Program

execution

order

(in instructions)

Instruction

fetch

Reg

ALU

access Reg

Data

Time

lw $1, 100($0)

lw $2, 200($0)

lw $3, 300($0)

2 ns

Instruction

_fetch

Reg

ALU

_{access Reg}

Data

2 ns

Instruction

_fetch

Reg

ALU

_{access Reg}

Data

2 ns

Program

execution

order

(4)



1998 Morgan Kaufmann Publishers

Pipeline

• O que o torna factível?

– Todas as instruções são do mesmo tamanho

– Poucos formatos de instruções

– Operandos de memória aparecem apenas em loads e stores

• O que o torna difícil

– Hazards estruturais: recursos compartilhados (Ex: memória)

– Hazards de controle: Preocupação com instruções de saltos

– Hazards de dados: uma instrução depende dos resultados

gerados pela instrução anterior

• Nosso foco: um pipeline simples abordando essas questões!

• Posteriormente (ou durante essa parte do curso..)

– Tratamento de exceções...

– Execução inorder, foradeordem, etc.

(5)

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1998 Morgan Kaufmann Publishers

Pipeline: Idéia básica

• O que é necessário para dividir a via de dados em estágios de execução?

Instruction

memory

Address

4

32

0 Add Add

_result

Shift

left 2

Instruction

M

ux

0

1 Add

PC

0 Write

data

M

_u

x

1 Registers

Read

data 1

Read

data 2

Read

register 1

Read

register 2

16 _Sign

extend

Write

register

Write

data

Read

data

Address

Data

memory

1 ALU

result

M

u

x

ALU

Zero

IF : Instruction fetch

ID: Instruction decode /

(6)



1998 Morgan Kaufmann Publishers

IM

Reg

ALU

DM

Reg

IM

Reg

ALU

DM

Reg

CC 1

CC 2

CC 3

CC 4

CC 5

CC 6

CC 7

Time (in clock cycles)

lw $2, 200($0)

lw $3, 300($0)

Program

execution

order

(in instructions)

lw $1, 100($0)

IM

Reg

ALU

DM

Reg

Uma representação para o pipeline

• Hachurado representa “atividade”

• Representação alternativa: imaginando que cada instrução tenha a sua

própria via de dados

(7)

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1998 Morgan Kaufmann Publishers

Via de dados com pipeline

• O que é produzido em cada estágio é armazenado em um registrador de

pipeline para uso pelo próximo estágio

• Problemas com o endereço do registrador de escrita?? Caminhando para

esquerda?

Instruction

memory

Address

4

32

0 Add Add

_result

Shift

left 2

Ins

truc

tion

IF/ID

EX/MEM

MEM/WB

M

ux

0

1 Add

PC

0 Write

data

M

ux

1 Registers

Read

data 1

Read

data 2

Read

register 1

Read

register 2

16 Sign

extend

Write

register

Write

data

Read

_data

1 ALU

result

M

ux

ALU

Zero

ID/EX

Data

memory

Address

(8)



1998 Morgan Kaufmann Publishers

Via de dados corrigida

Instruction

memory

Address

4

32

0 Add Add

_result

Shift

left 2

Ins

tru

ctio

n

IF/ID

EX/MEM

MEM/WB

M

ux

0

1 Add

PC

0 Address

W rite

_data

M

ux

1 Registers

Read

data 1

Read

data 2

Read

register 1

Read

register 2

16 Sign

extend

Wr ite

reg is ter

Write

data

Read

_data

Data

memory

1 ALU

result

M

ux

ALU

Zero

ID/EX

(9)

Exemplo com

sub e lw (1)

Instruction memory Address 4 32 0

Add Add_result

Shift left 2 In st ru ct io n

IF/ID EX/MEM MEM/WB

M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALUZero ID/EX

Instruction decode

lw $10, 20($1)

Instruction fetch

sub $11, $2, $3

Add Add_result

IF/ID EX/MEM MEM/WB

M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALUZero ID/EX

Instruction fetch

lw $10, 20($1)

Address Data memory Address Data memory

Clock 1

Clock 2

(10)

Instruction memory Address

4

0

Add Add_result

IF/ID EX/MEM MEM/WB

M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 32 16 Sign extend Write register Write data

Memory

lw $10, 20($1)

Read data 1 ALU result M u x ALUZero ID/EX

Execution

sub $11, $2, $3

Instruction memory Address 4 0

Add Add_result

IF/ID EX/MEM MEM/WB

M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 Write register Write data Read data 1 ALU result M u x ALUZero ID/EX

Execution

lw $10, 20($1)

Instruction decode

sub $11, $2, $3

32 16 Sign extend Address Data memory Data memory Address

Clock 3

Clock 4

Exemplo com

sub e lw (2)

(11)

Exemplo com

sub e lw (3)

Add Add_result

1 ALU result Zero Shift left 2 In st ru ct io n

IF/ID ID/EX EX/MEM MEM/WB

Write back

M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend M u x ALU Read data Write register Write data

lw $10, 20($1)

Add Add_result

1 ALU result Zero Shift left 2 In st ru ct io n

IF/ID ID/EX EX/MEM MEM/WB

Write back

M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend M u x ALU Read data Write register Write data

sub $11, $2, $3

Memory

sub $11, $2, $3

Address Data memory Address Data memory

Clock 6

Clock 5

(12)



1998 Morgan Kaufmann Publishers

Representando pipelines graficamente

• Essa representação pode ajudar a responder questões como:

– Quantos ciclos são necessários para executar esse código?

– O que a ULA está fazendo no ciclo 4?

• Use essa representação para entender melhor como o pipeline

funciona

IM

Reg

DM

Reg

IM

Reg

DM

Reg

CC 1

CC 2

CC 3

CC 4

CC 5

CC 6

Time (in clock cycles)

lw $10, 20($1)

Program

execution

order

(in instructions)

sub $11, $2, $3

ALU

(13)



1998 Morgan Kaufmann Publishers

Controle do pipeline

PC

Instruction

memory

Address

Ins

tru

cti

on

Instruction

[20–16]

MemtoReg

ALUOp

Branch

RegDst

ALUSrc

4

16

32 Instruction

[15–0]

0

0 Registers

Write

register

Write

data

Read

data 1

Read

data 2

Read

register 1

Read

register 2

Sign

extend

M

u

x

1 Write

data

Read

data

M

u

x

1 ALU

control

RegWrite

MemRead

Instruction

[15–11]

6 IF/ID

ID/EX

EX/MEM

MEM/WB

MemWrite

Address

Data

memory

PCSrc

Zero

Add Add

_result

Shift

left 2

ALU

result

ALU

Zero

Add

0

1 M

u

x

0

1 M

u

x

• campo function é usado para controle da ALU (EX)

• sinais de controle: os mesmos do capítulo 5, ciclo único

• PC e registradores de pipeline escritos em todos ciclos: não é necessário controle

(14)

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1998 Morgan Kaufmann Publishers

• O que necessita ser controlado em cada estágio?

– Busca da instrução e incremento do PC

– Decodificação da instrução / Leitura do registrador

– Execução

– Leitura/Escrita da memória

– Escrita no registrador

• Como o controle seria manipulado em um projeto de automóvel

– Controle central indicando o que cada parte deve fazer?

–

Controle do pipeline

(15)



1998 Morgan Kaufmann Publishers

• Os sinais de controle “passam” pelo pipeline assim como os dados

Controle do pipeline

Execution/Address Calculation

stage control lines

Memory access stage

control lines

Writeback

stage control

lines

Instruction

Reg

Dst

ALU

Op1

ALU

Op0

ALU

Src Branch

Read

Mem

Write

Mem

write

Reg

Mem to

Reg

Rformat

1

0

1

0 lw

₀

₁

₀

₁

₀

₁

sw

_X

₀

₁

₀

₁

₀

_X

beq

_X

₀

₁

₀

₁

₀

_X

Control

EX

M

WB

M

WB

IF/ID

ID/EX

EX/MEM

MEM/WB

Instruction

(16)



1998 Morgan Kaufmann Publishers

Controle na via de dados

PC

Instruction

memory

Ins

tru

ct

ion

Add

Instruction

[20–16]

Me

mt

oR

eg

ALUOp

Branch

RegDst

ALUSrc

4

16

32 Instruction

[15–0]

0

0 M

u

x

0

1 Add Add

_result

Registers

Write

register

Write

data

Read

data 1

Read

data 2

Read

register 1

Read

register 2

Sign

extend

M

u

x

1 ALU

result

Zero

Write

data

Read

data

_M

u

x

1 ALU

control

Shift

left 2

Re

gW

rite

MemRead

Control

ALU

Instruction

[15–11]

6 EX

M

WB

M

WB

IF/ID

PCSrc

ID/EX

EX/MEM

MEM/WB

M

u

x

0

1 Me

m

W

rite

Address

Data

memory

Address

(17)



1998 Morgan Kaufmann Publishers

Exemplo

(pag. 471)

Instruction memory Instruction [20–16] Me mt oR eg ALUOp Branch RegDst ALUSrc 4 Instruction [15–0] 0 M_u x 0 1

Add Add_result

Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M_u x 1 ALU result Zero ALU control Shift left 2 Re gW rite MemRead Control ALU Instruction [15–11] EX M WB M WB WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID : b e fore<1> E X : b efore <2> M E M : be fore<3> W B : befo re < 4>

MEM/WB IF : lw $10, 2 0($1) 000 00 0000 000 00 00 0 0 00 0 0 0 0 0 M ux 0 1 Add PC 0 Data memory Address Write data Read_data M_u x 1 WB EX M Instruction memory Me mt oR eg ALUOp Branch RegDst ALUSrc 4 0 M_u x 0 1

Add Add_result

Write register Write data M u x 1 ALU result Zero ALU control Shift left 2 Re gW rite ALU M WB WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID : lw $10 , 20($1) E X : b efore <1> M E M : be fore<2> W B : befo re < 3>

MEM/WB IF : sub $1 1, $2, $3 010 11 0001 000 00 00 0 0 00 0 0 0 0 0 M_u x 0 1 Add PC 0 Write data Read_data M ux 1 lw _Control Registers Read data 1 Read data 2 Read register 1 Read register 2 X 10 20 X 1 Instruction [20–16] Instruction [15–0] Sign extend Instruction [15–11] 20 $X $1 10 X Me mW rite MemRead Me mW rite Data memory Address Address Address C lo c k 2 C lo c k 1

lw

$10, 20($1)

sub

$11, $2, $3

and

$12, $4, $5

or

$13, $6, $7

add

$14, $8, $9

(18)



1998 Morgan Kaufmann Publishers

Exemplo

(pag. 471)

Instruction memory Address Instruction [20–16] Me mt oR eg Branch ALUSrc 4 Instruction [15–0] 0 1

Add Add_result

Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 ALU result Shift left 2 Re gW rite MemRead Control ALU Instruction [15–11] EX M WB WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID : sub $11, $ 2, $3 E X: lw $10, . . . M E M : b efore<1 > W B : be fore<2>

MEM/WB IF : an d $12 , $4, $ 5 000 10 1100 010 11 00 0 1 00 0 0 0 0 0 M ux 0 1 Add PC 0 Write data Read_data M ux 1 WB EX M Instruction memory Address Me mt oR eg ALUOp Branch RegDst ALUSrc 4 0 0 1

Add Add_result

Write register Write data 1 ALU result ALU control Shift left 2 Re gW rite M WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID : a nd $ 12, $ 4 , $5 E X: sub $1 1, . . . M E M : lw $ 10 , . . . W B : be fore<1>

MEM/WB IF : or $1 3, $6 , $ 7 000 10 1100 000 10 10 1 0 11 1 0 0 0 0 M ux 0 1 Add PC 0 Write data M ux 1 and _Control Registers Read data 1 Read data 2 Read register 1 Read register 2 12 X X 5 4 Instruction [20–16] Instruction [15–0] Instruction [15–11] X $5 $4 X 12 Me mW rite MemRead Me mW rite sub 11 X X 3 2 X $3 $2 X 11 $1 20 10 M_u x 0 M_u x 1 ALUOp RegDst ALU control M WB $3 $2 11 M u_x M u x ALU

Address Read_data

Data memory 10 WB Zero Zero Sign extend Sign extend Data memory Address C lo c k 3 C lo c k 4

lw

$10, 20($1)

sub

$11, $2, $3

and

$12, $4, $5

or

$13, $6, $7

add

$14, $8, $9

(19)



1998 Morgan Kaufmann Publishers

Exemplo

(pag. 471)

Instruction memory Address Instruction [20–16] Branch ALUSrc 4 Instruction [15–0] 0 1

Add Add_result

Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 ALU result Shift left 2 Re gW rite MemRead Control ALU Instruction [15–11] EX M WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID : o r $ 13, $6 , $7 E X : and $12, . . . M E M : sub $1 1, . . . W B : lw $ 10, . . .

MEM/WB IF : add $14, $ 8, $ 9 000 10 1100 000 10 10 1 0 10 0 0 0 M u x 0 1 Add PC 0 Write data Read data _M ux 1 WB EX M Instruction memory Address Me mt oR eg ALUOp Branch RegDst ALUSrc 4 0 0 1

Add Add_result

1 ALU result ALU control Shift left 2 Re gW rite M WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID : a dd $14 , $8, $ 9 E X : o r $1 3 , . . . M E M : an d $12, . . . W B : su b $11 , . . .

MEM/WB IF : afte r< 1 > 000 10 1100 000 10 10 1 0 10 0 0 0 1 0 M ux 0 1 Add PC 0 Write data M_u x 1 add _Control Registers Read data 1 Read data 2 Read register 1 Read register 2 14 X X 9 8 Instruction [20–16] Instruction [15–0] Instruction [15–11] X $9 $8 X 14 Me mW rite MemRead Me mW rite or 13 X X 7 6 X $7 $6 X 13 $4 M_u x 0 M_u x 1 ALUOp RegDst ALU control M WB $7 $6 13 M_u x M_u x ALU _Read data 12 WB 11 10 10 $5 12 WB Me mt oR eg 1 1 11 11 Write register Write data Zero Zero Data memory Address Data memory Address Sign extend Sign extend C lo c k 5 C lo c k 6

lw

$10, 20($1)

sub

$11, $2, $3

and

$12, $4, $5

or

$13, $6, $7

add

$14, $8, $9

(20)



1998 Morgan Kaufmann Publishers

Exemplo

(pag. 471)

Instruction memory Address Instruction [20–16] Branch ALUSrc 4 Instruction [15–0] 0 1

Add Add_result

Registers Write register Write data ALU result Shift left 2 Re gW rite MemRead Control ALU Instruction [15–11] Sign extend EX M WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID: afte r< 1 > E X: a dd $ 14, . . . M EM : or $13, . . . W B: and $1 2 , . . .

MEM/WB IF : after<2> 000 00 0000 000 10 10 1 0 10 0 0 0 M u x 0 1 Add PC 0 Write data Read data _M ux 1 WB EX M Instruction memory Address Me mt oR eg ALUOp Branch RegDst ALUSrc 4 0 0 1

Add Add_result

1 ALU result Zero ALU control Shift left 2 Re gW rite M WB Ins tru cti on

IF/ID ID/EX EX/MEM

ID: afte r< 2 > E X: after<1> M EM : add $14, . . . W B: or $13, . . .

MEM/WB IF : after<3> 000 00 0000 000 00 00 0 0 10 0 0 0 1 0 M ux 0 1 Add PC 0 Write data M ux 1 Control Registers Read data 1 Read data 2 Read register 1 Read register 2 Instruction [20–16] Instruction [15–0] Sign extend Instruction [15–11] Me mW rite MemRead Me mW rite $8 M_u x 0 M_u x 1 ALUOp RegDst ALU control M WB M_u x M u x ALU _Read data 14 WB 13 12 12 $9 14 WB Me mt oR eg 1 0 13 13 Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Zero Data memory Address Data memory Address C lo c k 7 C lo c k 8

lw

$10, 20($1)

sub

$11, $2, $3

and

$12, $4, $5

or

$13, $6, $7

add

$14, $8, $9