AMD 2700BKX4LB Microprocessor Structural Analysis

October 6, 2005

AMD

2700BKX4LB Microprocessor

Structural Analysis

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AMD 2700BKX4LB Microprocessor

Structural Analysis

Table of Contents

1 Overview

2 Device Overview

2.1 Package and Die

2.2 Die Features

3 Package Overview

3.1 Printed Wiring Board and Die

3.2 Solder Bumps

3.3 Package Pins

4 Process Analysis

4.1 General Device Structure

4.2 Die Edge and Die Seal

4.3 Bond Pads

4.4 Passivation and Interlevel Dielectrics

4.5 Metallization

4.6 Vias and Contacts

4.7 Transistors and Poly

4.8 Silicon Epitaxial Layer, Buried Oxide and Handle Wafer

5 SRAM Cell Analysis

5.1 SRAM Plan-View Analysis

AMD 2700BKX4LB Microprocessor

Structural Analysis

6 Materials Analysis

7 Critical Dimensions

8 Report Evaluation

1-1

AMD 2700BKX4LB Microprocessor

Overview

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1 Overview

2.1.4 Plan-View Package X-Ray

2.1.5 Plan-View Package X-Ray - Expanded View

2.1.6 Die Photograph

2.1.7 Die Marking 1

2.1.8 Die Marking 2

2.1.9 Die Deprocessed to Poly

2.2.1 Die Corner

2.2.2 Die Corner

2.2.3 Bond Pads

2.2.4 Bond Pads

3 Package Overview 3.1.1 Printed Wiring Board

3.1.2 Die Edge

3.2.1 Solder Bumps

3.2.2 Solder Bump

3.3.1 Package Pins

3.3.2 Package Pins and PWB

3.3.3 Package Pin and Land Detail

4 Process Analysis

4.1.1 General Device Structure of the 2700BKX4LB

4.2.1 Die Edge

4.2.2 Edge Seal

4.2.3 Detail of Edge Seal to Handle Wafer Contact

4.3.1 Typical Bond Pad

4.3.2 Metal 10 Bond Pad

4.4.1 Dielectric Stack

4.4.2 Passivation and ILD 8

1-2

AMD 2700BKX4LB Microprocessor

Overview

Rev 1.0 - Oct 27, 2004 09:29 \\vault-1\projwork\reports_public\amd\2700bkx4lb\sar\SAR-0410-004 4.4.4 TEM of ILD 7 4.4.5 ILD 7 4.4.6 TEM of ILD 6 4.4.7 TEM of ILD 5 4.4.8 TEM of ILD 4 4.4.9 TEM of ILD 3 4.4.10 TEM of ILD 2 4.4.11 TEM of ILD 1 4.4.12 Pre-Metal Dielectric

4.5.1 Minimum Pitch Metal 9

4.5.2 Minimum Pitch Metal 8

4.5.3 Minimum Pitch Metal 7

4.5.4 Minimum Pitch Metal 6

4.5.5 Minimum Pitch Metal 5

4.5.6 Minimum Pitch Metal 4

4.5.7 Minimum Pitch Metal 3

4.5.8 Minimum Pitch Metal 2

4.5.9 Minimum Pitch Metal 1

4.5.10 TEM of Metal 5 Through Metal 1 Composition

4.5.11 TEM of Metal 2 Liner

4.5.12 TEM Detail of Metal 2 Liner

4.5.13 TEM of Metal 1 Liner

4.6.1 Via 8’s and Via 7’s

4.6.2 Via 7’s and Via 6’s

4.6.3 Stacked Vias

4.6.4 Contacts to Polycide

4.6.5 TEM of Detail of W Plug Liner

4.6.6 Contacts to Si

4.6.7 TEM of Contact to Si and Polycide

4.7.1 TEM of General Transistor Structure

4.7.2 TEM of NMOS Gate

4.7.3 TEM of Stacking Faults (NMOS Gate Channel Region)

4.7.4 TEM of PMOS Transistor

4.7.5 TEM of Gate Dielectric

4.7.6 TEM Lattice Image of Gate Dielectric

4.7.7 TEM Si Island

4.7.8 Minimum Spaced Poly Gates

4.8.1 Silicon on Insulator

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AMD 2700BKX4LB Microprocessor

Overview

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5 SRAM Cell Analysis 5.0.1 6T SRAM Cell

5.1.1 SRAM at Metal 2 - Word Lines

5.1.2 SRAM at Metal 1 - Bit Lines, Power Distribution and Local Interconnect

5.1.3 SRAM at Polycide and Si

5.2.1 Overall Cross-Section of SRAM Cell - Parallel to Bit Line

5.2.2 Metal 1 Local Interconnect Strap

5.2.3 NMOS Pull Down Transistor

5.2.4 PMOS Pull Up Transistor

6 Materials Analysis (TEM-EDS) 6.2.1 TEM of Oxynitride Passivation 2

6.2.2 TEM of Nitride Passivation 1

6.2.3 TEM of Oxide ILD 8-4 (Line Dielectric)

6.2.4 TEM of Oxyinitride ILD 8-3 (Metal Etch Stop)

6.2.5 TEM of Oxide ILD 8-2 (Via Dielectric)

6.2.6 TEM of Nitride ILD 8-1 (Metal 8 Sealant)

6.2.7 TEM of Oxide ILD 7-5 (Line Dielectric)

6.2.8 TEM of SiOCN ILD 7-4 (Metal Etch Stop)

6.2.9 TEM of FSG ILD 7-3 (Via Dielectric)

6.2.10 TEM of Oxide ILD 7-2 (Adhesion Layer)

6.2.11 TEM of SiOCN 7-1 (Metal 7 Sealant)

6.2.12 TEM of Oxide ILD 6-6 (Sacrificial Planarization Layer)

6.2.13 TEM of SiOC ILD 6-5 (Line Dielectric)

6.2.14 TEM of FSG ILD 6-3 (Via Dielectric)

6.2.15 TEM of Oxide ILD 6-2 (Adhesion Layer)

6.2.16 TEM of SiOCN ILD 6-1 (Metal Sealant)

6.2.17 TEM of SiOC PMD 3 (Line Dielectric)

6.2.18 TEM of Oxide PMD 2 (Via Dielectric)

6.2.19 TEM of Nitride (Device Sealant)

6.2.20 TEM of Cobalt Silicided Gate Silicide

1-4

AMD 2700BKX4LB Microprocessor

Overview

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7 Critical Dimensions

1.2 List of Tables

4.4.1 Dielectric Layer Description and Composition

4.4.2 Dielectric Thickness

4.5.1 Metallization Vertical Dimensions

4.5.2 Metallization Horizontal Dimensions

4.6.1 Via and Contact Dimensions

4.7.1 General Transistor Structure

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