Chip behavior

In the chip no systematical failures are occurring, this meaning that the End of Life (EoL) was never reached in any tests and for any of the failure mechanisms occurring in the chip. Despite that fact, lifetime prediction diagrams with fitting functions were still established for all output parameters studied, by taking the total number of cycles performed for each test as the number of cycles to failure. So, all lifetime models defined for the chip are not representing an exact lifetime prediction, but a minimum of number of cycles that the chip is able to endure. Actually, the chip can survive even more cycles than what is shown. These lifetimes prediction diagrams should not be understood as lifetime models but are showing the Safe Operating Area (SOA) of the Cu clip module.

First the chip lifetime prediction is plotted Figure 7.1 in function of its warpage amplitude. As previously explained, under ΔTj=80-90K, a lifetime of 100 000 cycles is a minimum required while a lifetime of 1 million of cycles characterized already a robust module. For our experimental sensitivity study most of the tests were done with ΔTj= 120K, which is already a large temperature swing. On the graphic, one can see that for the worst case, the inverse of curvature radius amplitude reaches 1,1 m^-1 with ΔTj=170K and is able to survive more than 62 000 cycles. This result is acceptable as it represents a minimum of cycles and the loading conditions were really severe with ΔTj= 170K. The best case shows also quite good result, as with the lower warpage amplitude, more than 3 million of cycles can be reached under ΔTj=60K. The best fitting power trend line is plotted on the graphic with its equation and its R² value. The R² value reveals how closely the estimated values for the trend line correspond to the actual data. The trend line is reliable when its R² value is at or near 1. Here it appears that the curve fitting is not optimal as the R² value is quite far from 1.

This can be explained by the fact that what is taken as the number of cycles to failure is actually not exactly the number of cycles to failure but only the number of cycles until the End of Test (EoT). This generates imprecision in the lifetime prediction fitting function.

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Figure 7.1: N_f EoT cycles in function of the inverse of curvature radius amplitude

Then the prediction of the chip lifetime is plotted in function of the in-plane stress amplitude Figure 7.2. Here the trend line fits quite well the data as R²=0,6, thus the lifetime prediction function is quite reliable. In the best case, more than 3 million of cycles can be reached with an in-plane stress amplitude of 110MPa. In the worst case a stress amplitude of 410MPa leads to a lifetime superior to 62 000 cycles. As it is known from Bosch experience that no premature failure occurs in a chip submitted to 900 MPa of in-plane stress amplitude, the real lifetime should be significantly higher than what is predicted here.

Figure 7.2: N_f EoT cycles in function of the in-plane stress amplitude in the chip

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Figure 7.3: N_f EoT cycles in function of the out-of-plane stress amplitude in the chip

The lifetime of the chip is also predicted in function of the out-of-plane stress amplitude Figure 7.3. The data are quite scattered especially for the highest values of stress amplitude, thus the trend line is not very reliable.

Nevertheless, results appear to be quite good, as already more than 260 000 cycles are reached under ΔTj=120K for the highest stress amplitude of 60 MPa. As it is known from Bosch experience that no premature failure occurs in a chip submitted to 200 MPa of out-of-plane stress amplitude, the real lifetime should be significantly higher than what is predicted here.

Figure 7.4: N_f EoT cycles in function of the shear stress amplitude in the chip

Finally the Figure 7.4 presents the lifetime prediction of the chip in function of the shear stress amplitude. The trend line is moderately reliable. In the best case, with a stress amplitude of 30MPa the chip can pass minimum 2,3 million of cycles. In the worst case, a stress amplitude of 70MPa leads to a minimum lifetime

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of 62 000 cycles. This result is acceptable as it represents a minimum of cycles and the loading conditions were really severe with ΔTj=170K.

Concerning the crack growth at the interface chip/IMC, the lifetime is predicted in function of both GI and GII

amplitudes

Figure 7.5). For both GI and GII, theirtrend lines are only moderately reliable. Then it appears clearly on the graphic that the values reached for GI amplitude are lower than the ones reached for GII. For the mode I, in the best case, a GI amplitude of 0,0011mJ/mm² leads to a lifetime superior to 2,3 million of cycles. In the worst case, a GI amplitude of 0,005mJ/mm² induces a minimum lifetime of 220 000 cycles. These results are describing a very reliable module, as the worst case located on the trend line and happening with a GI

amplitude of 0,005mJ/mm² reached underΔTj=120K has a minimum lifetime already well above 100 000 cycles.

Regarding results for the mode II, values of GII amplitudes are more spread out than the ones obtained for GI. In the best case, a GII amplitude of 0,004mJ/mm² induces a lifetime superior to 2,3 million of cycles. In the worst case, a GII amplitude of 0,034mJ/mm², induces a minimum lifetime of 220 000 cycles. Here also results are really good, as the worst case close to the trend line and happening with a GII amplitude of 0,034mJ/mm² reached underΔTj=120K has a minimum lifetime already well above 100 000 cycles.

Figure 7.5: N_f EoT cycles in function of G_I and G_II amplitude for the crack at the interface chip/IMC