The results obtained for different cracks under PTC and APC are shown, as well as the results of a sensitivity study. 1 State-of-the-art reliability of power modules under active power cycling (APC).
Power electronics
MOSFET and IGBT semiconductors
As the potential difference increases, the free charges in the semiconductor are pushed away from the semiconductor/oxide junction, first creating a zone known as "depletion", and when the potential difference is large enough, a region of "inversion". This inversion zone is an area where the type of charge carriers is opposite to the rest of the substrate, creating a "channel" for conduction.
Power module design
The bottom side of the chip is soldered to the top DCB copper metallization. Ceramics provide electrical insulation and dissipation of the heat flow generated by the chip.
Working conditions
Failure mechanisms
- Bond wire fatigue
- Aluminum reconstruction and ratcheting
- Solder voids and solder fatigue
- Delamination at the interface Mold/Copper
- Chip cracking
The reconstruction of the Al metallization was found in the early years of microelectronics [San69], but only recently began to be studied [Mal95, Cia96]. This ratcheting mechanism occurs due to the CTE mismatch between the Si (2.4 ppm/K) and the cast compound (~11 ppm/K).
Technological improvements
- Joining layers
- Interconnects
- Dual side cooling
- Combination of improved technologies
- SiC
Diffusion of Cu into the semiconductor device can interfere with the electrical function of the device. At the same time, the sintering technology is also used to replace the soldering of the connection between the die and the DCB substrate.
State of the art in Active Power Cycling (APC) reliability
- Active Power Cycling (APC)
- The LESIT and RAPSDRA project on APC reliability
- A variety of test methods
- Review of papers on APC tests
Microscope (OM) and scanning electron microscope (SEM) were used to analyze 17% of the samples. Chip metallization on top of the chip is also commonly seen (18%), as well as DCB mounting (15%).
State of the art in Active Power Cycling (APC) simulation
Methods to simulate APC
This can be partly explained by the fact that testing a large number of cycles requires long test times on the order of several months. The mechanical analysis then produced a deformation map of the module from which stresses and strains were derived.
Review of papers on FEM simulations of APC
Determining the influence of temperature on the number of cycles to failure was also an important point. The number of cycles to failure obtained with simulation was plotted as a function of the temperature variation ATj, figure 1.54.
Conclusion
In simulations, as in experiments, the study of the effect of heating time on moduli under APC is neglected. But it is necessary to take advantage of the simulation and intensively study the influence of different combinations of parameters on the mechanical behavior of the modules.
Description of the module and its internal structure
The solder joint used in the power module to connect the clamp to the chip, but also the chip to the Cu lead frame, is a lead-free, tin-silver-copper solder and is called SAC 305 for Sn96.5Ag3Cu0.5. With soldering, some intermetallics are formed at both interfaces of the solder layer: Cu6Sn5 or Cu3Sn intermetallics are formed near the copper layers, while (Cu,Ni)6Sn5 or Ni3Sn4 intermetallics are formed near the chip.
The assembly process of the module
This post-curing process involves exposing the module to elevated temperatures to speed up the curing process and enhance some of the material's physical properties. A higher stress-free temperature is specified for the mold to account for residual stresses due to mold hardening.
Thermal and mechanical properties of materials
- The copper lead frame and clip
- The solder
- The silicon chip
- The aluminum metallization
- The intermetallics (IMC)
- The molding compound
The yield stress as a function of the thickness of the layer was plotted Figure 2.7 for all literature data: Yield stress values for an Al film 1 µm thick are widespread and range from 20 MPa to 470 MPa. Here, the yield stress varies from 50 MPa to 230 MPa, but the slopes of the different curves are often comparable.
Measurement and simulation of thermal impedance
Definition and application of the thermal impedance
Therefore, a thermal study was performed and the thermal impedance of the module was characterized. Zth B6 was simulated in 1D with the thermal RC model shown in Figure 3.7 and compared with measurement.
Detailed thermal study of the module
The Cu clip and bottom solder are at 98% and 94% of the chip's temperature, respectively. The temperature of the bottom solder and the Cu lead frame are now closer to that of the chip.
Definition of the Design of Experiment
The Cu lead frame in direct contact with the heatsink reached only 88% of the chip's temperature. The largest temperature rise occurs in the die, as it has 94% of the chip's temperature.
Experimental method
Active Power Cycling (APC) tests
This type of test is quite easy to perform and the induced thermo-mechanical failure mechanisms have already been extensively studied and are fairly well understood. Thus, in these tests, the temperature fluctuation comes from the environment and the temperature in the device is quasi-homogeneous.
Failure detection methods
In Figure 4.7, the drain leakage curve of IDSleak has an exponential shape due to its conduction properties, and the gate leakage curve of IGSleak can be explained by the tunnel effect for VGS ≤ -20V and VGS ≥ 20V, while the rest is noise. Then, one or two sections were cut in the module in the degraded area, which are observed under an optical microscope and a reflection electron microscope (REM) (Figure 4.11).
Failure mechanisms observed after Active Power Cycling
- Failure mechanisms in the entire module
- Failure mechanisms in the bottom solder
- Failure mechanisms in the Al metallization
- Failure mechanisms in the top solder
- Failure mechanisms in the mold
An increase in RDSon indicates degradations in the Al metallization but may also be a sign of degradations in the top weld. A slight increase in the thermal resistance Zth at the beginning of the measurement was reported as an indication of degradation in the Al metallization, but it could also be a high degradation of the weld.
Lifetime prediction
First evaluation of lifetime prediction
Finally, the influence of the tone pulse width on the lifetime of the device is shown in Figure 4.36. Finally, Figure 4.39 shows that the results of bridge B6 follow the same trend as those from the literature.
Correlation between ageing indicators
Results are quite scattered, so the correlation between the increase in Vf and RDSon is not really good. Despite the poor quality of the correlation between the increase in RDSon and Vf, this one will still be used to define a new EoL criterion.
Improved lifetime prediction
But this already gives an idea of the life gain with the new EoL criterion. The lifetime gain is not negligible, as changing the EoL criterion from a 1% increase in Vf to a 3% increase already doubles the module lifetime prediction.
Passive Temperature Cycling (PTC)
Loading conditions for PTC
After the 2D model was validated, the behavior of the module under PTC was analyzed in detail based on the 2D simulation results. Then, the APC was simulated with a 2D model and the results were analyzed in detail and discussed in comparison with the results obtained for the PTC.
Comparison 2D/3D: validation of the 2D model
Here the cross section passes through the upper solder meniscus and ends at the corner of the chip. The curve of the 2D model is included between both curves of the cross section through the chip diagonal.
Detailed module behavior under PTC
The warp corresponds to the deformation in the out-of-plane direction along the path in the chip. As shown in Figure 5.15, the critical zone for creep deformation is located at the end of the bottom solder, in the meniscus region and close to the chip.
Active Power Cycling (APC)
Loading conditions for APC
At low temperature, the von Mises stress reaches 230 MPa and is constant along the first half of the layer near the symmetry axis. At high temperature, the von Mises stress reaches 84 MPa and is constant almost along the entire path.
Detailed module behavior under APC
Finally, the evolution of temperature, von Mises stress and acc creep strain in one cycle in the critical region of the lower solder is shown in Figure 5.35. For the rest of the path, the out-of-plane voltage is close to zero, regardless of temperature.
Sensitivity study
The acc creep voltage in the top solder close to the chip is plotted for different sets of parameters in Figure 5.51. The acc creep stress in the top solder close to the clip is plotted for different sets of parameters in Figure 5.52.
Extension of the sensitivity study
The acc creep strain in the bottom solder as a function of tons is plotted in Figure 5.55. All crack configurations lead to an increase in the acceleration creep stress in the bottom solder.
Fracture mechanics model
- Selection of failure mechanisms
- Selection of fracture criteria
- Definition of fracture criteria
- Validation of the fracture criterions implementation
Here, the fracture toughness is known neither for the crack in the top IMC nor for the delamination at the interface chip/bottom IMC. The CTOD analysis takes place at a few nodes at a fixed distance in front of the crack tip as shown in figure 6.4.
Crack growth under PTC
Crack growth at the interface chip/IMC
Since this type of crack has never been observed, it can be concluded that GI=0.012 mJ/mm2 and GII=0.04mJ/mm2 are not critical values for crack growth under PTC even if the fracture toughness is not known. But again this is not certain as no values of fracture toughness are known for this case.
Crack growth in the Al metallization
In this case, the layer above the crack is always shifted to the left compared to the layer below. According to the definition of the CTOD criterion, this means that crack growth will occur along a local mode II direction.
Crack growth in the top IMC
Crack growth under APC
Crack growth at the interface chip/IMC
GI, it can be concluded that the crack can preferentially propagate through local mode II. Then, since the values of G obtained for mode II are higher than for mode I, it can be concluded that the crack can possibly propagate through the local mode II.
Crack growth in the Al metallization
Thus, the absolute maximum value of the CTOD component at the new crack tip is obtained by the shear component, and thus crack growth will occur along a local mode II direction. Only a slightly larger amplitude is observed for the shear mode under APC than under PTC.
Crack growth at the top IMC
At the very beginning of the heating phase, the crack closes to its original closed position, and then some small shear displacements occur. Finally, the cracking behavior under PTC and APC is very similar and the values obtained for both G components are comparable.
Sensitivity study on cracks growth
Crack growth at the interface chip/IMC
So PTC is more critical for the crack growth in the shear direction at the interface chip/IMC than APC. Based on experiments, it is inferred that the crack growth remains subcritical, as no such crack was observed during APC.
Crack growth in the Al metallization
This means that for those drawers the layer above the crack moves to the right compared to the layer below the crack. And according to the definition of the CTOD criterion, the crack growth will occur along a local mode II direction for all cases of the sensitivity study.
Crack growth in the top IMC
When comparing histograms of GI and GII components, it is noticeable that the same set of test parameters is crucial in terms of amplitudes, namely: low Tjmin with large ΔTj and long tons. The notable difference between the two modes is that the shear mode is clearly dominant (values of GII are approximately 100 times higher than values of GI) for all load cases of the sensitivity study.
Failure mechanisms under APC
During PTC, the degradation of the bottom solder is actually the main failure mechanism, and the degradation of the Al metallization appears as another failure mechanism. The fact that the degradation of the Al metallization is the main failure mechanism during APC has performed the EoL criterion to be based on the RDSon increase.
Influence of test parameters
It can be deduced from experimental results that the degradation of the Al metallization is the main failure mechanism that occurs in the module under APC and leads to the device failure. The same information therefore comes from the study of these three output parameters, which means that the study of crack growth in the IMC may have been spared.
Lifetime models
Chip behavior
The lifetime of the chip is also predicted as a function of the out-of-plane voltage amplitude. Figure 7.3. Finally, Figure 7.4 shows the chip lifetime prediction as a function of shear stress amplitude.
Bottom solder behavior
For mode I, at best, a GI amplitude of 0.0011 mJ/mm2 leads to a lifetime greater than 2.3 million cycles. Thus, this 0.08% acc creep strain may set a critical limit for the life of the bottom solder.
Top solder behavior
Al metallization behavior
Therefore, to have a lifetime equal to or greater than 500,000 cycles, the amplitude of CTODII must remain equal to or less than 0.14 µm. This 0.14 µm amplitude of CTODII could thus define a critical limit for the lifetime of Al metallization.
IMC behavior
Xu, "Power Cycling Reliability of IGBT Power Modules", IEEE Annual Meeting of Industry Applications Society, (1997), s. Herr "A Novel Power Module Design and Technology for Improved Power Cycling Capability", Microelectronics Reliability, Vol.
