In the previous five Sections we have covered the entire domain of reliability modeling and mitigation, with specific emphasis on parametric violations (which represent the target domain of time-dependent variability). Apart from creating
the classification frameworks, we have mapped prior art samples to the leaves of the former, so that the validity of our classification is completely substantiated.
In the current Section, we will reflect on the mapping of this text’s next Chapters to the classification frameworks mentioned above. Detailed and specialized prior art listings appear in each of the following technical Chapters. Here, we incorporate the technical contributions of the current text in the overall valley of reliability analysis, modeling and mitigation solutions. Schematically, the correspondence of technical Chapters of this text to the leaves of the framework presented above are shown in Figures 2.1 and 2.2, respectively.
Chapter 3: This Chapter deals with the modeling of BTI and RTN. The focus of this part of the text is the compression of signal activity, in order to enalbe reliability predicitions across extended time intervals (e.g. throughout the circuit lifetime). This modeling Chapter deals with the HW utilization at the level of circuit and especially at the level of the voltage waveform that is applied to the transistor gate. As a result, we classify Chapter 3 to theIV Activity branch of Figure 2.1. The novelty of this Chapter lies on the systematic compression. It will be demonstrated that, in comparison to previous approaches, thre CDW succeeds in balancing the accuracy vs. computation time in circuit aging analysis. The core of the work presented in Chapter 3 has been previously disclosed by the author in an IEEE TDMR journal paper [234].
Chapter 4: The MPFP methodology is used in this Chapter in order to deliver time-dependent failure probabilities for SRAM components. The target siliocn aging phenomena are, again, BTI and RTN. A partial recovery component has long been identified for these phenomena (corresponding to the emission of minority carriers in the gate stack) [119]. As a result, it is valid to classify this Chapter under the leafPartially Reversible of Figure 2.1. This Chapter is based on the well known MPFP and proposes extensions for circuits other than memory cells. It also discusses paths of digital standard cells. The core of the work presented in Chapter 4 has been previously disclosed by the author in two workshops [233, 232].
Chapter 5: This Chapter deals with the implementation of a functional mitigation technique (fine-grain rollbacks) and the performance implications thereof.
Static DVFS boosts are proposed to enable performance dependability of the experimental setup. Even though this is clearly a mitigation technique, it is verified with extensive reliability analysis campaigns. Given the scope and implementation of the concepts discussed in this Chapter, we can classify it, from a reliability analysis perspective, under leafInjector Module in Figure 2.1. From a mitigation perspective the proposed technique is
CRITICAL APPRECIATION AND CONTRIBUTIONS 33
clearlyReactive, hence it is classified accordingly in Figure 2.2. The core of the work presented in Chapter 5 has been previously disclosed by the author in an IEEE TVLSI journal paper [230].
Chapter 6: This Chapter deals with the formulation and generalization of the mitigation technique presented in Chapter 5. As such if falls under the same classificaton leaves as discussed above. The main novelty featured in this Chapter is the casting of the performance vulnerability problem from cycles [138, 102] to time units. This is a much required translation of the problem, since it connects RAS temporal overheads with the overall quality of service provided by a processor. Additionally, the DVFS capabilities that appear in abundance in modern processors are appropriately exploited in the concept presented herein. The formulation and reductions to practice presented in this Chapter have been previously disclosed by the author in one IEEE journal paper and an ACM journal submission [226, 229].
Chapter 3
Compact Digital Waveform for Circuit Aging Modeling
This Chapter discusses the usability of a novel signal representation format for efficient modeling of integrated circuit aging. Especially at aggressively downscaled nodes, semiconductor aging phenomena are getting increasingly complex to predict. In the Chapter, a case is made for Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN). We start from some general background on BTI and RTN and discuss the most prevalent samples of prior art on this domain (Section 3.1) and also focus on the inner workings of atomistic aging models. Then, we present the Compact Digital Waveform (CDW) and discuss its applicability for BTI/RTN modeling (Section 3.3). An extensive verification of this signal representation format is performed in Section 3.4. The CDW’s applicability in terms of bias- and temperature-awareness is discussed in Section 3.5. Finally, the compatibility to standard design flows is discussed in Section 3.6. We need to note that the largest part of the current Chapter has been already disclosed in a previous publication [234].
3.1 Background
Bias Temperature Instability (BTI) has been examined for more than 30 years [115] as a major concern for integrated circuit (IC) reliability. It causes the absolute threshold voltage (𝑉𝑡ℎ) increase under certain bias and temperature conditions. Typical simulation involves a degradation model assigning𝑉𝑡ℎshifts to each transistor and timing analysis employed to reveal timing fluctuations.
35
The Reaction-Diffusion (RD) model for BTI has triggered prior art in both modeling [12, 201, 276, 243, 168] and mitigation [147, 43, 146, 201, 33]. This model emphasizes on the breaking and annealing of Si-H bonds at the Si/oxide interface and mainly focuses on pFETs (NBTI). As a pFET is stressed, the model argues that minority carriers (holes) are replacing H atoms in Si-H bonds at the Si/oxide interface, thus causing a shift to the pFET’s threshold votlage (𝑉𝑡ℎ). Once the stress is removed from the pFET’s gate (off state), a subset of the Si-H bonds is annealed, thus partially restoring𝑉𝑡ℎshifts [49]. However, the RD model has been shown to deviate from experimental data at aggressively downscaled technologies. Thus, it is motivated to adapt circuit simulation to the deca-nanometer technology paradigm [94].
Atomistic approaches do move to this direction, additionally capturing the effects of Random Telegraph Noise (RTN) in the same model. Certain transient implementations of the atomistic model [228, 120, 41] are very accurate but are very processing- and memory-intensive, which sometimes causes them to fail.
Hence, their computational feasibilitycannot be guaranteed.
What makes atomistic approaches different is that, instead of having an analytical formula that predicts average aging, such models account for matter discretization in a more detailed manner: Each defect in the gate stack is independently modeled, with its𝑉𝑡ℎimpact (Δ𝑉𝑡ℎ) and time constants for the capture and emission of minority carriers. When a minority carrier is captured by a defect, then the appropriate Δ𝑉𝑡ℎis superimposed to the transistor’s𝑉𝑡ℎ. Even though extremely accurate, this technique is very time-consuming given that different transistors have different numbers of different defects. This difference between average RD and atomistic models for BTI is clarified schematically in Figure 3.1.
It is worth noting that, since the initial papers [120, 228] and patent disclosures [41] on atomistic BTI/RTN modeling, an attempt to scale the complexity of this task has been made by embedding the atomistic model’s code within the source of code of an open source SPICE implementation and scaling it with a hypervisor [161]. This technique succeeded in removing the memory wall of time-driven, atomistic BTI/RTN simulation, especially in comparison to commercial SPICE solvers [228].
In any case, in order to perform atomistic simulations for the entire lifetime of a typical integrated circuit, it is very important to enable strides over circuit workload. This is exactly the direction of the current Chapter and of the general concept of the Compact Digital Waveform (CDW).
One of the attributes that became rather apparent since the first SPICE- compatible atomistic modeling papers [120, 228] is that such models succeed in
BACKGROUND 37
p n
n
Si-H bonds break and H diffuses up the date stack Stress removed; Annealing of Si-H bonds
NB: Extra development required to add time-zero/-
dependent variability ΔVth(total)=f (tstressα
) Power Law for Total Vth Shift
stress relaxation
(a)
(b) Note: As disclosed in previous work [228]
Figure 3.1: Artist’s illustration of the differences between the average RD model and the sought-after atomistic modeling schemes for BTI/RTN
maintainingboth the stochastic nature of minority carrier capture and emission andthe workload dependent attribute of this phenomenon. These are two aspects of gate stack defect interference which should remain coupled for the BTI/RTN study to be accurate. The former component is rather trivial, in the sense that the capture and emission of minority carriers are quantum-mechanically described, hence absolutely deterministic modeling of these mechanisms is out of the question. However, there is a strongworkload dependency in BTI/RTN, in the sense that certain𝑉𝑔𝑠signals at the transistor gate favor certain degradation patterns. The combination of these two attributes has been substantiated in the lower levels of the circuit abstraction for simple memory simulations [228]. One of the fundamental goals of this Chapter is to retain the combined stochastic and workload dependent model for BTI/RTN, while reducing its computational complexity.