This section summarizes theses presented in the dissertation. The main theme of the dissertation was improving software switch performance by improving its data-flow-graph batch-scheduling and embedding. Below we present the three main contributions and its sub-results.
The first thesis presents a model to describe data-flow-graph batch-scheduling in software switches. The model enables to formulate the optimal data-flow-graph batch- scheduling. An interesting equivalency is highlighted between weighted-fair queuing and run-to-completion scheduling modes under assumptions from Section 2.3.2. Chapter 2 and [C2] presents this work.
Thesis 1. [C2]I have designed a comprehensive analytical model for batch-scheduling in packet processing pipelines under delay constraints. The model covers run-to-completion and WFQ (weighted-fair queuing) scheduling mode. I formulated the problem in a novel analytical model and I gave an algorithm to the optimal batch-schedule for WFQ and run-to-completion mode. Furthermore, I have shown a deep equivalence between run-to-completion and WFQ scheduling under assumptions A1, A2, A3 and A4.
The first result quantifies network functions processing costs in software switches with thebatchinessmetricβ. Details and calculation ofβ is shown in Section 2.3.1.
Thesis 1.1. [C2]By extensive measurements on real-life packet processing engines, I have shown that batch processing time of common-case primitive packet processing functions exhibit a linear dependence on the number of packets in each batch.
The second result is a comprehensive system model for data flow graphs. Description of the model is in Section 2.3.2.
Thesis 1.2. [C2]I have designed a system model to describe batch processing packet pro- cessing pipelines. I have modeled packet processing primitives as a combination of an ingress queue and a network function at the egress connected back-to-back. The model covers all types of packet processing primitives that do buffering, processing or splitting.
The model (Thesis 1.2) and the network function processing cost quantification (The- sis 1.1) enables formulating the optimal data-flow-graph batch-scheduling. A formulation for weighted-fair queuing (WFQ) is given in Thesis 1.3 and for run-to-completion (RTC) in Thesis 1.4. Formulation and detailed proof is given for WFQ in Section 2.3.3, and for RTC in Section 2.3.4.
Thesis 1.3. [C2]I have shown that the optimal WFQ (weighted-fair queuing) data-flow- graph batch-scheduling is unique and it can be obtained in polynomial time.
Proof. The mathematical program is convex.
Observation. We can redefine assumptionA3Feasibilityusing the formulated program.
Feasibility stands, if there is at least one feasible solution for the mathematical program.
Thesis 1.4. [C2]I have shown that the optimal run-to-completion data-flow-graph batch- scheduling is unique and it can be obtained in polynomial time.
Proof. The mathematical program is convex.
A compelling finding of ours is that any feasible data-flow-graph batch-scheduling of WFQ and RTC can be interchanged by a simple conversion in our model. Section 2.3.5 details and provides a proof of this equivalence.
Thesis 1.5. [C2]I have shown that, under assumptions A1, A2, A3, and A4, any system state feasible under the WFQ scheduling model is also attainable with a run-to-completion schedule.
The second main contribution of this dissertation relaxes the assumptions of the model from Thesis 1.2 and introduces a controller framework to implement optimal data-flow- graph batch-scheduling on real software switches. Results are detailed in Chapter 3 and are published in [C2].
Thesis 2. [C2]I have designed a one-step receding horizon optimal controller to implement the optimal batch-schedule under delay constraints in the run-to-completion model and I deployed the controller in a real-life packet processing engine. My design includes two heuristic algorithms to adaptively compute the optimal queuing; a simplified gradient optimization algorithm that is shown to be optimal in steady state, and a much simplified on-off control algorithm which does not require fractional buffer. I improved the performance of these control algorithms by introducing a heuristic to adaptively insert/remove buffers. My implementation also contains a feasibility-recovery algorithm and a pipeline decomposition heuristics that operate on different timescales to recover the pipeline from a state when delay constraints are temporarily violated.
The controller framework takes inspiration from Nagle’s algorithm [60]. This requires fine-grained control over queue backlogs. For this purpose, The first result is thefractional buffer, a queuing abstraction (Thesis 2.1). Details are shown in Section 3.3.1.
Thesis 2.1. [C2]I have introduced the fractional buffer queuing abstraction, which enables to control the size of the batches a packet processing function receives at a fine grain.
The receding horizon controller is introduced in Section 3.3.2. The first control algo- rithm of the controller is a projected gradient control algorithm, presented in Section 3.3.3.
Thesis 2.2. [C2]I designed a gradient optimization algorithm to tune fractional buffer sizes.
I have shown that this control algorithm attains the optimal batch-schedule in steady state.
Thesis 2.3 presents an effective heuristics to improve performance of the controller.
Details in Section 3.3.4.
Thesis 2.3. [C2]I have designed an algorithm to adaptively remove buffers from the input of specific modules if (1) if it already receives large enough batches at the input, (2) if it would further fragment batches instead of reconstructing them, or (3) introducing the buffer already violates the delay-SLO.
The controller contains a heuristic to recover the control algorithm from an infeasible (SLO-violating) state at each control cycle. Section 3.4.1 shows the details.
Thesis 2.4. [C2]I have developed a feasibility recovery algorithm to bring the controller back to the feasible region.
Poor resource allocation can result an infeasible state for the controller in which it is unable to set triggers to conform with delay-SLOs. A feasibility-recovery mechanism to fix the delay-SLO violation caused by poor resource allocation is introduced in Section 3.4.2.
Thesis 2.5. [C2] I have developed a pipeline decomposition method to reallocate CPU resources across different flows by decomposing the pipeline to multiple disjunct connected worker subgraphs.
The fractional buffer is not available for most software switches yet. To make the controller work with simple queue or buffer implementations available in software switches, an on-off control algorithm is presented in Section 3.5.1.
Thesis 2.6. [C2]I have designed and implemented an on-off control algorithm which switches between two extreme control actions based on the delay-SLOs: it either inserts a full batch-size buffer at the input of each module or removes queuing all together. The on-off controller does not require a fractional buffer.
The controller framework is implemented on BESS [22]. Implementation details are shown in Section 3.5.2. Extensive evaluation of the controller over real use cases is presented in Section 3.5.3.
Thesis 2.7. [C2]In comprehensive evaluations on 6 real-life reference scenarios I have shown that my optimal batch-scheduling controller implementation provides up to2–3×
performance improvement while closely conforming to SLO requirements. In addition, I gave a comprehensive experimental evaluation of the operational regime where the controller provides the highest performance improvement.
As Thesis 2.5 highlights, a poor resource allocation limits performance of software switches. Chapter 4 and [C3] focuses on solving resource allocation issues by focusing on data-flow-graph embedding (i.e.,the act of assigning modules to CP U cores) to provide feasibility, efficiency, and resiliency.
Thesis 3. [C3]I have designed a novel, comprehensive analytical model for packet processing pipeline resource allocation (embedding). I have designed a method to protect high-availability data flow graph flows against CPU errors. I have formulated the embedding problem as an Integer Linear Program to find an optimal solution, and gave heuristic algorithms to obtain feasible solutions in polynomial time.
The first sub-result is a comprehensive model for data-flow-graph embedding presented in Section 4.1.
Thesis 3.1. [C3]I have designed a model to express the resilience requirements on data flow graph flows. The model enables marking high-availability flows which requires resilience against CPU errors. Additionally, I have designed a method to protect the high-availability flows against CPU errors.
The efficient embedding without resilience requirements is NP-hard and can be reducted tominimum bin-packing[94]. Hence the problem is NP-complete (Thesis 3.2). The problem remains NP-complete with resilience constraints (Thesis 3.3). Problem formulation and proof is presented in Section 4.3.1.
Thesis 3.2. [C3]I have shown that both MinSumEmbed and MinMaxEmbed are NP-complete.
Thesis 3.3. [C3]I have shown that both ResMinSumEmbed and ResMinMaxEmbed are NP-complete.
An exact algorithm is given in Section 4.3.2 to obtain optimal solution for the embedding problems.
Thesis 3.4. [C3]I have formulated the feasible embedding and resilient embedding as decision problems. I have shown optimal solution can be found with exponential time complexity.
Heuristic algorithms find embedding solution in polynomial time. The heuristics are presented in Section 4.3.3. The algorithms are evaluated numerically in Section 4.3.4, and in a case study in Section 4.3.5.
Thesis 3.5. [C3]I have developed a family of fast and effective heuristics for finding feasible embedding and resilient embedding in polynomial time. I have conducted extensive numerical evaluation and a real-life case study, and showed that the best-fit heuristic provides the best approximation of the optimal embedding in real-life applications.
International Journals
[ J1] Tamás Lévaiand Gábor Rétvári,“Batch-scheduling Data Flow Graphs with Service- level Objectives on Multicore Systems”, Infocommunications Journal, 2022. (Accepted) [ J2] Tamás Lévai, Gergely Pongrácz, Péter Megyesi, Péter Vörös, Sándor Laki, Feli- cián Németh, and Gábor Rétvári,“The Price for Programmability in the Software Data Plane: The Vendor Perspective”, IEEE Journal on Selected Areas in Communications, vol. 36, pp. 2621–2630, 2018.
[ J3] Tamás Lévai, István Pelle, Felicián Németh, and András Gulyás, “EPOXIDE: A Modular Prototype for SDN Troubleshooting”, ACM SIGCOMM COMP UTER COM- MUNICATION REVIEW, vol. 45, no. 4, pp. 359–360, 2015.
International Conferences
[C1] Jane Yen, Tamás Lévai, Qinyuan Ye, Xiang Ren, Ramesh Govindan, and Barath Raghavan,“Semi-Automated Protocol Disambiguation and Code Generation”, ACM SIGCOMM 2021, 2021
[C2] Tamás Lévai, Felicián Németh, Barath Raghavan, and Gábor Rétvári,“Batchy: Batch- scheduling Data Flow Graphs with Service-level Objectives”, 17th USENIX Symposium on Networked Systems Design and Implementation (NSDI 20), 2020.
[C3] Tamás Lévai and Gábor Rétvári, “Resilient Dataflow Graph Embedding for Pro- grammable Software Switches”, 11th International Workshop on Resilient Networks Design and Modeling (RNDM), 2019.
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[C4] István Pelle,Tamás Lévai, Felicián Németh, and András Gulyás,“One tool to rule them all: a modular troubleshooting framework for SDN (and other) networks”, 1st ACM SIGCOMM Symposium on Software Defined Networking Research (SOSR), 2015.
[C5] Tamás Lévai,“Cost-effective Network Emulation using Cloud Infrastructure”, 20th International Scientific Student Conference POSTER 2016, 2016.
[C6] Tamás Lévai and Felicián Németh, “Distributed Network Emulation over Cloud Infrastructure”, Mesterpróba 2016, pp. 57–60.
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