Arquiteturas de Computadores

(1)

Arquiteturas de Computadores

Implementação de MIPS multiciclo (cont.)

Arquiteturas de Computadores

Fontes dos slides: Patterson &

Hennessy book website

(copyright Morgan Kaufmann)

e Dr. Sumanta Guha

(2)

Caminho de dados com controle I

Shift left 2

MemtoReg IorD MemRead MemWrite

PC

Memory MemData Write

data M

u x 0

1

Registers Write register Write data

Read data 1 Read data 2 Read

register 1 Read register 2

Instruction [15– 11]

M u x 0

1 M

u x 0

1

4

ALUOp ALUSrcB RegDst RegWrite

Sign extend

32 16

Instruction register

1 Mu x 0

3 2

ALU control M

u x 0

1

ALU result ALU ALUSrcA

A Zero

B

ALUOut IRWrite

Address

Memory data register

…somente linhas de controle e da ALU mostradas

(3)

Caminho de dados com controle II

Caminho de dados para MIPS multiciclo

Shift left 2 PC

M u x 0

1

Registers Write register Write data

Read data 1

Read data 2 Read

register 1 Read register 2

M u x 0

1

M u x 0

1

4

Sign extend

32 16

Instruction register

ALU control

ALU result ALU

Zero

Memory data register

A

B IorD

MemRead MemWrite MemtoReg

PCWriteCond PCWrite

IRWrite

ALUOp ALUSrcB

ALUSrcA

RegDst PCSource

RegWrite Control

Outputs

Op [5– 0]

Instruction [31-26]

M u x 0

2 Jump

address [31-0]

Instruction [25– 0] 26 28

Shift left 2

PC [31-28]

1

1 Mu x 0

3 2

M u x 0

1

ALUOut Memory

MemData

Write data Address

New multiplexor

New gates For the jump address

(4)

Passo 1 para busca de instrução

IR = Memory[PC];

PC = PC + 4;

1

0

1

0 1 X 0

0 X

0 010

1

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

ALUSrcA jmpaddr

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

MemtoReg IorD

PCWr*

IRWrite

(5)

Passo 2 para decodificação e busca no registrador

A = Reg[IR[25-21]]; (A = Reg[rs]) B = Reg[IR[20-15]]; (B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2);

0 0

X 0

0 X

3 X 0

X 010

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(6)

0 X

Passo 3 para referência à memória

ALUOut = A + sign-extend(IR[15-0]);

X

2 0

0 X 0 1

X 010

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(7)

Passo 3 para instruções R com acesso à ALU

ALUOut = A op B;

0 X

X

0 0

0 X 0 1

X

???

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(8)

1 if Zero=1

Passo 3 para instruções de desvio

if (A == B) PC = ALUOut;

0 X

X

0 0

X 0 1

1 011

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(9)

Passo 3 para instruções de salto

PC = PC[21-28] concat (IR[25-0] << 2);

0 X

X

X 0

1 X 0 X

2 XXX

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(10)

Passo 4 com acesso de leitura à memória ( lw )

MDR = Memory[ALUOut];

0 X

X

X 1

0 1 0 X

X XXX

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(11)

Passo 4 com acesso de escrita à memória (sw)

Memory[ALUOut] = B;

0 X

X

X 0

0 1 1 X

X XXX

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

1 0

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(12)

0 1 0

X 0

XXX

X X

1

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

0 1

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

Passo 4 com acesso à ALU (tipo R)

Reg[IR[15:11]] = ALUOut; (Reg[Rd] =

ALUOut)

(13)

Passo 5 com finalização de leitura de memória (tipo R)(lw)

Reg[IR[20-16]] = MDR;

1 0

0 X 0

0 X 0 X

X XXX

0

5 5

RD1

RD2 RN1 RN2 WN

WD

RegWrite

Registers

Operation

ALU

3

E X T N

16 32

Zero RD

WD

MemRead

Memory

ADDR

MemWrite

5 Instruction I

32

ALUSrcB

<<2 PC

4 RegDst 5

I R

M D R

M U X

0 1 2 3

M U X

0 1

M U X

0

A 1

B

ALU OUT

0 1 2

M U X

<<2 ^CONCAT

28 32

M U X

0 1

I[25:0]

rd

MUX

0 1

rt rs

immediate

PCSource

PCWr*

IRWrite

(14)



Quantos ciclos serão utilizados pelo programa abaixo?

lw $t2, 0($t3) lw $t3, 4($t3)

beq $t2, $t3, Label #assume not equal add $t5, $t2, $t3

sw $t5, 8($t3) Label: ...



O que acontece no oitavo ciclo?



Em que ciclo o conteúdo de $t2 é somado ao de $t3 ?

Perguntas

(15)



Os valores dos sinais de controle dependem:



Qual instrução está sendo executada



Qual passo está sendo executado



Deve-se especificar uma máquina de estados utilizando



gráficos, ou



Microprogramação



A implementação é derivada da especificação

Implementando o controle

(16)

 Máquinas de estado finito (FSMs):



Um conjunto de estados e



Função de próximo estado, determinada pelo estado corrente e entrada



Função de saída, determinada pelo estado corrente e possivelmente entrada



Máquina de Moore– saída baseada somente no estado corrente

Máquinas de estado finito

Next-state function Current state

Clock

Output function

Next state

Outputs Inputs

(17)

Controle representado por FSM

Memory access instructions (Figure 5.38)

R-type instructions (Figure 5.39)

Branch instruction (Figure 5.40)

Jump instruction (Figure 5.41) Instruction fetch/decode and register fetch

(Figure 5.37) Start

ALUSrcA = 0 ALUSrcB = 11

ALUOp = 00 MemRead

ALUSrcA = 0 IorD = 0

IRWrite ALUSrcB = 01

ALUOp = 00 PCWrite PCSource = 00

Instruction fetch Instruction decode/

Register fetch

(Op = 'LW') or (Op = 'SW') (Op = R-type)

(Op = 'BEQ')

(Op = 'JMP')

0

1

Start

Memory reference FSM

(Figure 5.38) R-type FSM (Figure 5.39)

Branch FSM (Figure 5.40)

Jump FSM (Figure 5.41)

Visão de alto nível

Os passos de busca e decodificação de instrução são idênticos para todas instruções

Sinais são mostrados

nos círculos

(18)

Referência à memória

MemWrite IorD = 1 MemRead

IorD = 1 ALUSrcA = 1 ALUSrcB = 10

ALUOp = 00

RegWrite MemtoReg = 1

RegDst = 0

Memory address computation (Op = 'LW') or (Op = 'SW')

Memory access

Write-back step (Op =

'SW ')

(Op = 'LW')

4 2

5 3

From state 1

To state 0 (Figure 5.37) Memory

access

Possui 4 estados

(19)

Instrução do tipo R

ALUOp = 10

RegDst = 1 RegWrite MemtoReg = 0

Execution

R-type completion 6

7

(Op = R-type) From state 1

To state 0 (Figure 5.37)

Possui 2 estados

(20)

Instrução de desvio

Branch completion 8

(Op = 'BEQ') From state 1

To state 0 (Figure 5.37) ALUSrcA = 1

ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01

Possui 1 estado

(21)

Instrução de salto

Jump completion 9

(Op = 'J') From state 1

To state 0 (Figure 5.37) PCWrite

PCSource = 10

Possui 1 estado

(22)

Controle FSM

PCWrite PCSource = 10 ALUSrcA = 1

ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 ALUSrcA =1

ALUSrcB = 00 ALUOp = 10

RegDst = 1 RegWrite MemtoReg = 0 MemWrite

IorD = 1 MemRead

IorD = 1 ALUSrcA = 1 ALUSrcB = 10

ALUOp = 00

RegDst = 0 RegWrite MemtoReg = 1

ALUOp = 00 MemRead

ALUSrcA = 0 IorD = 0

IRWrite ALUSrcB = 01

ALUOp = 00 PCWrite PCSource = 00

Instruction fetch Instruction decode/

register fetch

Jump completion Branch

completion Execution

Memory address computation

Memory access

Memory

access R-type completion

Write-back step

(Op = 'LW') or (Op = 'SW') (Op = R-type)

(Op = 'BEQ')

(Op = 'J')

(Op = 'SW

')

(Op = 'LW')

4

0

1

9 8

6 2

7 5

3

Start

Labels nos arcos são condições que determinam o próximo estado