Power Reduction in VLSI chips by Optimizing Switching Activity at Test Process, Architecture & Gate Level

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Power Reduction in VLSI chips by

Optimizing Switching Activity at Test

Process, Architecture & Gate Level

Chetan Sharma

(M.Tech-VLSI Design, JSS Academy of Technical Education, Noida, India)

Abstract: Due to increasing the demand of low power VLSI test process, it is necessary to consider all small factors which affect on total power dissipation. This paper gives the reduction of power by advancement in test pattern generation methods and gives the complete flow of data using switching suppression blocks at architecture and gate level.

Keywords: Don’t care bit feeling, ATPG method, Signal gating flow, Bus invert coding flow.

Introduction:

The power dissipation of any circuit depends upon switching activity as shown in following equation: P= α CV2f. ………..(1)

There are various techniques for reducing this switching activity at different levels of VLSI design at different level of design like

(1) For Architecture level: We use guarded evaluation at architecture level. In this case a latch circuit is used which checked the condition of input after that it decide that these input should be feed to original circuit or not. Thus switching activities are reduced at this level.

Fig (a): Switching activity reduction architecture level (2) For Gate level:

(a) Gate level signal gating technique is used for switching activity reduction. In this technique an extra hardware such as controller circuit is required. The main drawback at this level switching power reduction is that if controller need more power to operate their functionality then it becomes ineffective. So prior to use this technique power consumption by controller circuit is calculated and use as shown in following fig (b)

Multiplier

B

C

A

La

tc

condition

Chetan Sharma / International Journal of Engineering Science and Technology (IJEST)

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Fig (b): flow chart of signal gating

(b) Bus inverter encoding: The key idea behind this technique is to compare the bit streams of previous transmitted data & present data then we’ll decide that whether we have to send original data or invert foam of it, depending on minimum switching activity present either in original information or in invert foam.

Calculate power

consumption of

original circuit by

switching activity

Calculate power

consumption by

controlled circuit

Compare

either

controlled

circuit power

is less or not

Less

Don’t use

controller

More

Use

controller

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Fig (c): Flow chart of bus invert encoding

(3) Switching activity reduction in testing techniques:

There are various steps of frontend VLSI for making a good quality product. Firstly RTL is design by keeping into account the testing aspects for minimizing technical effort in test vector generation and producing low cost testing. It has few disadvantages like as increasing complexity of designing, increasing area and number of input pads. RTL is designed by taking into consideration the specification preapered by architecture team according to customer requirement. After it Test bench is designed by the same design engineer.

At the last frontend step, Test case is written which will initiate all test bench modules and provide test vectors for testing the RTL.

For the test vector anyone can use manual method of test pattern generation in which CAD tool can be used. According to functionality of gate, test vectors are generated in the manual method.

Except it another technique of test pattern generation is ATPG (Automatic Test Pattern Generation). A specified method is used for self generation of test vectors for testing the CUT (circuit under test).There are various method like as D Roth’s algorithm technique, Boolean difference method.

In the D Routh’s technique there are following three steps: (a) Fault activation: if stuck at 0 fault then set that particular node to 1 and vise-versa. (b): Path sensitization: propagation is done on faulty node to accessable output node. (c) Line justification: In this step back trace is done fro accessable output to accessable input nodes. By doing these three steps Test vectors are generated at all input nodes. In this method don’t care ‘x’ may come at the test vector.

Second ATPG method is by Boolean method. In this technique boolean relation between test vectors. It does’nt need to path sensitization like D routh’s method. For calculate test vector for the stuck at 0 fault at any node N (suppose). Then df/dN is calculated by Exclusive OR between output function f1 and output function f2. Output

function f1 is calculated by placing N=0 in original output f and Output function f2 is calculated by placing N=1

in original output f. Now nor stuck at 0 fault N is multiplied in df/dN.

Now value of primary inputs are calculated by comparing this function to logic value1.This technique may also have don’t care bit “x” at the test vector.

Present bit

stearm

transmitted bit

Compare switching

activity minimum

either in invert foam

or original foam

Switching

activity is

minimum in

invert foam

Data

transfer

by invert

foam

Data

transfer

in

original

foam

Yes

No

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This don’t care should replaced by particular defined bit. We can choose either 0 or 1.Normally it is seen that design engineer choose randomly this don’t care bit. But it should choose such that there will be minimum switching activity in the test vector because on reducing switching activity, desirable power reduction will produce.

For example test vector generated by automatic test pattern generation technique shown in fig(d). It has two X bits i.e. second bit and fifth bit.

Fig(d): Test vector generated by ATPG technique

Now on the place of X state, defined bit 0 or 1 is used according to previous and next bit of this don’t care bit. As shown in example second don’t care is replaced by bit 1 because there is no switching among first three bits of test vector. If we replace it by 0 then it’ll increase 2 switching activities. Finally affect the power. So by this method second bit is replaces as defined bit 1.

In the case of fifth bit generated by ATPG method. We’ll check only fourth bit because bit vector length is 5.As fourth bit is 0 so this don’t care should replaced by 0 for no switching activity involved in fourth and fifth bit position.

Fig(e): Modified test vectors for switching activity reduction

Conclusion:

In this paper power dissipation of testing process is decreased by minimizing switching activities of test vector. This test vector is generated by Automatic test pattern generation method. There is the requirement of define path for external circuit which is used to switching activity optimization as described in this paper.

References:

[1] P.Girard Survey of Low –Power Testing of VLSI Circuits: proceeding IEEE Design & Test -2002 pp.82-92

[2] N.Nicola and B.M.Al-Hashimi Power –Costrained Testing of VLSI Circuits: proceeding in Kluwer Academic Publishers-2003 [3] P.Girard, C. Landrault, S. Pravossoudovitch and D.Severac Reducing Power Consumption During Test Application by Test Vector

Ordering: proceeding in ISCAS-1998 pp.296-299

[4] R.Sankaralingam, R. Oruganti and N. Touba Static Compaction Techniques to Control Scan vector Power Dissipation Proceeding in IEEEVLSITestSymposium-2000

[5] K.A.Bhavsar Mehta, Analysis of Test Data Compression Techniques Emphazing Statistical Coding Schemes: proceeding in ACM Digital Library USA,2011

[6] Giacomotto C. and Oklobdzija V.G., "LogicStyle Comparison for Ultra Low PowerApplications,"Techcon (SemiconductorResearch Corp.), Oct. 2005.

[7] "Predictive Technology Model”, Websitecurrently available online at www.eas.asu.edu/~ptm.

Power Reduction in VLSI chips by Optimizing Switching Activity at Test Process, Architecture & Gate Level