Design & Implementation of Majority
Gates on FPGA & Comparison of Area
/Power Tradeoff
1
Rajeev Kumar
Assistant Professor, Deptt of ECE IITT College, Punjab rajeevpundir@hotmail.com
2Mandeep Singh Saini
Assistant Professor, Deptt of ECE IITT College, Punjab mandeepsinghsaini@yahoo.com
3
Poonam Chohan
Assistant Professor, Deptt of EIE chohan_poonam@yahoo.com
IITT College, Punjab
Abstract
Majority gates are the simple and fast logic to transfer the input to output. In this logic the number of bits which are maximum at input is transferred at the output. For example if we take the example of four bit binary number 0001 at the input that contains 3 zero’s in the binary number then this 0 is transferred at the output.
In the present paper we design the 4 input majority gate based on Low Power VLSI Design which provides low power consumption implemented on FPGA.After design the final architecture is synthesized on various FPGA Architectures & comparison is done based on area and power consumption. In the previous
papers implementation is done for 3bit majority logic. But in this particular paper the main focus is the implementation of 4bit majority logic on FPGA (Field Programmable Gate Array) used for design verification. From the available FPGA architectures design is implemented on the FPGA that provides the low chip area (lowest gate count) & low power consumption. So in the present architecture efforts are done to reduce the power and chip area. In the Digital IC design area, speed & power consumption are the parameters which are available for optimization. When an IC is designed the power is consumed to charge the parasitic capacitance of the interconnections. So by choosing the particular material this factor can be reduced by the significant amount decided by the process technology. So by choosing a particular FPGA package required for final implementation one can reduce the parasitic effects in the architecture design. The another method is the gate clocking in which the output of the AND gate is connected with the clock input inside the architecture design.
Keywords
Introduction
In the portable & hand held devices such as mobile phones used today requires long battery life. For that purpose low power architectures are required in VLSI Design.This field of VLSI is known as Low Power VLSI Design.Using the majority gates one can implement the AND function.In the present paper design & implementation of majority gate is done on FPGA.To check the functionality Simulation is done on Altera Modelsim 6.4a (Quartus 2 9.0).Now to decides the technology of implemented design Synthesis is done. The another application of majority gate is QCA (Quantum Cellular Automata) used in Nanotechnology for low power.
Experimental Result:
To check the functionality simulation is done on Modelsim 6.4a and to check the tradeoff between the area and power consumption various FPGA Architectures are used.
Encoding: Input Output 0000 0 0001 0 0010 0 0011 1 0100 0 0101 1 0110 1 0111 1 1000 0 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 1
The encoding for the four bit binary number is shown in the following table. In the following table if the number contains equal number of zero and ones then according to the driving strength of the signal 1 is transferred at the output. The designing is done in Verilog HDL (Hardware Description Language).
Simulation Result
To check the functionality simulation is done in modelsim 6.4a (Quartus 2 9.0).
Here when clk becomes negative edge triggered then the applied input is transferred to the output. Here the operating frequency of the clock is 0.1GHz i.e a time delay of 10ns.Here the setup time of the clock is 3.069ns & the hold time is 6.788ns.Here the fanout of the clock is 1.
Here the gate delay is 6.788ns & net delay is 5.753ns & the routing delay is 1.035ns.After observation we found that clock latency is 10.
Synthesis
To generate the netlist (electrical connectivity of the circuit) synthesis is done using Xilinx ISE 9.2i.Synthesis is done on Spartan2 FPGA with xc2s15 device and cs144 package with speed grade -6.Finally the architecture is implemented on 0.18µm CMOS Technology i.e the gate length of each transistor inside the IC package is 0.18 µm. The package contains 5 bonded IO & the gate count is 14.
Chip Floorplan
Chip Design
Power Report
Extraction of Parasitics
Based on the synthesis results the parasitic Resistance, Capacitance, Inductance of the package is as follows R_pkg=145.6mΩ
C_pkg=1.70pF L_pkg=2.45nH
After designing the final chip DRC (Design Rule Check) is run. During the DRC no errors are found i.e the final design (layout) is correct.
Area/Power Consumption Tradeoff
FPGA Type Sparta n2 Sparta n 3 Spartan3 E Virte x Virtex 2 Virtex2P ro Virtex 4 Virtex 5 Virtex E
LUT 1 1 1 1 1 1 1 1 1
Slices 1 1 1 1 1 1 1 1 1
Gate Count 14 17 17 14 17 17 14 7 14
JTAG Gate Count
288 288 288 288 288 288 288 288 288
Power
Consumption(m w)
Conclusion
The area of the design is depends upon the gate count.Here as shown from the table Virtex5 FPGA contains only 7gates to implement 4 input majority logic. Now Virtex & Virtex E FPGA provides Low power consumption & Low gate count i.e. low chip area. If the chip area is low then fabrication cost becomes low. In future design can be implemented for high speed i.e. for clock frequency.
References
[1] V.Bertacco, “Decision Diagram and Pass Transistor Logic Synthesis,”Proc.of theACM/IEEE International Workshop on Logic
Synthesis, May 1997, pp.1-5.
[2] L.Benini, G.D., Micheli, “Dynamic Power Management,” 1st ed.Springer, Nov 1997, pp.24-25.
[3] http://www.synopsys.com/Tools/TCAD/Device Simulation, accessed June 1, 2009
[4] C.Winstead, “C-element multiplexing for Fault -tolerant logic circuits,”IET Electron,Lett., vol.45, no.19, pp.969-970, Sep. 2009.
[5] Kwon, O., K. Nowka and E.Swartzlander,2000. “A 16x16 bit MAC design using fast5:2 compressor”, Proc.IEEE Int.
