Carrier transport and impact of series resistance

The impacts of device geometry and germanium concentration on the current flowing through the NWs will be discussed. We will also show that a correction of the measured drain current is necessary in order to mitigate the strong influence of series resistance (RSD).

3.3.2.1 Hole carrier transport and mobility

For parameter extraction, the geometrical factor (fg) is normally equal to W/L where W and L represent the width and length of the transistor. In order to take into account the real value of the drain current in our parameter extractions, we considered that fg is equal to number of nanowires that are vertically stacked multiplied by weff/L (here 3×(weff/L)). The extractions of μ0, VT are done using the Y- function method [9]. Other parameters such as subthreshold swing S and series resistance RSD can also be extracted as documented in chapter II.

Table IV-8 shows the geometry, the Ge concentration (Ge %) and the extracted low-field mobility of holes (μp). Superior hole mobility values were obtained in the nanowire with a higher Ge (100 %) concentration, i.e. narrow width (wdes =50 nm). This result is in agreement with previous data obtained for SiGe thin films on insulator [34]. It suggests that hole transport is primarily dominated by the material nature (Ge) rather than by the interface traps, the density of which can increase in nanowires with smaller diameter [40]. In principle, the interface between Ge enriched NW and the surrounding silicon oxide has high quality because SiO2 was grown during the Ge condensation, with a dry oxidation process and high temperature. Therefore, the density of states at the interface is presumably low and does not affect the channel conduction.

Table IV-8: Geometry and electrical properties of SiGeC vertically stacked 3-level nanowires in a single row.

Per NW 3-level NWs @ VG =-10 V

L

(nm) wdes

(nm) weff

(nm)

Ge

() µp

(cm²/V.s) ID

(nA)

100 50 9 100 80 390

100 100 60 40 14 450

500 100 60 40 34 230

The values of the weff and the Ge concentration were taken from [41] after investigation by SEM and EDX studies, respectively. The relatively low values of extracted mobility are explained by the difficulty to determine the precise effective width and also by the fact that the series resistance in these samples is very high (due to undoped source and drain). Using the experimental θ1 values, we can estimate the series resistance to about 60 kΩ for wdes =100 nm and L=100 nm.

Another way to validate our experimental results is suggested by the drain current formula. The drain current should be proportional to the aspect-ratio multiplied by the mobility. We know that the mobility is Ge-concentration dependent, so the drain current should be roughly proportional to Ge concentration multiplied by 3×(weff/L). Figure IV-21 shows that this proportionality is qualitatively verified. We used here experimental values of drain current measured for -10 V on the back-gate (strong accumulation).

Figure IV-21: ID measured at VG =-10 V as a function of (3×weff/L) multiplied by Ge-concentration.

All extracted parameters suffer from an unknown information: where is the dominant current flowing through? Normally, we have parallel conduction through multiple stacked nanowires with different gate dielectric thicknesses. As a consequence, a variable oxide capacitance should be seen by each NW: the stacked parallel channels should exhibit different threshold voltages. However, multiple threshold voltages could not be evidenced from the experimental curves: when plotting the second derivative of current with respect to gate voltage (Figure IV-22), we obtained one peak, not multiple peaks (which would be the signature of multiple VT). We explain this result by the thickness of the buried oxide which is much larger than the inter-wire separation. In our experimental conditions, the threshold voltage measurement cannot confirm whether the drain current flows mainly through the lowest nanowire or through several stacked nanowires, which are simultaneously unblocked by the field effect.

Figure IV-22: Second derivative of drain current with respect to gate voltage versus gate voltage for a nanowire with wdes =100 nm and L=100 nm. The peak positions indicate the threshold voltage and the flat-band voltage. These values confirm the ones obtained by the Y-function method.

3.3.2.2 Impact of series resistance

The series resistance is significant in this nanowire configuration because the source/drain stacks are not doped. Furthermore, the undoped nature of source/drain suggests that a field effect might also be present in source and drain stacks. This phenomenon was explored by conducting -MOSFET experiments on the source stack only (Figure IV-23a). Figure IV-23b confirms that the current through the source stack is depending on the gate voltage. The contribution of the gate-dependent series resistance has not been taken into account in the extracted values of mobility presented above. The series resistance effect is complicated due to the contributions of the vertical current flow in the source/drain terminals (through the Si/SiGe super- lattice) and horizontal flow (along the SiGe layers contacting the NWs).

The average value of the nanowire series resistance is found to be higher for SiGe (≈2×10⁶ Ω) than for SiGeC (≈4×10⁴ Ω): series resistance in SiGe exceeds by about two orders of magnitude that in SiGeC NWs. The RSD values were extracted using equation (II-13) illustrated in chapter II.

To clarify the effect of series resistance, we corrected the drain current by the voltage drop on RSD =RS +RD for SiGe NWs using the equation below detailed in [42]:

( ) (IV-10)

Figure IV-23: (a) Schematic view of the pseudo-MOSFET measurement on the contact stack: probes are placed on the same contact pad. (b) Drain current versus back-gate voltage in double sweep mode (forward and backward) for the SiGeC-Si super-lattice.

Figure IV-24a shows a comparison between ID before and after correction for SiGe NWs. The corrected current is much higher than the measured one for both positive and negative back-gate voltage. This confirms our expectations about the strong RSD consequence on SiGe NWs. The mobility extracted after correction is almost six times larger. For SiGeC NWs no variation was obtained between corrected and non-corrected drain current (Figure IV-24b); this result points out low value of RSD.

Figure IV-24: Drain current versus back-gate voltage (a) for a SiGe-based NW and (b) for a SiGeC- based NW before and after correction of series resistance. VD =0.2 V, L=100 nm and wdes =100 nm.