ELTRAN

The Epitaxial Layer TRANsfer (ELTRAN) technique is another approach that combines the formation of a porous layer and wafer bonding to produce a material with good film thickness uniformity. This technique was developed by Canon in 1990

A donor Si substrate ‘Wafer A’ undergoes an electrolytic attack making the Si surface porous (Figure I-13). Two successive epitaxial steps, first of porous silicon followed by single-crystal silicon allow forming a layer of non-porous silicon with high crystalline quality. The porous silicon wafer with the epitaxial layer film is then oxidized and bonded to another wafer ‘Handle Wafer’. The fracture is made by means of a high-power water jet along the planar porous layers which are mechanically more fragile, leading to a more uniform cleavage. After wafers splitting, the residual porous Si on the SOI wafer is etched away, and the newly exposed SOI wafer surface is smoothed by a second application of hydrogen annealing at about 1100°C.

The wafer ‘A’ that donated the epitaxial film can be reclaimed, polished if necessary, and then reutilized. The crystal quality of the SOI material obtained by wafer bonding and etch-back is, in principle, as good as that of the starting silicon wafer. The control of film thickness is challenging.

Figure I-13: Schematic representation of ELTRAN process for SOI wafer manufacturing [34].

2.2.2.3 Unibond (Smart-Cut^TM process)

In the 1990s, a revolutionary process of wafer separation, named Smart- Cut^TM, was invented by Michel Bruel from CEA-Leti (France-Grenoble) [35] and constitutes the technological exclusivity of the company Soitec (France-Bernin). The key step of the Smart-Cut^TM process is the implantation of hydrogen for splitting the wafers (Figure I-14).

First the ‘donor wafer’ A undergoes a thermal oxidation to form an oxide which will serve as a BOX. Its thickness is easily adjustable by the control of oxidation. Then, a dose of hydrogen between 3×10¹⁶ and 1×10¹⁷ cm^-2 is implanted through this oxide. The hydrogen engenders micro-cavities (zone in dashed lines on Figure I-14). These are going to allow defining a plan of the fracture. The ‘donor wafer’ and ‘Handle wafer’ B are then cleaned to eliminate particles and contaminations on surface. This stage also allows returning both surfaces hydrophilic. The two wafers are aligned and putted in contact so that the bonding is made on the entire surface. During the bonding of wafers A and B (Figure I-14) and of the annealing that follows, the pressure of hydrogen molecules (H2) in micro-cavities increases. H2 propagates then in micro-cavities and provokes a horizontal fracture which leads to a natural separation of wafers. This separation takes place, not at the bonding interface, but in the region defined by the localization of hydrogen micro- cavities.

Figure I-14: Schematic illustration of the fabrication steps for a standard Unibond SOI wafer with Smart-Cut^TM process described by Soitec [36].

After this step, the surface roughness is of the order of some nanometers. It is important to underline that one of the advantages of this technique is to be able to reuse wafer A: the process is called “refresh”.

To improve the crystalline quality of the transferred layer, some fracture processes use at present the co-implantation of hydrogen-helium. The implanted

fills the voids and provides most of the pressure that causes separation of a Si film from the bulk substrate. In addition, the helium improves the quality of the fracture.

A better quality of the film and a reduction in the production cost are obtained.

The extraordinary potential of the Smart-Cut^TM approach is evidenced by several essential key benefits [5]:

i. The thinning step can be achieved without any limitations.

ii. The donor wafer (A) undergoes only the removal of a thin Si surface layer and can be recycled several times. The quality of this mother wafer must be excellent, while that of the wafer B, used primarily for mechanical support, is not critical. Therefore, the Smart-Cut^TM is almost mono-wafer, with a low cost for the wafer B. This translates into competitive production costs.

iii. Conventional implantation and annealing equipments are used, even for the manufacturing of 12 inch wafers, which is not the case of SIMOX where only maximum 8 inch wafers can be obtained.

iv. The silicon film and the BOX thicknesses are adjustable (via the implantation energy of hydrogen and oxidation time) in a wide range (tSi =0.01 to 1.5 microns and tBOX =0.01 to 5 microns) in order to adapt to most architectures of integrated components: ultra-thin CMOS, power transistors or sensors with thick films.

v. The crystal quality, defect density and characteristics of the Si film are excellent, while the buried oxide keeps the usual properties of the thermal oxide. The fact that the bonding interface is below the BOX improves the Si film quality.

The Smart-Cut™ wafer manufacturing technology gives Soitec the flexibility to tailor SOI substrates to meet most demanding design specifications and to cover the full range of applications for microelectronics markets (Figure I-15). Note that the Smart-Cut^TM is universal in the sense of adaptability to a variety of materials. These new products (showed in the next section) allow Soitec to answer the expectation of the microelectronics market subjected to the technological nodes defined by the ITRS (International Technology Roadmap for Semiconductors) and to invest new market

Figure I-15: Soitec’s Unibond SOI wafers with wide flexibility in top Si and buried oxide thicknesses to meet the industry's most rigorous requirements [37].