In the first part, we will introduce SOI technology and transistor structures fabricated on SOI substrate. In the second section, state-of-the-art SOI material technology and fabrication methods are discussed.
SOI devices
- SOI technology: an answer to scaling and diversity in Moore’s law
- Advantages of the SOI technology
- SOI MOSFETs
- Partially depleted transistors: PD MOSFETs
- Fully depleted transistors: FD MOSFETs
- Innovative SOI transistors
- Multi-gate transistors
- Gate-All-Around (GAA) transistors
- Tri-dimensional nanowires (3D NWs)
The Gate-Induced Floating Body Effect (GIFBE) effect [12] occurs for very thin gate oxides and at strong gate voltage; the leakage currents through tunneling effect can be important, leading to body scratch, a variation of the film potential (even for low drain current) and an increase in the drain current. Unlike PD technology, full depletion appears when the depletion regions cover the entire transistor body (i.e., the film thickness).
SOI materials
State-of-the-art
Fabrication methods
- SIMOX technology
- SOI by wafer bonding
- BESOI
- ELTRAN
- Silicon-On-Nothing (SON)
- Other SOI technologies .1 Silicon-On-Sapphire
In addition, it enabled the drastic limitation of the dislocation density (reduced to 106 cm-2) in the Si layer (with thickness between 170 and 215 nm) [26]. In the case of the SOI (Figure I- 11aA), we have one substrate with oxidized surface (which will later represent the insulator) and another substrate (with or without surface oxidation).
Novel semiconductor on insulator structures
- Strained SOI materials
- Hybrid orientation technologies
- Germanium-On-Insulator
- Other semiconductor, BOX and substrate materials
After integrating the first layer of the active circuits on SOI, the growth steps can be repeated several times. The strained Si film is grown epitaxially on relaxed Si1-xGex; the degree of elongation achieved is a function of the germanium percentage (Ge %) [43].
Defects of SOI material
Taniguchi, “Analysis of kink characteristics in silicon-on-insulator MOSFETs using two-carrier modeling,” Electron Devices, IEEE Transactions on, vol. Monfray, "Silicon-on-Nothing (SON) - an innovative process for advanced CMOS," Electron Devices, IEEE Transactions on, vol.
Pseudo-MOSFET principle and operation
- Overview
- Point-contact -MOSFET technique
- Sample preparation
- Typical I D -V G in -MOSFET configuration
- Substrate effect
- Influence of probe pressure
- Extraction methods of the electrical parameters
- Threshold voltage and flat-band voltage
- Carrier mobility
- Mobility reduction factor and series resistance
- Subthreshold swing and interface traps density
- Impact of the top interface in thin SOI films
- Revisited -MOSFET models
This effect is due to the variation of series resistances with probe pressure. In the case of the -MOSFET, where the BOX is thick enough, the second mobility attenuation factor (θ2) is negligible because it appears only at very high gate voltage (very strong inversion).
Characterization of ultra and extra thin SOI wafers
Experimental conditions
- Sample preparation
- Measurement system
The wafer is etched in silicon islands that are isolated from the edges where a leakage current can occur between the gate and the electrodes, which will degrade the measured electrical properties. The wafer is coated with a photosensitive resist using a spin coater with a preset speed to achieve uniform distribution on the wafer surface. The wafer undergoes a Reactive Ion Etching (RIE), which frees silicon islands with a slight over-etch.
This station has undergone some modifications by connecting the chuck to a triaxial connector to engage the rear port substrate.
Results obtained on UT/ET SOI
After validating the -MOSFET characteristics for 25 nm BOX with 88 nm film, for the first time we characterized the extra thin layer (12 nm) of silicon with the same BOX thickness (25 nm). Successful ID-VG curves are shown in Figure II-16a and gm-VG curves in Figure II-16b. A similar behavior is observed in comparison to Figure II-15, although the benefit of surface passivation is pronounced.
The equations used before to extract the electrical parameters did not take into account the substrate under the BOX.
Low-temperature -MOSFET measurements
- Interest of low-temperature measurements
- Experimental set-up
- Drain current variation with temperature
- Extracted parameters
- Carrier mobility
- Subthreshold swing and threshold voltage
We will discuss the impact of the top interface on the extracted parameters below. The -MOSFET measurements are promising because the evolution of the curves with temperature is qualitatively correct. The relative contribution of these three scattering mechanisms depends on the temperature and on the concentration of the carriers in the channel.
The effect of the passivation of the top interface on the electrical behavior of the SOI wafer was shown.
Low-frequency noise measurements on bare SOI wafers
- Why noise measurements?
- Overview of the electronic noise
- Fundamentals of noise
- Different sources of noise in MOS transistor
- LFN on SOI wafers
- LFN in -MOSFET: experimental set-up
- Experimental results
- Conclusion of section 1
McWhorter proposed that the fluctuation of the drain current is due to the fluctuation of the charge cell number in the channel near the semiconductor/oxide interface [10]. This modification of the charge trapped in the oxide (δQox) is associated with a change of VFB [12]. The frequency-independent curve confirms the correctness of the CNF model of 1/f noise in thick films.
No probe pressure dependence of the noise is observed at least in non-passivated samples.
Split C-V measurement in -MOSFET configuration
- Split C-V technique and principle
- Interest of split C-V for SOI wafer characterization
- Extension of -MOSFET for split C-V measurements
- Method and experiment
- Experimental C-V curves
- Impact of experimental conditions on C-V measurements
- Probe pressure impact on C-V curves
- Frequency effects
- Extraction of μ eff by split C-V technique
- Adapted methodology to extract μ eff
- Applications of μ eff extraction for advanced SOI structures
- Conclusion of section 2
The schematic of the measurement system and the equivalent circuit is shown in Figure III-10. A Cp-G model is used to eliminate the dispersive effect of the resistance (R=1/G) in the capacitance curves. Then the capacitance increases reflecting the gradual build-up of the inversion or accumulation channel.
Therefore, the effective area covered by the carriers will be lower, leading to a reduction in total capacity [29].
Characterization of heavily doped SOI wafers
From undoped to doped SOI
- Y-function
The drain current and transconductance curves in HD SOI have clear variations between 0 to +40 V and 0 to -40 V, revealing two types of conduction mechanisms. The superlinear curves in Figure IV-1b indicate that an accumulation channel is activated (0 to +40 V for As-implanted and P-implanted samples and 0 to -40 V for B-implanted samples). However, the heavily doped films cannot be completely depleted: there is no zero current region at VG ≈0 V as with undoped SOI (Figure IV-1a @ VG = 0 V).
In Figure IV-3a, the linear form of the Y vs. VG function [9] for undoped SOI wafers allows us to derive the main parameters: VFB and µp for holes; VT and µn.
Revised model for parameter extraction in HD SOI
- Volume conduction
- Surface accumulation
- Extracted parameters
A comparison of the results between the Hall effect -MOSFET and the four-point probe follows in the next section. However, a comparison of the -MOSFET and the Hall effect provides additional information about the scattering mechanisms. The results for doping concentration and mobility extraction show a convincing match between the -MOSFET and the Hall effect.
It follows that the -MOSFET can be replaced by more tedious, time-consuming Hall effect measurements.
SOI-based sensor for gold nanoparticles detection
SOI as a detection platform
Another application was explored by grafting a monolayer of molecules (Figure IV-8b) with electron-donating abilities onto the SOI surface [20]. The results show a shift of the threshold voltage that allows the opening of a channel in the silicon film. Both studies presented above suggest that the -MOSFET can be easily used for detection functions, which is indeed an exotic application.
Furthermore, Ionica et al showed that the -MOSFET configuration can be easily used for biological and chemical detection purposes (i.e., for biosensor applications as "conjugate carriers") [21].
Gold nanoparticles detection by -MOSFET
- Fabrication steps of SOI sensors
- Sensor response
To test the reproducibility of the technological process, two samples were processed with the same technological parameters (APTES concentration and time, gold deposition time). The rightward shift of the curve after gold deposition is consistent with theoretical expectations for negative surface charge. The proportionality of the response was tested on SOI with 20 nm film and BOX thickness of 145 nm.
The larger shift of the curves for thinner films implies an improvement of the sensitivity.
Conclusion of section 2
Overview
For example, the best possible electrostatic control and immunity to short-channel effects can be achieved by using GAA nanowire-based transistors [32]. Again, one of the critical issues in Ge nanostructures is the low level of drain current that can be supported. Tilt SEM images after release of stacked NWs for (b) 2X laterally arrayed tri-stacked NWs, (c) 2X laterally arrayed 4-stacked NWs, and (d) 5X laterally arrayed 4-stacked NWs [ 35].
We proposed a nanowire characterization technique prior to gate processing in order to qualify the quality of these structures (in Section 3.3).
Fabrication process
The SiGe beams are then enriched by Ge condensation below 900◦C in dry oxygen (Figure IV-14d) in order to increase the Ge content and achieve near-pure Ge, between the structures by consuming Si during the oxidation process. In this case, the selective etching used to release the nanowires is more stable and avoids bending of the structures. Before moving on to the electrical characterization, let us give an important detail about the geometry of the structures.
The effective width (weff) of the Ge-enriched channel is smaller than the designed width (wdes) as shown in Figure IV-17.
Electrical transport properties of SiGe NWs
- Basic characteristics
- Carrier transport and impact of series resistance
- Low-temperature measurements
- Multiple parallel NWs at 300 K
A special feature of both graphics (Figure IV-19a & Figure IV-19b) is the possibility to activate the drain current with positive and negative feedback voltages. To document this enigmatic ambipolar conductance, in Fig. IV-20 we show the drain current versus reverse gate voltage (ID-VG) curves obtained for two 100 nm long structures, one with a design width of 100 nm (Fig. IV-20a) and the other 50 nm (Figure IV-20b). We will also show that correction of the measured drain current is necessary to mitigate the strong influence of series resistance (RSD).
We used here experimental values of drain current, measured for -10 V on the back gate (strong accumulation).
Conclusion of section 3
Cristoloveanu, "Detailed investigation of a pseudo-Mos transistor for in situ characterization of solar wafers," at the SOI conference, 1992. 34; Electrical transport at room and low temperature in 3D vertically stacked SiGe and SiGeC nanowires," Journal of the Electrochemical Society, vol. The effect of top interface defects on the oscillation and threshold voltage is more pronounced in the.
Displacements are related to the change in surface potential (charge density) on the surface, i.e.
Journal publications
International conference papers
Cristoloveanu, “Detection of gold nanoparticles using an intrinsic SOI-based sensor,” Nanotechnology (IEEE-NANO), Portland, USA, p. , Proc. Cristoloveanu, “Advances in the Pseudo-MOSFET Characterization Method”, IEEE Semiconductor Conference (CAS), Sinaia, Romania, p.
Published book chapter
National conference papers
Title: Novel pseudo-MOSFET methods for the characterization of advanced SOI substrates
Titre: Nouvelles méthodes pseudo-MOSFET pour la caractérisation des substrats SOI avancés
French thesis summary
Introduction générale
Le matériau SOI fabrication et caractérisation
- Le procédé Unibond (Smart-Cut TM )
- La technique pseudo-MOSFET
- Extraction des paramètres électriques
- Caractérisation des plaques SOI très minces
Un canal conducteur est créé à l'interface film/BOX via la polarisation du substrat VG, et des zones de défauts sont créées par la pénétration de la pointe dans le film de silicium. L'intersection de la partie linéaire de Y avec l'axe des abscisses (VG) donne les valeurs VT et VFB (Figure 4a). Pour déterminer la mobilité à faible champ des électrons et des trous, nous utilisons la pente d'une partie linéaire de la fonction Y (Figure 4a).
Les résultats de la figure 5 sur la passivation de surface pour un oxyde mince enfoui (25 nm) confirment ceux obtenus pour un oxyde épais (145 nm) [13].
Partie II: Nouvelles techniques de caractérisation des plaques SOI
Mesures -MOSFET à basse température
Dans la région de VG positif, le courant de drain diminue avec l'augmentation de la température, là où domine l'évolution de la mobilité avec la température. L'échelle semi-logarithmique des courbes de débit (Figure 7a) montre une augmentation de la pente dans le régime d'inversion faible avec une diminution de la température. Les VG (Figure 7b) montrent qu'avec une diminution de la température, le pic de gm augmente (pour VG> 0) en raison de l'amélioration de la mobilité à basse température.
Les résultats des figures 8a et 8b montrent la dépendance de la mobilité à faibles champs sur la température pour les électrons et les trous, respectivement.
Mesures de bruit à basse fréquence
Dans son modèle, le bruit 1/f du courant de drain est un phénomène de volume dû aux fluctuations de la mobilité des porteurs dues aux collisions avec les phonons [22]. Dans les films très fins (12 nm), l'impact de la surface supérieure sur le bruit du canal enterré (à l'interface film-BOX) est plus important que dans les films plus épais (88 nm). Un bruit excessif peut être généré sur la surface libre de la plaquette SOI (interface Si/air).
Nous avons également étudié l’effet de la passivation de la surface des plaques sur les résultats sonores.
Mesures split C-V
En plus de mettre en œuvre cette méthode de mesure, nous avons également démontré que le bruit n’est pas affecté par la pression de la pointe. Ensuite, la capacité augmente en raison de l’accumulation progressive de la couche d’inversion ou d’accumulation. Cette technique directe est utilisée pour évaluer les courbes μeff (Qinv, acc) à partir de mesures C-V divisées.
Après avoir démontré la faisabilité de la mesure et validé la technique d'extraction de mobilité sur différentes géométries d'échantillons, nous nous sommes intéressés à des études plus subtiles, comme le développement et la validation d'un modèle physique pour étudier la variation de la valeur maximale de la capacité avec la fréquence ou de la passivation des surfaces des échantillons.
Conclusion générale
