position. The aggressor and victim signal values for the current state are generated (see Figure III-6) on the PA
and PV outputs. In Figure III-8, the nine-state FSM that generate the shift control signal and the aggressor- victim signals is represented.
S0
S1 S2
S3
S5 S6
S7 S8
S4
START=’1’
END=’1’
END=’0’
PV=’1’
PA=’1’
SHIFT=’0’
PV=’1’
PA=’0’
SHIFT=’0’
PV=’0’
PA=’1’
SHIFT=’0’
PV=’1’
PA=’0’
SHIFT=’0’
PV=’1’
PA=’1’
SHIFT=’0’
PV=’0’
PA=’1’
SHIFT=’1’
PV=’0’
PA=’0’
SHIFT=’0’
PV=’0’
PA=’0’
PV=’0’
PA=’0’
SHIFT=’0’
Figure III-8 FSM for generating aggressor / victim test signals
In the idle state S0, the inter-die 3D NoC link is in normal operation mode. When the interconnect test phase is initiated (i.e. START=’1’), the shift counter indicates the first victim set V1 and the FSM transitions to state S1. In this state, PV=’0’ is sent on all victim TSVs in V1 and ‘0’ is sent on aggressor TSVs. Then, the FSM will perform transitions from S1 to S2, then from S2 to S3 and so on, until it arrives in S8. In each of these states, the enable signal of the counter is ‘0’ and the aggressor-victim signal values are sent out on PA
and PV, according to the eight vector values in Figure III-6. When the S8 state is reached, the shift counter status is checked. If the shift counter has finished counting the victim sets, then the END signal is set to ’1’
and the FSM performs the S8 to S0 transition. Otherwise, for the currently active victim set Vi, the counter value increments, SHIFT=’1’ (i.e. CNTi=’0’ and CNTi+1=’1’), and the FSM goes through the S1-S8 states again for the next victim set Vi+1.
The delay of the KAF-based IBIST circuitry represented in Figure III-2 comprises the TPG delay (i.e.
3FSM+3MUX), the 2:1 MUX delay 3MUX, the interconnect and buffer delays 3WIRE, and the RA cell delay 3RA= 3FF+3XOR+3OR. Hence, tests can be performed at high clock rates. For example, in a 65 nm low-power technology, the IBIST can be clocked at 2 GHz.
The difficulty in applying the KAF model is that the aggressor order must be determined for each TSV technology such that there is no fault coverage loss and the test times are minimal. An improvement of this implementation consists in modifying the test generation strategy with capabilities to perform tests for different aggressor orders. In the following section, a configurable KAF-based TPG implementation is presented.
3.3.2 Configurable KAF-based Test Patterns
Under-estimating the K-order reduces test duration, but fault coverage is reduced, as shorts between victim TSVs of the same set are not detectable. If higher aggressor orders are used then there are more victim TSV sets. However, the longer test sequence generated for higher aggressor orders may not sensitize more delay faults due to crosstalk. In this section, the implementation of configurable KAF-based TPGs is presented. The
test logic can be configured during system lifetime with different TSV victim sets by adjusting the aggressor order with a value K ranging from KMIN to KMAX. The configurable KAF-based TPG architecture is shown in Figure III-9.
FSMwMAX-positions Shift Counter
BN
B2
B1 …
TSV1
SHIFT END PV
PA
START
TSV2
TSVN
Crossover Switch
Configuration Logic
K
w
Mij
CNT0
CNTwmax
CNT1
…
Figure III-9 Configurable KAF pattern generator
During interconnect tests, the aggressor or victim signal sent on each TSV is determined using shift counters that indicate the active victim set Vi. Given the maximal aggressor order KMAX, the N TSVs are partitioned in maximum wMAX of victim subsets (V1,…,VvMAX). Thus, a programmable shift counter with wMAX
positions (CNT1-CNTwmax) is used in order to indicate the active victim set. For an aggressor order K, the number of victim sets w is determined by the Configuration Logic block.
When the TSVs are partitioned in victim sets using the algorithm in Figure III-4, it is possible that some wires TSVi are in the nth partition for an order K1 and in the mth partition for a different order K2. Thus, the behavior of TSVi (i.e. value of signal Bi) is given by the counter’s nth position in the first case and on the mth position in the second case. To illustrate this, let us consider a 4×4 TSV array. In Figure III-10, the victim sets are represented for the first K=1 (a) and second K=2 (b) aggressor orders.
TSV1 TSV2 TSV3 TSV4
TSV5 TSV6 TSV7 TSV8
TSV9 TSV10 TSV11 TSV12
TSV13 TSV14 TSV15 TSV16
(a)
V1
V2
TSV1 TSV2 TSV3 TSV4
TSV5 TSV6 TSV7 TSV8
TSV9 TSV10 TSV11 TSV12
TSV13 TSV14 TSV15 TSV16
(b)
V1
V2
V3
V4
V5
V6
Figure III-10 Victim subsets for 4x4 TSVs for K=1 (a) and K=2 (b) aggressor orders
From these plots it can be seen that, for K=1 and K=2, some TSVs are in different victim sets. For example, TSV5 is in the second victim subset for K=1 and it is in the third victim subset for K=2, while TSV1
and TSV16 remain in the same group. The behavior of TSV5 is given by the first position of the counter for K=1 and by the third position for K=2.
The counter position selection process is done for each wire TSVi by a crossover switch whose inputs are the counter positions CNT1-CNTwmax and whose outputs are the TSV victim-aggressor control signals Bi. For each wire TSVi, the victim signal PV is sent if Bi=’1’, and the aggressor signal PA is sent if Bi=’0’. The crossover switch is implemented using MUXes or arrays of switching elements controlled by the matrix control signal M. For each valid CNTi-Bj signal pair (i.e. there is an aggressor order for which TSVj is in Vi) there is a unique select signal Mi,j. When Mi,j is active, the input signal CNTi is mapped on output Bj. The crossover switch control signals Mi,j are determined by the Configuration Logic block. This block is implemented using truth tables that have the aggressor order K as input.
For the 4×4 TSV bundle, the crossover switch must be able to map the counter positions CNT1-CNT6 to the MUX selection signals B1-B16 of each wire TSV1-TSV16. Let us consider that the TPG can generate test patterns for the 1st and 2nd aggressor orders. In this case, the signal sent on each TSV is determined by the counter register (i.e. the current victim according to the partitioning in Figure III-10). The mapping process of victim / aggressor signals on TSVs (i.e. MUX selection signals B1-B16) is performed by the crossover switch represented in Figure III-11.
CNT1 CNT2
CNT3 CNT4 CNT5 CNT6
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16
M1,1
M2,2
M1,3
M3,3
M1,4
M2,4 M2,5
M3,5
M1,6
M4,6
M2,7
M5,7
M1,8
M2,8
M1,9
M2,9
M1,11
M2,10
M1,10
M6,11
M2,12
M3,12
M2,13
M4,13
M1,14
M3,14
M2,15
M1,16
Figure III-11 Crossover switch structure for 4x4 TSVs having K=1 (w=2) and K=2 (w=6) aggressor orders
In the example above, TSV5 is in the second and third victim sets for K=1 and K=2, respectively. In Figure III-11 there are two switching elements, one of which is active at a time, that connects B5 to CNT2 and to CNT3, respectively. Similarly, B10 is connected to CNT2 and CNT1 such that M2,10=’1’ for K=1 and M1,10=’1’
for K=2.
A benefit of the configurable TPGs is reduced interconnect test duration during system lifetime. For example, initial tests could be performed with the highest aggressor order KMAX in order to detect all possible errors. Then, in order to reduce link off-line duration due to tests, the aggressor order can be gradually reduced KMIN. For example, M TSV interconnect test phases performed for an aggressor order K1 require 82M2w1
cycles, where w1 is the number of victim sets. However, if m of these test phases are performed for a lower aggressor order K2 then the test duration is reduced by 82m2(w1-w2) cycles, where w2 represent the number of victim sets for K2.
The configurable KAF-based IBIST delay comprise the TPG delay (i.e. 3FSM+3MUX), the 2:1 MUX delay 3MUX, the interconnect and buffer delays 3WIRE, and the RA cell delay 3RA= 3FF+3XOR+3OR. These delays do not comprise the Configuration Logic and crossover switch delays, as the input signal K is constant during the
TSV test phase. Therefore, high-speed configurable IBIST implementations are possible. For a 65 nm low- power technology, the configurable IBIST can be clocked at frequencies as high as 2 GHz.